x86: apic - unify clear_local_APIC

- Remove redundant masking of APIC_LVTTHMR register in apic_32.c

- Add masking of APIC_LVTTHMR register to apic_64.c. We use a bit
  complicated #ifdef here: CONFIG_X86_MCE_P4THERMAL is 32bit specific
  and X86_MCE_INTEL is 64bit specific so the appropriate config variable
  will be set by Kconfig.

- the APIC_ESR register clearing in apic_64.c now uses not straightforward
  way but this is allowed tradeoff.

Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

1 files changed, 15 insertions, 2 deletions

diff --git a/arch/x86/kernel/apic_64.c b/arch/x86/kernel/apic_64.c
index 99d18b8976a5..d834b7583624 100644
--- a/arch/x86/kernel/apic_64.c
+++ b/arch/x86/kernel/apic_64.c
@@ -630,6 +630,13 @@ void clear_local_APIC(void)
                 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
         }
 
+        /* lets not touch this if we didn't frob it */
+#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
+        if (maxlvt >= 5) {
+                v = apic_read(APIC_LVTTHMR);
+                apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
+        }
+#endif
         /*
          * Clean APIC state for other OSs:
          */
@@ -640,8 +647,14 @@ void clear_local_APIC(void)
                 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
         if (maxlvt >= 4)
                 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
-        apic_write(APIC_ESR, 0);
-        apic_read(APIC_ESR);
+
+        /* Integrated APIC (!82489DX) ? */
+        if (lapic_is_integrated()) {
+                if (maxlvt > 3)
+                        /* Clear ESR due to Pentium errata 3AP and 11AP */
+                        apic_write(APIC_ESR, 0);
+                apic_read(APIC_ESR);
+        }
 }
 
 /**