diff options
author | Cyrill Gorcunov <gorcunov@gmail.com> | 2008-08-16 15:21:51 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2008-08-17 08:41:48 -0400 |
commit | 92206c909ad1d4f9c355b4842722d5a355d6b76b (patch) | |
tree | a27464b6008d77ef5314bd364405d73c5f3a3168 /arch/x86/kernel/apic_32.c | |
parent | 6764014bc8bb4849f6a4f336477e873ad5861ed2 (diff) |
x86: apic - unify lapic_resume
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/apic_32.c')
-rw-r--r-- | arch/x86/kernel/apic_32.c | 29 |
1 files changed, 18 insertions, 11 deletions
diff --git a/arch/x86/kernel/apic_32.c b/arch/x86/kernel/apic_32.c index 3131603a4d6a..3d40213d3af2 100644 --- a/arch/x86/kernel/apic_32.c +++ b/arch/x86/kernel/apic_32.c | |||
@@ -1606,16 +1606,21 @@ static int lapic_resume(struct sys_device *dev) | |||
1606 | 1606 | ||
1607 | local_irq_save(flags); | 1607 | local_irq_save(flags); |
1608 | 1608 | ||
1609 | /* | 1609 | #ifdef CONFIG_X86_64 |
1610 | * Make sure the APICBASE points to the right address | 1610 | if (x2apic) |
1611 | * | 1611 | enable_x2apic(); |
1612 | * FIXME! This will be wrong if we ever support suspend on | 1612 | else |
1613 | * SMP! We'll need to do this as part of the CPU restore! | 1613 | #endif |
1614 | */ | 1614 | /* |
1615 | rdmsr(MSR_IA32_APICBASE, l, h); | 1615 | * Make sure the APICBASE points to the right address |
1616 | l &= ~MSR_IA32_APICBASE_BASE; | 1616 | * |
1617 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | 1617 | * FIXME! This will be wrong if we ever support suspend on |
1618 | wrmsr(MSR_IA32_APICBASE, l, h); | 1618 | * SMP! We'll need to do this as part of the CPU restore! |
1619 | */ | ||
1620 | rdmsr(MSR_IA32_APICBASE, l, h); | ||
1621 | l &= ~MSR_IA32_APICBASE_BASE; | ||
1622 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | ||
1623 | wrmsr(MSR_IA32_APICBASE, l, h); | ||
1619 | 1624 | ||
1620 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | 1625 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
1621 | apic_write(APIC_ID, apic_pm_state.apic_id); | 1626 | apic_write(APIC_ID, apic_pm_state.apic_id); |
@@ -1625,7 +1630,7 @@ static int lapic_resume(struct sys_device *dev) | |||
1625 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | 1630 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); |
1626 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | 1631 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); |
1627 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | 1632 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); |
1628 | #ifdef CONFIG_X86_MCE_P4THERMAL | 1633 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
1629 | if (maxlvt >= 5) | 1634 | if (maxlvt >= 5) |
1630 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | 1635 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); |
1631 | #endif | 1636 | #endif |
@@ -1639,7 +1644,9 @@ static int lapic_resume(struct sys_device *dev) | |||
1639 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | 1644 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); |
1640 | apic_write(APIC_ESR, 0); | 1645 | apic_write(APIC_ESR, 0); |
1641 | apic_read(APIC_ESR); | 1646 | apic_read(APIC_ESR); |
1647 | |||
1642 | local_irq_restore(flags); | 1648 | local_irq_restore(flags); |
1649 | |||
1643 | return 0; | 1650 | return 0; |
1644 | } | 1651 | } |
1645 | 1652 | ||