Merge branch 'linus' into perfcounters/core

Conflicts:
	arch/x86/kernel/irqinit.c
	arch/x86/kernel/irqinit_64.c
	arch/x86/kernel/traps.c
	arch/x86/mm/fault.c
	include/linux/sched.h
	kernel/exit.c

10 files changed, 658 insertions, 595 deletions

diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 60df2efd7c80..076d3881f3da 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -100,6 +100,29 @@ early_param("lapic", parse_lapic);
 /* Local APIC was disabled by the BIOS and enabled by the kernel */
 static int enabled_via_apicbase;
 
+/*
+ * Handle interrupt mode configuration register (IMCR).
+ * This register controls whether the interrupt signals
+ * that reach the BSP come from the master PIC or from the
+ * local APIC. Before entering Symmetric I/O Mode, either
+ * the BIOS or the operating system must switch out of
+ * PIC Mode by changing the IMCR.
+ */
+static inline void imcr_pic_to_apic(void)
+{
+        /* select IMCR register */
+        outb(0x70, 0x22);
+        /* NMI and 8259 INTR go through APIC */
+        outb(0x01, 0x23);
+}
+
+static inline void imcr_apic_to_pic(void)
+{
+        /* select IMCR register */
+        outb(0x70, 0x22);
+        /* NMI and 8259 INTR go directly to BSP */
+        outb(0x00, 0x23);
+}
 #endif
 
 #ifdef CONFIG_X86_64
@@ -113,13 +136,19 @@ static __init int setup_apicpmtimer(char *s)
 __setup("apicpmtimer", setup_apicpmtimer);
 #endif
 
+int x2apic_mode;
 #ifdef CONFIG_X86_X2APIC
-int x2apic;
 /* x2apic enabled before OS handover */
 static int x2apic_preenabled;
 static int disable_x2apic;
 static __init int setup_nox2apic(char *str)
 {
+        if (x2apic_enabled()) {
+                pr_warning("Bios already enabled x2apic, "
+                           "can't enforce nox2apic");
+                return 0;
+        }
+
         disable_x2apic = 1;
         setup_clear_cpu_cap(X86_FEATURE_X2APIC);
         return 0;
@@ -211,6 +240,31 @@ static int modern_apic(void)
         return lapic_get_version() >= 0x14;
 }
 
+/*
+ * bare function to substitute write operation
+ * and it's _that_ fast :)
+ */
+static void native_apic_write_dummy(u32 reg, u32 v)
+{
+        WARN_ON_ONCE((cpu_has_apic || !disable_apic));
+}
+
+static u32 native_apic_read_dummy(u32 reg)
+{
+        WARN_ON_ONCE((cpu_has_apic && !disable_apic));
+        return 0;
+}
+
+/*
+ * right after this call apic->write/read doesn't do anything
+ * note that there is no restore operation it works one way
+ */
+void apic_disable(void)
+{
+        apic->read = native_apic_read_dummy;
+        apic->write = native_apic_write_dummy;
+}
+
 void native_apic_wait_icr_idle(void)
 {
         while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
@@ -350,7 +404,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
 
 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
 {
-        unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
+        unsigned long reg = (lvt_off << 4) + APIC_EILVTn(0);
         unsigned int  v   = (mask << 16) | (msg_type << 8) | vector;
 
         apic_write(reg, v);
@@ -817,7 +871,7 @@ void clear_local_APIC(void)
         u32 v;
 
         /* APIC hasn't been mapped yet */
-        if (!x2apic && !apic_phys)
+        if (!x2apic_mode && !apic_phys)
                 return;
 
         maxlvt = lapic_get_maxlvt();
@@ -1290,7 +1344,7 @@ void check_x2apic(void)
 {
         if (x2apic_enabled()) {
                 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
-                x2apic_preenabled = x2apic = 1;
+                x2apic_preenabled = x2apic_mode = 1;
         }
 }
 
@@ -1298,7 +1352,7 @@ void enable_x2apic(void)
 {
         int msr, msr2;
 
-        if (!x2apic)
+        if (!x2apic_mode)
                 return;
 
         rdmsr(MSR_IA32_APICBASE, msr, msr2);
@@ -1307,6 +1361,7 @@ void enable_x2apic(void)
                 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
         }
 }
+#endif /* CONFIG_X86_X2APIC */
 
 void __init enable_IR_x2apic(void)
 {
@@ -1315,32 +1370,21 @@ void __init enable_IR_x2apic(void)
         unsigned long flags;
         struct IO_APIC_route_entry **ioapic_entries = NULL;
 
-        if (!cpu_has_x2apic)
-                return;
-
-        if (!x2apic_preenabled && disable_x2apic) {
-                pr_info("Skipped enabling x2apic and Interrupt-remapping "
-                        "because of nox2apic\n");
-                return;
+        ret = dmar_table_init();
+        if (ret) {
+                pr_debug("dmar_table_init() failed with %d:\n", ret);
+                goto ir_failed;
         }
 
-        if (x2apic_preenabled && disable_x2apic)
-                panic("Bios already enabled x2apic, can't enforce nox2apic");
-
-        if (!x2apic_preenabled && skip_ioapic_setup) {
-                pr_info("Skipped enabling x2apic and Interrupt-remapping "
-                        "because of skipping io-apic setup\n");
-                return;
+        if (!intr_remapping_supported()) {
+                pr_debug("intr-remapping not supported\n");
+                goto ir_failed;
         }
 
-        ret = dmar_table_init();
-        if (ret) {
-                pr_info("dmar_table_init() failed with %d:\n", ret);
 
-                if (x2apic_preenabled)
-                        panic("x2apic enabled by bios. But IR enabling failed");
-                else
-                        pr_info("Not enabling x2apic,Intr-remapping\n");
+        if (!x2apic_preenabled && skip_ioapic_setup) {
+                pr_info("Skipped enabling intr-remap because of skipping "
+                        "io-apic setup\n");
                 return;
         }
 
@@ -1360,19 +1404,16 @@ void __init enable_IR_x2apic(void)
         mask_IO_APIC_setup(ioapic_entries);
         mask_8259A();
 
-        ret = enable_intr_remapping(EIM_32BIT_APIC_ID);
-
-        if (ret && x2apic_preenabled) {
-                local_irq_restore(flags);
-                panic("x2apic enabled by bios. But IR enabling failed");
-        }
-
+        ret = enable_intr_remapping(x2apic_supported());
         if (ret)
                 goto end_restore;
 
-        if (!x2apic) {
-                x2apic = 1;
+        pr_info("Enabled Interrupt-remapping\n");
+
+        if (x2apic_supported() && !x2apic_mode) {
+                x2apic_mode = 1;
                 enable_x2apic();
+                pr_info("Enabled x2apic\n");
         }
 
 end_restore:
@@ -1381,37 +1422,34 @@ end_restore:
                  * IR enabling failed
                  */
                 restore_IO_APIC_setup(ioapic_entries);
-        else
-                reinit_intr_remapped_IO_APIC(x2apic_preenabled, ioapic_entries);
 
         unmask_8259A();
         local_irq_restore(flags);
 
 end:
-        if (!ret) {
-                if (!x2apic_preenabled)
-                        pr_info("Enabled x2apic and interrupt-remapping\n");
-                else
-                        pr_info("Enabled Interrupt-remapping\n");
-        } else
-                pr_err("Failed to enable Interrupt-remapping and x2apic\n");
         if (ioapic_entries)
                 free_ioapic_entries(ioapic_entries);
+
+        if (!ret)
+                return;
+
+ir_failed:
+        if (x2apic_preenabled)
+                panic("x2apic enabled by bios. But IR enabling failed");
+        else if (cpu_has_x2apic)
+                pr_info("Not enabling x2apic,Intr-remapping\n");
 #else
         if (!cpu_has_x2apic)
                 return;
 
         if (x2apic_preenabled)
                 panic("x2apic enabled prior OS handover,"
-                      " enable CONFIG_INTR_REMAP");
-
-        pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
-                " and x2apic\n");
+                      " enable CONFIG_X86_X2APIC, CONFIG_INTR_REMAP");
 #endif
 
         return;
 }
-#endif /* CONFIG_X86_X2APIC */
+
 
 #ifdef CONFIG_X86_64
 /*
@@ -1428,7 +1466,6 @@ static int __init detect_init_APIC(void)
         }
 
         mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
-        boot_cpu_physical_apicid = 0;
         return 0;
 }
 #else
@@ -1542,32 +1579,49 @@ void __init early_init_lapic_mapping(void)
  */
 void __init init_apic_mappings(void)
 {
-        if (x2apic) {
+        unsigned int new_apicid;
+
+        if (x2apic_mode) {
                 boot_cpu_physical_apicid = read_apic_id();
                 return;
         }
 
-        /*
-         * If no local APIC can be found then set up a fake all
-         * zeroes page to simulate the local APIC and another
-         * one for the IO-APIC.
-         */
+        /* If no local APIC can be found return early */
         if (!smp_found_config && detect_init_APIC()) {
-                apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
-                apic_phys = __pa(apic_phys);
-        } else
+                /* lets NOP'ify apic operations */
+                pr_info("APIC: disable apic facility\n");
+                apic_disable();
+        } else {
                 apic_phys = mp_lapic_addr;
 
-        set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
-        apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
-                                APIC_BASE, apic_phys);
+                /*
+                 * acpi lapic path already maps that address in
+                 * acpi_register_lapic_address()
+                 */
+                if (!acpi_lapic)
+                        set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
+
+                apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
+                                        APIC_BASE, apic_phys);
+        }
 
         /*
          * Fetch the APIC ID of the BSP in case we have a
          * default configuration (or the MP table is broken).
          */
-        if (boot_cpu_physical_apicid == -1U)
-                boot_cpu_physical_apicid = read_apic_id();
+        new_apicid = read_apic_id();
+        if (boot_cpu_physical_apicid != new_apicid) {
+                boot_cpu_physical_apicid = new_apicid;
+                /*
+                 * yeah -- we lie about apic_version
+                 * in case if apic was disabled via boot option
+                 * but it's not a problem for SMP compiled kernel
+                 * since smp_sanity_check is prepared for such a case
+                 * and disable smp mode
+                 */
+                apic_version[new_apicid] =
+                         GET_APIC_VERSION(apic_read(APIC_LVR));
+        }
 }
 
 /*
@@ -1736,8 +1790,7 @@ void __init connect_bsp_APIC(void)
                  */
                 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
                                 "enabling APIC mode.\n");
-                outb(0x70, 0x22);
-                outb(0x01, 0x23);
+                imcr_pic_to_apic();
         }
 #endif
         if (apic->enable_apic_mode)
@@ -1765,8 +1818,7 @@ void disconnect_bsp_APIC(int virt_wire_setup)
                  */
                 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
                                 "entering PIC mode.\n");
-                outb(0x70, 0x22);
-                outb(0x00, 0x23);
+                imcr_apic_to_pic();
                 return;
         }
 #endif
@@ -1972,10 +2024,10 @@ static int lapic_suspend(struct sys_device *dev, pm_message_t state)
 
         local_irq_save(flags);
         disable_local_APIC();
-#ifdef CONFIG_INTR_REMAP
+
         if (intr_remapping_enabled)
                 disable_intr_remapping();
-#endif
+
         local_irq_restore(flags);
         return 0;
 }
@@ -1985,42 +2037,34 @@ static int lapic_resume(struct sys_device *dev)
         unsigned int l, h;
         unsigned long flags;
         int maxlvt;
-
-#ifdef CONFIG_INTR_REMAP
-        int ret;
+        int ret = 0;
         struct IO_APIC_route_entry **ioapic_entries = NULL;
 
         if (!apic_pm_state.active)
                 return 0;
 
         local_irq_save(flags);
-        if (x2apic) {
+        if (intr_remapping_enabled) {
                 ioapic_entries = alloc_ioapic_entries();
                 if (!ioapic_entries) {
                         WARN(1, "Alloc ioapic_entries in lapic resume failed.");
-                        return -ENOMEM;
+                        ret = -ENOMEM;
+                        goto restore;
                 }
 
                 ret = save_IO_APIC_setup(ioapic_entries);
                 if (ret) {
                         WARN(1, "Saving IO-APIC state failed: %d\n", ret);
                         free_ioapic_entries(ioapic_entries);
-                        return ret;
+                        goto restore;
                 }
 
                 mask_IO_APIC_setup(ioapic_entries);
                 mask_8259A();
-                enable_x2apic();
         }
-#else
-        if (!apic_pm_state.active)
-                return 0;
 
-        local_irq_save(flags);
-        if (x2apic)
+        if (x2apic_mode)
                 enable_x2apic();
-#endif
-
         else {
                 /*
                  * Make sure the APICBASE points to the right address
@@ -2058,21 +2102,16 @@ static int lapic_resume(struct sys_device *dev)
         apic_write(APIC_ESR, 0);
         apic_read(APIC_ESR);
 
-#ifdef CONFIG_INTR_REMAP
-        if (intr_remapping_enabled)
-                reenable_intr_remapping(EIM_32BIT_APIC_ID);
-
-        if (x2apic) {
+        if (intr_remapping_enabled) {
+                reenable_intr_remapping(x2apic_mode);
                 unmask_8259A();
                 restore_IO_APIC_setup(ioapic_entries);
                 free_ioapic_entries(ioapic_entries);
         }
-#endif
-
+restore:
         local_irq_restore(flags);
 
-
-        return 0;
+        return ret;
 }
 
 /*
@@ -2120,31 +2159,14 @@ static void apic_pm_activate(void) { }
 #endif  /* CONFIG_PM */
 
 #ifdef CONFIG_X86_64
-/*
- * apic_is_clustered_box() -- Check if we can expect good TSC
- *
- * Thus far, the major user of this is IBM's Summit2 series:
- *
- * Clustered boxes may have unsynced TSC problems if they are
- * multi-chassis. Use available data to take a good guess.
- * If in doubt, go HPET.
- */
-__cpuinit int apic_is_clustered_box(void)
+
+static int __cpuinit apic_cluster_num(void)
 {
         int i, clusters, zeros;
         unsigned id;
         u16 *bios_cpu_apicid;
         DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
 
-        /*
-         * there is not this kind of box with AMD CPU yet.
-         * Some AMD box with quadcore cpu and 8 sockets apicid
-         * will be [4, 0x23] or [8, 0x27] could be thought to
-         * vsmp box still need checking...
-         */
-        if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
-                return 0;
-
         bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
         bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
 
@@ -2180,18 +2202,67 @@ __cpuinit int apic_is_clustered_box(void)
                         ++zeros;
         }
 
-        /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
-         * not guaranteed to be synced between boards
-         */
-        if (is_vsmp_box() && clusters > 1)
+        return clusters;
+}
+
+static int __cpuinitdata multi_checked;
+static int __cpuinitdata multi;
+
+static int __cpuinit set_multi(const struct dmi_system_id *d)
+{
+        if (multi)
+                return 0;
+        pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
+        multi = 1;
+        return 0;
+}
+
+static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
+        {
+                .callback = set_multi,
+                .ident = "IBM System Summit2",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
+                },
+        },
+        {}
+};
+
+static void __cpuinit dmi_check_multi(void)
+{
+        if (multi_checked)
+                return;
+
+        dmi_check_system(multi_dmi_table);
+        multi_checked = 1;
+}
+
+/*
+ * apic_is_clustered_box() -- Check if we can expect good TSC
+ *
+ * Thus far, the major user of this is IBM's Summit2 series:
+ * Clustered boxes may have unsynced TSC problems if they are
+ * multi-chassis.
+ * Use DMI to check them
+ */
+__cpuinit int apic_is_clustered_box(void)
+{
+        dmi_check_multi();
+        if (multi)
                 return 1;
 
+        if (!is_vsmp_box())
+                return 0;
+
         /*
-         * If clusters > 2, then should be multi-chassis.
-         * May have to revisit this when multi-core + hyperthreaded CPUs come
-         * out, but AFAIK this will work even for them.
+         * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
+         * not guaranteed to be synced between boards
          */
-        return (clusters > 2);
+        if (apic_cluster_num() > 1)
+                return 1;
+
+        return 0;
 }
 #endif
 
diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c
index 306e5e88fb6f..d0c99abc26c3 100644
--- a/arch/x86/kernel/apic/apic_flat_64.c
+++ b/arch/x86/kernel/apic/apic_flat_64.c
@@ -161,7 +161,7 @@ static int flat_apic_id_registered(void)
 
 static int flat_phys_pkg_id(int initial_apic_id, int index_msb)
 {
-        return hard_smp_processor_id() >> index_msb;
+        return initial_apic_id >> index_msb;
 }
 
 struct apic apic_flat =  {
@@ -235,7 +235,7 @@ static int physflat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
          * regardless of how many processors are present (x86_64 ES7000
          * is an example).
          */
-        if (acpi_gbl_FADT.header.revision > FADT2_REVISION_ID &&
+        if (acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID &&
                 (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL)) {
                 printk(KERN_DEBUG "system APIC only can use physical flat");
                 return 1;
diff --git a/arch/x86/kernel/apic/es7000_32.c b/arch/x86/kernel/apic/es7000_32.c
index 302947775575..69328ac8de9c 100644
--- a/arch/x86/kernel/apic/es7000_32.c
+++ b/arch/x86/kernel/apic/es7000_32.c
@@ -145,7 +145,7 @@ es7000_rename_gsi(int ioapic, int gsi)
         return gsi;
 }
 
-static int wakeup_secondary_cpu_via_mip(int cpu, unsigned long eip)
+static int __cpuinit wakeup_secondary_cpu_via_mip(int cpu, unsigned long eip)
 {
         unsigned long vect = 0, psaival = 0;
 
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 30da617d18e4..1946fac42ab3 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -59,6 +59,7 @@
 #include <asm/setup.h>
 #include <asm/irq_remapping.h>
 #include <asm/hpet.h>
+#include <asm/hw_irq.h>
 #include <asm/uv/uv_hub.h>
 #include <asm/uv/uv_irq.h>
 
@@ -129,12 +130,9 @@ struct irq_pin_list {
         struct irq_pin_list *next;
 };
 
-static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
+static struct irq_pin_list *get_one_free_irq_2_pin(int node)
 {
         struct irq_pin_list *pin;
-        int node;
-
-        node = cpu_to_node(cpu);
 
         pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
 
@@ -148,9 +146,6 @@ struct irq_cfg {
         unsigned move_cleanup_count;
         u8 vector;
         u8 move_in_progress : 1;
-#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
-        u8 move_desc_pending : 1;
-#endif
 };
 
 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
@@ -212,12 +207,9 @@ static struct irq_cfg *irq_cfg(unsigned int irq)
         return cfg;
 }
 
-static struct irq_cfg *get_one_free_irq_cfg(int cpu)
+static struct irq_cfg *get_one_free_irq_cfg(int node)
 {
         struct irq_cfg *cfg;
-        int node;
-
-        node = cpu_to_node(cpu);
 
         cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
         if (cfg) {
@@ -238,13 +230,13 @@ static struct irq_cfg *get_one_free_irq_cfg(int cpu)
         return cfg;
 }
 
-int arch_init_chip_data(struct irq_desc *desc, int cpu)
+int arch_init_chip_data(struct irq_desc *desc, int node)
 {
         struct irq_cfg *cfg;
 
         cfg = desc->chip_data;
         if (!cfg) {
-                desc->chip_data = get_one_free_irq_cfg(cpu);
+                desc->chip_data = get_one_free_irq_cfg(node);
                 if (!desc->chip_data) {
                         printk(KERN_ERR "can not alloc irq_cfg\n");
                         BUG_ON(1);
@@ -254,10 +246,9 @@ int arch_init_chip_data(struct irq_desc *desc, int cpu)
         return 0;
 }
 
-#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
-
+/* for move_irq_desc */
 static void
-init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
+init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
 {
         struct irq_pin_list *old_entry, *head, *tail, *entry;
 
@@ -266,7 +257,7 @@ init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
         if (!old_entry)
                 return;
 
-        entry = get_one_free_irq_2_pin(cpu);
+        entry = get_one_free_irq_2_pin(node);
         if (!entry)
                 return;
 
@@ -276,7 +267,7 @@ init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
         tail            = entry;
         old_entry       = old_entry->next;
         while (old_entry) {
-                entry = get_one_free_irq_2_pin(cpu);
+                entry = get_one_free_irq_2_pin(node);
                 if (!entry) {
                         entry = head;
                         while (entry) {
@@ -316,12 +307,12 @@ static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
 }
 
 void arch_init_copy_chip_data(struct irq_desc *old_desc,
-                                 struct irq_desc *desc, int cpu)
+                                 struct irq_desc *desc, int node)
 {
         struct irq_cfg *cfg;
         struct irq_cfg *old_cfg;
 
-        cfg = get_one_free_irq_cfg(cpu);
+        cfg = get_one_free_irq_cfg(node);
 
         if (!cfg)
                 return;
@@ -332,7 +323,7 @@ void arch_init_copy_chip_data(struct irq_desc *old_desc,
 
         memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
 
-        init_copy_irq_2_pin(old_cfg, cfg, cpu);
+        init_copy_irq_2_pin(old_cfg, cfg, node);
 }
 
 static void free_irq_cfg(struct irq_cfg *old_cfg)
@@ -356,19 +347,7 @@ void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
                 old_desc->chip_data = NULL;
         }
 }
-
-static void
-set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
-{
-        struct irq_cfg *cfg = desc->chip_data;
-
-        if (!cfg->move_in_progress) {
-                /* it means that domain is not changed */
-                if (!cpumask_intersects(desc->affinity, mask))
-                        cfg->move_desc_pending = 1;
-        }
-}
-#endif
+/* end for move_irq_desc */
 
 #else
 static struct irq_cfg *irq_cfg(unsigned int irq)
@@ -378,13 +357,6 @@ static struct irq_cfg *irq_cfg(unsigned int irq)
 
 #endif
 
-#ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
-static inline void
-set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
-{
-}
-#endif
-
 struct io_apic {
         unsigned int index;
         unsigned int unused[3];
@@ -518,132 +490,18 @@ static void ioapic_mask_entry(int apic, int pin)
         spin_unlock_irqrestore(&ioapic_lock, flags);
 }
 
-#ifdef CONFIG_SMP
-static void send_cleanup_vector(struct irq_cfg *cfg)
-{
-        cpumask_var_t cleanup_mask;
-
-        if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
-                unsigned int i;
-                cfg->move_cleanup_count = 0;
-                for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
-                        cfg->move_cleanup_count++;
-                for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
-                        apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
-        } else {
-                cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
-                cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
-                apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
-                free_cpumask_var(cleanup_mask);
-        }
-        cfg->move_in_progress = 0;
-}
-
-static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
-{
-        int apic, pin;
-        struct irq_pin_list *entry;
-        u8 vector = cfg->vector;
-
-        entry = cfg->irq_2_pin;
-        for (;;) {
-                unsigned int reg;
-
-                if (!entry)
-                        break;
-
-                apic = entry->apic;
-                pin = entry->pin;
-                /*
-                 * With interrupt-remapping, destination information comes
-                 * from interrupt-remapping table entry.
-                 */
-                if (!irq_remapped(irq))
-                        io_apic_write(apic, 0x11 + pin*2, dest);
-                reg = io_apic_read(apic, 0x10 + pin*2);
-                reg &= ~IO_APIC_REDIR_VECTOR_MASK;
-                reg |= vector;
-                io_apic_modify(apic, 0x10 + pin*2, reg);
-                if (!entry->next)
-                        break;
-                entry = entry->next;
-        }
-}
-
-static int
-assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
-
-/*
- * Either sets desc->affinity to a valid value, and returns
- * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
- * leaves desc->affinity untouched.
- */
-static unsigned int
-set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
-{
-        struct irq_cfg *cfg;
-        unsigned int irq;
-
-        if (!cpumask_intersects(mask, cpu_online_mask))
-                return BAD_APICID;
-
-        irq = desc->irq;
-        cfg = desc->chip_data;
-        if (assign_irq_vector(irq, cfg, mask))
-                return BAD_APICID;
-
-        /* check that before desc->addinity get updated */
-        set_extra_move_desc(desc, mask);
-
-        cpumask_copy(desc->affinity, mask);
-
-        return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
-}
-
-static void
-set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
-{
-        struct irq_cfg *cfg;
-        unsigned long flags;
-        unsigned int dest;
-        unsigned int irq;
-
-        irq = desc->irq;
-        cfg = desc->chip_data;
-
-        spin_lock_irqsave(&ioapic_lock, flags);
-        dest = set_desc_affinity(desc, mask);
-        if (dest != BAD_APICID) {
-                /* Only the high 8 bits are valid. */
-                dest = SET_APIC_LOGICAL_ID(dest);
-                __target_IO_APIC_irq(irq, dest, cfg);
-        }
-        spin_unlock_irqrestore(&ioapic_lock, flags);
-}
-
-static void
-set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
-{
-        struct irq_desc *desc;
-
-        desc = irq_to_desc(irq);
-
-        set_ioapic_affinity_irq_desc(desc, mask);
-}
-#endif /* CONFIG_SMP */
-
 /*
  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  * shared ISA-space IRQs, so we have to support them. We are super
  * fast in the common case, and fast for shared ISA-space IRQs.
  */
-static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
+static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
 {
         struct irq_pin_list *entry;
 
         entry = cfg->irq_2_pin;
         if (!entry) {
-                entry = get_one_free_irq_2_pin(cpu);
+                entry = get_one_free_irq_2_pin(node);
                 if (!entry) {
                         printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
                                         apic, pin);
@@ -663,7 +521,7 @@ static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
                 entry = entry->next;
         }
 
-        entry->next = get_one_free_irq_2_pin(cpu);
+        entry->next = get_one_free_irq_2_pin(node);
         entry = entry->next;
         entry->apic = apic;
         entry->pin = pin;
@@ -672,7 +530,7 @@ static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
 /*
  * Reroute an IRQ to a different pin.
  */
-static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
+static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
                                       int oldapic, int oldpin,
                                       int newapic, int newpin)
 {
@@ -692,7 +550,7 @@ static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
 
         /* why? call replace before add? */
         if (!replaced)
-                add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
+                add_pin_to_irq_node(cfg, node, newapic, newpin);
 }
 
 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
@@ -850,7 +708,6 @@ static int __init ioapic_pirq_setup(char *str)
 __setup("pirq=", ioapic_pirq_setup);
 #endif /* CONFIG_X86_32 */
 
-#ifdef CONFIG_INTR_REMAP
 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
 {
         int apic;
@@ -948,20 +805,6 @@ int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
         return 0;
 }
 
-void reinit_intr_remapped_IO_APIC(int intr_remapping,
-        struct IO_APIC_route_entry **ioapic_entries)
-
-{
-        /*
-         * for now plain restore of previous settings.
-         * TBD: In the case of OS enabling interrupt-remapping,
-         * IO-APIC RTE's need to be setup to point to interrupt-remapping
-         * table entries. for now, do a plain restore, and wait for
-         * the setup_IO_APIC_irqs() to do proper initialization.
-         */
-        restore_IO_APIC_setup(ioapic_entries);
-}
-
 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
 {
         int apic;
@@ -971,7 +814,6 @@ void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
 
         kfree(ioapic_entries);
 }
-#endif
 
 /*
  * Find the IRQ entry number of a certain pin.
@@ -1032,54 +874,6 @@ static int __init find_isa_irq_apic(int irq, int type)
         return -1;
 }
 
-/*
- * Find a specific PCI IRQ entry.
- * Not an __init, possibly needed by modules
- */
-static int pin_2_irq(int idx, int apic, int pin);
-
-int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
-{
-        int apic, i, best_guess = -1;
-
-        apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
-                bus, slot, pin);
-        if (test_bit(bus, mp_bus_not_pci)) {
-                apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
-                return -1;
-        }
-        for (i = 0; i < mp_irq_entries; i++) {
-                int lbus = mp_irqs[i].srcbus;
-
-                for (apic = 0; apic < nr_ioapics; apic++)
-                        if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
-                            mp_irqs[i].dstapic == MP_APIC_ALL)
-                                break;
-
-                if (!test_bit(lbus, mp_bus_not_pci) &&
-                    !mp_irqs[i].irqtype &&
-                    (bus == lbus) &&
-                    (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
-                        int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
-
-                        if (!(apic || IO_APIC_IRQ(irq)))
-                                continue;
-
-                        if (pin == (mp_irqs[i].srcbusirq & 3))
-                                return irq;
-                        /*
-                         * Use the first all-but-pin matching entry as a
-                         * best-guess fuzzy result for broken mptables.
-                         */
-                        if (best_guess < 0)
-                                best_guess = irq;
-                }
-        }
-        return best_guess;
-}
-
-EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
-
 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
 /*
  * EISA Edge/Level control register, ELCR
@@ -1298,6 +1092,64 @@ static int pin_2_irq(int idx, int apic, int pin)
         return irq;
 }
 
+/*
+ * Find a specific PCI IRQ entry.
+ * Not an __init, possibly needed by modules
+ */
+int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
+                                struct io_apic_irq_attr *irq_attr)
+{
+        int apic, i, best_guess = -1;
+
+        apic_printk(APIC_DEBUG,
+                    "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
+                    bus, slot, pin);
+        if (test_bit(bus, mp_bus_not_pci)) {
+                apic_printk(APIC_VERBOSE,
+                            "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
+                return -1;
+        }
+        for (i = 0; i < mp_irq_entries; i++) {
+                int lbus = mp_irqs[i].srcbus;
+
+                for (apic = 0; apic < nr_ioapics; apic++)
+                        if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
+                            mp_irqs[i].dstapic == MP_APIC_ALL)
+                                break;
+
+                if (!test_bit(lbus, mp_bus_not_pci) &&
+                    !mp_irqs[i].irqtype &&
+                    (bus == lbus) &&
+                    (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
+                        int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
+
+                        if (!(apic || IO_APIC_IRQ(irq)))
+                                continue;
+
+                        if (pin == (mp_irqs[i].srcbusirq & 3)) {
+                                set_io_apic_irq_attr(irq_attr, apic,
+                                                     mp_irqs[i].dstirq,
+                                                     irq_trigger(i),
+                                                     irq_polarity(i));
+                                return irq;
+                        }
+                        /*
+                         * Use the first all-but-pin matching entry as a
+                         * best-guess fuzzy result for broken mptables.
+                         */
+                        if (best_guess < 0) {
+                                set_io_apic_irq_attr(irq_attr, apic,
+                                                     mp_irqs[i].dstirq,
+                                                     irq_trigger(i),
+                                                     irq_polarity(i));
+                                best_guess = irq;
+                        }
+                }
+        }
+        return best_guess;
+}
+EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
+
 void lock_vector_lock(void)
 {
         /* Used to the online set of cpus does not change
@@ -1628,58 +1480,70 @@ static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq
         ioapic_write_entry(apic_id, pin, entry);
 }
 
+static struct {
+        DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
+} mp_ioapic_routing[MAX_IO_APICS];
+
 static void __init setup_IO_APIC_irqs(void)
 {
-        int apic_id, pin, idx, irq;
+        int apic_id = 0, pin, idx, irq;
         int notcon = 0;
         struct irq_desc *desc;
         struct irq_cfg *cfg;
-        int cpu = boot_cpu_id;
+        int node = cpu_to_node(boot_cpu_id);
 
         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 
-        for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
-                for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
-
-                        idx = find_irq_entry(apic_id, pin, mp_INT);
-                        if (idx == -1) {
-                                if (!notcon) {
-                                        notcon = 1;
-                                        apic_printk(APIC_VERBOSE,
-                                                KERN_DEBUG " %d-%d",
-                                                mp_ioapics[apic_id].apicid, pin);
-                                } else
-                                        apic_printk(APIC_VERBOSE, " %d-%d",
-                                                mp_ioapics[apic_id].apicid, pin);
-                                continue;
-                        }
-                        if (notcon) {
-                                apic_printk(APIC_VERBOSE,
-                                        " (apicid-pin) not connected\n");
-                                notcon = 0;
-                        }
+#ifdef CONFIG_ACPI
+        if (!acpi_disabled && acpi_ioapic) {
+                apic_id = mp_find_ioapic(0);
+                if (apic_id < 0)
+                        apic_id = 0;
+        }
+#endif
 
-                        irq = pin_2_irq(idx, apic_id, pin);
+        for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
+                idx = find_irq_entry(apic_id, pin, mp_INT);
+                if (idx == -1) {
+                        if (!notcon) {
+                                notcon = 1;
+                                apic_printk(APIC_VERBOSE,
+                                        KERN_DEBUG " %d-%d",
+                                        mp_ioapics[apic_id].apicid, pin);
+                        } else
+                                apic_printk(APIC_VERBOSE, " %d-%d",
+                                        mp_ioapics[apic_id].apicid, pin);
+                        continue;
+                }
+                if (notcon) {
+                        apic_printk(APIC_VERBOSE,
+                                " (apicid-pin) not connected\n");
+                        notcon = 0;
+                }
 
-                        /*
-                         * Skip the timer IRQ if there's a quirk handler
-                         * installed and if it returns 1:
-                         */
-                        if (apic->multi_timer_check &&
-                                        apic->multi_timer_check(apic_id, irq))
-                                continue;
+                irq = pin_2_irq(idx, apic_id, pin);
 
-                        desc = irq_to_desc_alloc_cpu(irq, cpu);
-                        if (!desc) {
-                                printk(KERN_INFO "can not get irq_desc for %d\n", irq);
-                                continue;
-                        }
-                        cfg = desc->chip_data;
-                        add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
+                /*
+                 * Skip the timer IRQ if there's a quirk handler
+                 * installed and if it returns 1:
+                 */
+                if (apic->multi_timer_check &&
+                                apic->multi_timer_check(apic_id, irq))
+                        continue;
 
-                        setup_IO_APIC_irq(apic_id, pin, irq, desc,
-                                        irq_trigger(idx), irq_polarity(idx));
+                desc = irq_to_desc_alloc_node(irq, node);
+                if (!desc) {
+                        printk(KERN_INFO "can not get irq_desc for %d\n", irq);
+                        continue;
                 }
+                cfg = desc->chip_data;
+                add_pin_to_irq_node(cfg, node, apic_id, pin);
+                /*
+                 * don't mark it in pin_programmed, so later acpi could
+                 * set it correctly when irq < 16
+                 */
+                setup_IO_APIC_irq(apic_id, pin, irq, desc,
+                                irq_trigger(idx), irq_polarity(idx));
         }
 
         if (notcon)
@@ -1869,7 +1733,7 @@ __apicdebuginit(void) print_APIC_bitfield(int base)
 
 __apicdebuginit(void) print_local_APIC(void *dummy)
 {
-        unsigned int v, ver, maxlvt;
+        unsigned int i, v, ver, maxlvt;
         u64 icr;
 
         if (apic_verbosity == APIC_QUIET)
@@ -1957,6 +1821,18 @@ __apicdebuginit(void) print_local_APIC(void *dummy)
         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
         v = apic_read(APIC_TDCR);
         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
+
+        if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
+                v = apic_read(APIC_EFEAT);
+                maxlvt = (v >> 16) & 0xff;
+                printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
+                v = apic_read(APIC_ECTRL);
+                printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
+                for (i = 0; i < maxlvt; i++) {
+                        v = apic_read(APIC_EILVTn(i));
+                        printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
+                }
+        }
         printk("\n");
 }
 
@@ -2005,6 +1881,11 @@ __apicdebuginit(void) print_PIC(void)
 __apicdebuginit(int) print_all_ICs(void)
 {
         print_PIC();
+
+        /* don't print out if apic is not there */
+        if (!cpu_has_apic || disable_apic)
+                return 0;
+
         print_all_local_APICs();
         print_IO_APIC();
 
@@ -2360,6 +2241,118 @@ static int ioapic_retrigger_irq(unsigned int irq)
  */
 
 #ifdef CONFIG_SMP
+static void send_cleanup_vector(struct irq_cfg *cfg)
+{
+        cpumask_var_t cleanup_mask;
+
+        if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
+                unsigned int i;
+                cfg->move_cleanup_count = 0;
+                for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
+                        cfg->move_cleanup_count++;
+                for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
+                        apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
+        } else {
+                cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
+                cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
+                apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
+                free_cpumask_var(cleanup_mask);
+        }
+        cfg->move_in_progress = 0;
+}
+
+static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
+{
+        int apic, pin;
+        struct irq_pin_list *entry;
+        u8 vector = cfg->vector;
+
+        entry = cfg->irq_2_pin;
+        for (;;) {
+                unsigned int reg;
+
+                if (!entry)
+                        break;
+
+                apic = entry->apic;
+                pin = entry->pin;
+                /*
+                 * With interrupt-remapping, destination information comes
+                 * from interrupt-remapping table entry.
+                 */
+                if (!irq_remapped(irq))
+                        io_apic_write(apic, 0x11 + pin*2, dest);
+                reg = io_apic_read(apic, 0x10 + pin*2);
+                reg &= ~IO_APIC_REDIR_VECTOR_MASK;
+                reg |= vector;
+                io_apic_modify(apic, 0x10 + pin*2, reg);
+                if (!entry->next)
+                        break;
+                entry = entry->next;
+        }
+}
+
+static int
+assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
+
+/*
+ * Either sets desc->affinity to a valid value, and returns
+ * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
+ * leaves desc->affinity untouched.
+ */
+static unsigned int
+set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
+{
+        struct irq_cfg *cfg;
+        unsigned int irq;
+
+        if (!cpumask_intersects(mask, cpu_online_mask))
+                return BAD_APICID;
+
+        irq = desc->irq;
+        cfg = desc->chip_data;
+        if (assign_irq_vector(irq, cfg, mask))
+                return BAD_APICID;
+
+        cpumask_copy(desc->affinity, mask);
+
+        return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
+}
+
+static int
+set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
+{
+        struct irq_cfg *cfg;
+        unsigned long flags;
+        unsigned int dest;
+        unsigned int irq;
+        int ret = -1;
+
+        irq = desc->irq;
+        cfg = desc->chip_data;
+
+        spin_lock_irqsave(&ioapic_lock, flags);
+        dest = set_desc_affinity(desc, mask);
+        if (dest != BAD_APICID) {
+                /* Only the high 8 bits are valid. */
+                dest = SET_APIC_LOGICAL_ID(dest);
+                __target_IO_APIC_irq(irq, dest, cfg);
+                ret = 0;
+        }
+        spin_unlock_irqrestore(&ioapic_lock, flags);
+
+        return ret;
+}
+
+static int
+set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
+{
+        struct irq_desc *desc;
+
+        desc = irq_to_desc(irq);
+
+        return set_ioapic_affinity_irq_desc(desc, mask);
+}
 
 #ifdef CONFIG_INTR_REMAP
 
@@ -2374,26 +2367,25 @@ static int ioapic_retrigger_irq(unsigned int irq)
  * Real vector that is used for interrupting cpu will be coming from
  * the interrupt-remapping table entry.
  */
-static void
+static int
 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
 {
         struct irq_cfg *cfg;
         struct irte irte;
         unsigned int dest;
         unsigned int irq;
+        int ret = -1;
 
         if (!cpumask_intersects(mask, cpu_online_mask))
-                return;
+                return ret;
 
         irq = desc->irq;
         if (get_irte(irq, &irte))
-                return;
+                return ret;
 
         cfg = desc->chip_data;
         if (assign_irq_vector(irq, cfg, mask))
-                return;
-
-        set_extra_move_desc(desc, mask);
+                return ret;
 
         dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
 
@@ -2409,27 +2401,30 @@ migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
                 send_cleanup_vector(cfg);
 
         cpumask_copy(desc->affinity, mask);
+
+        return 0;
 }
 
 /*
  * Migrates the IRQ destination in the process context.
  */
-static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
+static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
                                             const struct cpumask *mask)
 {
-        migrate_ioapic_irq_desc(desc, mask);
+        return migrate_ioapic_irq_desc(desc, mask);
 }
-static void set_ir_ioapic_affinity_irq(unsigned int irq,
+static int set_ir_ioapic_affinity_irq(unsigned int irq,
                                        const struct cpumask *mask)
 {
         struct irq_desc *desc = irq_to_desc(irq);
 
-        set_ir_ioapic_affinity_irq_desc(desc, mask);
+        return set_ir_ioapic_affinity_irq_desc(desc, mask);
 }
 #else
-static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
+static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
                                                    const struct cpumask *mask)
 {
+        return 0;
 }
 #endif
 
@@ -2491,86 +2486,19 @@ static void irq_complete_move(struct irq_desc **descp)
         struct irq_cfg *cfg = desc->chip_data;
         unsigned vector, me;
 
-        if (likely(!cfg->move_in_progress)) {
-#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
-                if (likely(!cfg->move_desc_pending))
-                        return;
-
-                /* domain has not changed, but affinity did */
-                me = smp_processor_id();
-                if (cpumask_test_cpu(me, desc->affinity)) {
-                        *descp = desc = move_irq_desc(desc, me);
-                        /* get the new one */
-                        cfg = desc->chip_data;
-                        cfg->move_desc_pending = 0;
-                }
-#endif
+        if (likely(!cfg->move_in_progress))
                 return;
-        }
 
         vector = ~get_irq_regs()->orig_ax;
         me = smp_processor_id();
 
-        if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) {
-#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
-                *descp = desc = move_irq_desc(desc, me);
-                /* get the new one */
-                cfg = desc->chip_data;
-#endif
+        if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
                 send_cleanup_vector(cfg);
-        }
 }
 #else
 static inline void irq_complete_move(struct irq_desc **descp) {}
 #endif
 
-static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
-{
-        int apic, pin;
-        struct irq_pin_list *entry;
-
-        entry = cfg->irq_2_pin;
-        for (;;) {
-
-                if (!entry)
-                        break;
-
-                apic = entry->apic;
-                pin = entry->pin;
-                io_apic_eoi(apic, pin);
-                entry = entry->next;
-        }
-}
-
-static void
-eoi_ioapic_irq(struct irq_desc *desc)
-{
-        struct irq_cfg *cfg;
-        unsigned long flags;
-        unsigned int irq;
-
-        irq = desc->irq;
-        cfg = desc->chip_data;
-
-        spin_lock_irqsave(&ioapic_lock, flags);
-        __eoi_ioapic_irq(irq, cfg);
-        spin_unlock_irqrestore(&ioapic_lock, flags);
-}
-
-#ifdef CONFIG_X86_X2APIC
-static void ack_x2apic_level(unsigned int irq)
-{
-        struct irq_desc *desc = irq_to_desc(irq);
-        ack_x2APIC_irq();
-        eoi_ioapic_irq(desc);
-}
-
-static void ack_x2apic_edge(unsigned int irq)
-{
-        ack_x2APIC_irq();
-}
-#endif
-
 static void ack_apic_edge(unsigned int irq)
 {
         struct irq_desc *desc = irq_to_desc(irq);
@@ -2634,9 +2562,6 @@ static void ack_apic_level(unsigned int irq)
          */
         ack_APIC_irq();
 
-        if (irq_remapped(irq))
-                eoi_ioapic_irq(desc);
-
         /* Now we can move and renable the irq */
         if (unlikely(do_unmask_irq)) {
                 /* Only migrate the irq if the ack has been received.
@@ -2683,22 +2608,50 @@ static void ack_apic_level(unsigned int irq)
 }
 
 #ifdef CONFIG_INTR_REMAP
+static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
+{
+        int apic, pin;
+        struct irq_pin_list *entry;
+
+        entry = cfg->irq_2_pin;
+        for (;;) {
+
+                if (!entry)
+                        break;
+
+                apic = entry->apic;
+                pin = entry->pin;
+                io_apic_eoi(apic, pin);
+                entry = entry->next;
+        }
+}
+
+static void
+eoi_ioapic_irq(struct irq_desc *desc)
+{
+        struct irq_cfg *cfg;
+        unsigned long flags;
+        unsigned int irq;
+
+        irq = desc->irq;
+        cfg = desc->chip_data;
+
+        spin_lock_irqsave(&ioapic_lock, flags);
+        __eoi_ioapic_irq(irq, cfg);
+        spin_unlock_irqrestore(&ioapic_lock, flags);
+}
+
 static void ir_ack_apic_edge(unsigned int irq)
 {
-#ifdef CONFIG_X86_X2APIC
-       if (x2apic_enabled())
-               return ack_x2apic_edge(irq);
-#endif
-       return ack_apic_edge(irq);
+        ack_APIC_irq();
 }
 
 static void ir_ack_apic_level(unsigned int irq)
 {
-#ifdef CONFIG_X86_X2APIC
-       if (x2apic_enabled())
-               return ack_x2apic_level(irq);
-#endif
-       return ack_apic_level(irq);
+        struct irq_desc *desc = irq_to_desc(irq);
+
+        ack_APIC_irq();
+        eoi_ioapic_irq(desc);
 }
 #endif /* CONFIG_INTR_REMAP */
 
@@ -2903,7 +2856,7 @@ static inline void __init check_timer(void)
 {
         struct irq_desc *desc = irq_to_desc(0);
         struct irq_cfg *cfg = desc->chip_data;
-        int cpu = boot_cpu_id;
+        int node = cpu_to_node(boot_cpu_id);
         int apic1, pin1, apic2, pin2;
         unsigned long flags;
         int no_pin1 = 0;
@@ -2969,7 +2922,7 @@ static inline void __init check_timer(void)
                  * Ok, does IRQ0 through the IOAPIC work?
                  */
                 if (no_pin1) {
-                        add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
+                        add_pin_to_irq_node(cfg, node, apic1, pin1);
                         setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
                 } else {
                         /* for edge trigger, setup_IO_APIC_irq already
@@ -3006,7 +2959,7 @@ static inline void __init check_timer(void)
                 /*
                  * legacy devices should be connected to IO APIC #0
                  */
-                replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
+                replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
                 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
                 enable_8259A_irq(0);
                 if (timer_irq_works()) {
@@ -3218,14 +3171,13 @@ static int nr_irqs_gsi = NR_IRQS_LEGACY;
 /*
  * Dynamic irq allocate and deallocation
  */
-unsigned int create_irq_nr(unsigned int irq_want)
+unsigned int create_irq_nr(unsigned int irq_want, int node)
 {
         /* Allocate an unused irq */
         unsigned int irq;
         unsigned int new;
         unsigned long flags;
         struct irq_cfg *cfg_new = NULL;
-        int cpu = boot_cpu_id;
         struct irq_desc *desc_new = NULL;
 
         irq = 0;
@@ -3234,7 +3186,7 @@ unsigned int create_irq_nr(unsigned int irq_want)
 
         spin_lock_irqsave(&vector_lock, flags);
         for (new = irq_want; new < nr_irqs; new++) {
-                desc_new = irq_to_desc_alloc_cpu(new, cpu);
+                desc_new = irq_to_desc_alloc_node(new, node);
                 if (!desc_new) {
                         printk(KERN_INFO "can not get irq_desc for %d\n", new);
                         continue;
@@ -3243,6 +3195,9 @@ unsigned int create_irq_nr(unsigned int irq_want)
 
                 if (cfg_new->vector != 0)
                         continue;
+
+                desc_new = move_irq_desc(desc_new, node);
+
                 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
                         irq = new;
                 break;
@@ -3260,11 +3215,12 @@ unsigned int create_irq_nr(unsigned int irq_want)
 
 int create_irq(void)
 {
+        int node = cpu_to_node(boot_cpu_id);
         unsigned int irq_want;
         int irq;
 
         irq_want = nr_irqs_gsi;
-        irq = create_irq_nr(irq_want);
+        irq = create_irq_nr(irq_want, node);
 
         if (irq == 0)
                 irq = -1;
@@ -3366,7 +3322,7 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms
 }
 
 #ifdef CONFIG_SMP
-static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
+static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
 {
         struct irq_desc *desc = irq_to_desc(irq);
         struct irq_cfg *cfg;
@@ -3375,7 +3331,7 @@ static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
 
         dest = set_desc_affinity(desc, mask);
         if (dest == BAD_APICID)
-                return;
+                return -1;
 
         cfg = desc->chip_data;
 
@@ -3387,13 +3343,15 @@ static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
 
         write_msi_msg_desc(desc, &msg);
+
+        return 0;
 }
 #ifdef CONFIG_INTR_REMAP
 /*
  * Migrate the MSI irq to another cpumask. This migration is
  * done in the process context using interrupt-remapping hardware.
  */
-static void
+static int
 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
 {
         struct irq_desc *desc = irq_to_desc(irq);
@@ -3402,11 +3360,11 @@ ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
         struct irte irte;
 
         if (get_irte(irq, &irte))
-                return;
+                return -1;
 
         dest = set_desc_affinity(desc, mask);
         if (dest == BAD_APICID)
-                return;
+                return -1;
 
         irte.vector = cfg->vector;
         irte.dest_id = IRTE_DEST(dest);
@@ -3423,6 +3381,8 @@ ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
          */
         if (cfg->move_in_progress)
                 send_cleanup_vector(cfg);
+
+        return 0;
 }
 
 #endif
@@ -3518,15 +3478,17 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
         unsigned int irq_want;
         struct intel_iommu *iommu = NULL;
         int index = 0;
+        int node;
 
         /* x86 doesn't support multiple MSI yet */
         if (type == PCI_CAP_ID_MSI && nvec > 1)
                 return 1;
 
+        node = dev_to_node(&dev->dev);
         irq_want = nr_irqs_gsi;
         sub_handle = 0;
         list_for_each_entry(msidesc, &dev->msi_list, list) {
-                irq = create_irq_nr(irq_want);
+                irq = create_irq_nr(irq_want, node);
                 if (irq == 0)
                         return -1;
                 irq_want = irq + 1;
@@ -3576,7 +3538,7 @@ void arch_teardown_msi_irq(unsigned int irq)
 
 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
 #ifdef CONFIG_SMP
-static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
+static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
 {
         struct irq_desc *desc = irq_to_desc(irq);
         struct irq_cfg *cfg;
@@ -3585,7 +3547,7 @@ static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
 
         dest = set_desc_affinity(desc, mask);
         if (dest == BAD_APICID)
-                return;
+                return -1;
 
         cfg = desc->chip_data;
 
@@ -3597,6 +3559,8 @@ static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
 
         dmar_msi_write(irq, &msg);
+
+        return 0;
 }
 
 #endif /* CONFIG_SMP */
@@ -3630,7 +3594,7 @@ int arch_setup_dmar_msi(unsigned int irq)
 #ifdef CONFIG_HPET_TIMER
 
 #ifdef CONFIG_SMP
-static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
+static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
 {
         struct irq_desc *desc = irq_to_desc(irq);
         struct irq_cfg *cfg;
@@ -3639,7 +3603,7 @@ static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
 
         dest = set_desc_affinity(desc, mask);
         if (dest == BAD_APICID)
-                return;
+                return -1;
 
         cfg = desc->chip_data;
 
@@ -3651,6 +3615,8 @@ static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
 
         hpet_msi_write(irq, &msg);
+
+        return 0;
 }
 
 #endif /* CONFIG_SMP */
@@ -3707,7 +3673,7 @@ static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
         write_ht_irq_msg(irq, &msg);
 }
 
-static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
+static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
 {
         struct irq_desc *desc = irq_to_desc(irq);
         struct irq_cfg *cfg;
@@ -3715,11 +3681,13 @@ static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
 
         dest = set_desc_affinity(desc, mask);
         if (dest == BAD_APICID)
-                return;
+                return -1;
 
         cfg = desc->chip_data;
 
         target_ht_irq(irq, dest, cfg->vector);
+
+        return 0;
 }
 
 #endif
@@ -3794,6 +3762,8 @@ int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
         unsigned long flags;
         int err;
 
+        BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
+
         cfg = irq_cfg(irq);
 
         err = assign_irq_vector(irq, cfg, eligible_cpu);
@@ -3807,15 +3777,13 @@ int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
 
         mmr_value = 0;
         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
-        BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
-
-        entry->vector = cfg->vector;
-        entry->delivery_mode = apic->irq_delivery_mode;
-        entry->dest_mode = apic->irq_dest_mode;
-        entry->polarity = 0;
-        entry->trigger = 0;
-        entry->mask = 0;
-        entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
+        entry->vector           = cfg->vector;
+        entry->delivery_mode    = apic->irq_delivery_mode;
+        entry->dest_mode        = apic->irq_dest_mode;
+        entry->polarity         = 0;
+        entry->trigger          = 0;
+        entry->mask             = 0;
+        entry->dest             = apic->cpu_mask_to_apicid(eligible_cpu);
 
         mmr_pnode = uv_blade_to_pnode(mmr_blade);
         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
@@ -3833,10 +3801,10 @@ void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
         struct uv_IO_APIC_route_entry *entry;
         int mmr_pnode;
 
+        BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
+
         mmr_value = 0;
         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
-        BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
-
         entry->mask = 1;
 
         mmr_pnode = uv_blade_to_pnode(mmr_blade);
@@ -3900,6 +3868,71 @@ int __init arch_probe_nr_irqs(void)
 }
 #endif
 
+static int __io_apic_set_pci_routing(struct device *dev, int irq,
+                                struct io_apic_irq_attr *irq_attr)
+{
+        struct irq_desc *desc;
+        struct irq_cfg *cfg;
+        int node;
+        int ioapic, pin;
+        int trigger, polarity;
+
+        ioapic = irq_attr->ioapic;
+        if (!IO_APIC_IRQ(irq)) {
+                apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
+                        ioapic);
+                return -EINVAL;
+        }
+
+        if (dev)
+                node = dev_to_node(dev);
+        else
+                node = cpu_to_node(boot_cpu_id);
+
+        desc = irq_to_desc_alloc_node(irq, node);
+        if (!desc) {
+                printk(KERN_INFO "can not get irq_desc %d\n", irq);
+                return 0;
+        }
+
+        pin = irq_attr->ioapic_pin;
+        trigger = irq_attr->trigger;
+        polarity = irq_attr->polarity;
+
+        /*
+         * IRQs < 16 are already in the irq_2_pin[] map
+         */
+        if (irq >= NR_IRQS_LEGACY) {
+                cfg = desc->chip_data;
+                add_pin_to_irq_node(cfg, node, ioapic, pin);
+        }
+
+        setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
+
+        return 0;
+}
+
+int io_apic_set_pci_routing(struct device *dev, int irq,
+                                struct io_apic_irq_attr *irq_attr)
+{
+        int ioapic, pin;
+        /*
+         * Avoid pin reprogramming.  PRTs typically include entries
+         * with redundant pin->gsi mappings (but unique PCI devices);
+         * we only program the IOAPIC on the first.
+         */
+        ioapic = irq_attr->ioapic;
+        pin = irq_attr->ioapic_pin;
+        if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
+                pr_debug("Pin %d-%d already programmed\n",
+                         mp_ioapics[ioapic].apicid, pin);
+                return 0;
+        }
+        set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
+
+        return __io_apic_set_pci_routing(dev, irq, irq_attr);
+}
+
 /* --------------------------------------------------------------------------
                           ACPI-based IOAPIC Configuration
    -------------------------------------------------------------------------- */
@@ -3980,6 +4013,7 @@ int __init io_apic_get_unique_id(int ioapic, int apic_id)
 
         return apic_id;
 }
+#endif
 
 int __init io_apic_get_version(int ioapic)
 {
@@ -3992,39 +4026,6 @@ int __init io_apic_get_version(int ioapic)
 
         return reg_01.bits.version;
 }
-#endif
-
-int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
-{
-        struct irq_desc *desc;
-        struct irq_cfg *cfg;
-        int cpu = boot_cpu_id;
-
-        if (!IO_APIC_IRQ(irq)) {
-                apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
-                        ioapic);
-                return -EINVAL;
-        }
-
-        desc = irq_to_desc_alloc_cpu(irq, cpu);
-        if (!desc) {
-                printk(KERN_INFO "can not get irq_desc %d\n", irq);
-                return 0;
-        }
-
-        /*
-         * IRQs < 16 are already in the irq_2_pin[] map
-         */
-        if (irq >= NR_IRQS_LEGACY) {
-                cfg = desc->chip_data;
-                add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
-        }
-
-        setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
-
-        return 0;
-}
-
 
 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
 {
@@ -4055,51 +4056,44 @@ int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
 #ifdef CONFIG_SMP
 void __init setup_ioapic_dest(void)
 {
-        int pin, ioapic, irq, irq_entry;
+        int pin, ioapic = 0, irq, irq_entry;
         struct irq_desc *desc;
-        struct irq_cfg *cfg;
         const struct cpumask *mask;
 
         if (skip_ioapic_setup == 1)
                 return;
 
-        for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
-                for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
-                        irq_entry = find_irq_entry(ioapic, pin, mp_INT);
-                        if (irq_entry == -1)
-                                continue;
-                        irq = pin_2_irq(irq_entry, ioapic, pin);
-
-                        /* setup_IO_APIC_irqs could fail to get vector for some device
-                         * when you have too many devices, because at that time only boot
-                         * cpu is online.
-                         */
-                        desc = irq_to_desc(irq);
-                        cfg = desc->chip_data;
-                        if (!cfg->vector) {
-                                setup_IO_APIC_irq(ioapic, pin, irq, desc,
-                                                  irq_trigger(irq_entry),
-                                                  irq_polarity(irq_entry));
-                                continue;
+#ifdef CONFIG_ACPI
+        if (!acpi_disabled && acpi_ioapic) {
+                ioapic = mp_find_ioapic(0);
+                if (ioapic < 0)
+                        ioapic = 0;
+        }
+#endif
 
-                        }
+        for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
+                irq_entry = find_irq_entry(ioapic, pin, mp_INT);
+                if (irq_entry == -1)
+                        continue;
+                irq = pin_2_irq(irq_entry, ioapic, pin);
 
-                        /*
-                         * Honour affinities which have been set in early boot
-                         */
-                        if (desc->status &
-                            (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
-                                mask = desc->affinity;
-                        else
-                                mask = apic->target_cpus();
+                desc = irq_to_desc(irq);
 
-                        if (intr_remapping_enabled)
-                                set_ir_ioapic_affinity_irq_desc(desc, mask);
-                        else
-                                set_ioapic_affinity_irq_desc(desc, mask);
-                }
+                /*
+                 * Honour affinities which have been set in early boot
+                 */
+                if (desc->status &
+                    (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
+                        mask = desc->affinity;
+                else
+                        mask = apic->target_cpus();
 
+                if (intr_remapping_enabled)
+                        set_ir_ioapic_affinity_irq_desc(desc, mask);
+                else
+                        set_ioapic_affinity_irq_desc(desc, mask);
         }
+
 }
 #endif
 
diff --git a/arch/x86/kernel/apic/nmi.c b/arch/x86/kernel/apic/nmi.c
index ce4fbfa315a1..a691302dc3ff 100644
--- a/arch/x86/kernel/apic/nmi.c
+++ b/arch/x86/kernel/apic/nmi.c
@@ -104,7 +104,7 @@ static __init void nmi_cpu_busy(void *data)
 }
 #endif
 
-static void report_broken_nmi(int cpu, int *prev_nmi_count)
+static void report_broken_nmi(int cpu, unsigned int *prev_nmi_count)
 {
         printk(KERN_CONT "\n");
 
diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c
index 01eda2ac65e4..440a8bccd91a 100644
--- a/arch/x86/kernel/apic/probe_32.c
+++ b/arch/x86/kernel/apic/probe_32.c
@@ -160,7 +160,6 @@ extern struct apic apic_summit;
 extern struct apic apic_bigsmp;
 extern struct apic apic_es7000;
 extern struct apic apic_es7000_cluster;
-extern struct apic apic_default;
 
 struct apic *apic = &apic_default;
 EXPORT_SYMBOL_GPL(apic);
diff --git a/arch/x86/kernel/apic/probe_64.c b/arch/x86/kernel/apic/probe_64.c
index 1783652bb0e5..bc3e880f9b82 100644
--- a/arch/x86/kernel/apic/probe_64.c
+++ b/arch/x86/kernel/apic/probe_64.c
@@ -50,7 +50,7 @@ static struct apic *apic_probe[] __initdata = {
 void __init default_setup_apic_routing(void)
 {
 #ifdef CONFIG_X86_X2APIC
-        if (x2apic && (apic != &apic_x2apic_phys &&
+        if (x2apic_mode && (apic != &apic_x2apic_phys &&
 #ifdef CONFIG_X86_UV
                        apic != &apic_x2apic_uv_x &&
 #endif
diff --git a/arch/x86/kernel/apic/summit_32.c b/arch/x86/kernel/apic/summit_32.c
index 9cfe1f415d81..344eee4ac0a4 100644
--- a/arch/x86/kernel/apic/summit_32.c
+++ b/arch/x86/kernel/apic/summit_32.c
@@ -173,13 +173,6 @@ static inline int is_WPEG(struct rio_detail *rio){
                 rio->type == LookOutAWPEG || rio->type == LookOutBWPEG);
 }
 
-
-/* In clustered mode, the high nibble of APIC ID is a cluster number.
- * The low nibble is a 4-bit bitmap. */
-#define XAPIC_DEST_CPUS_SHIFT   4
-#define XAPIC_DEST_CPUS_MASK    ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
-#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
-
 #define SUMMIT_APIC_DFR_VALUE   (APIC_DFR_CLUSTER)
 
 static const struct cpumask *summit_target_cpus(void)
diff --git a/arch/x86/kernel/apic/x2apic_cluster.c b/arch/x86/kernel/apic/x2apic_cluster.c
index 4a903e2f0d17..8e4cbb255c38 100644
--- a/arch/x86/kernel/apic/x2apic_cluster.c
+++ b/arch/x86/kernel/apic/x2apic_cluster.c
@@ -10,7 +10,7 @@
 #include <asm/apic.h>
 #include <asm/ipi.h>
 
-DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
+static DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
 
 static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 {
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 2bda69352976..ef0ae207a7c8 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -105,7 +105,7 @@ static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
         cpumask_set_cpu(cpu, retmask);
 }
 
-static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
+static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 {
 #ifdef CONFIG_SMP
         unsigned long val;
@@ -562,7 +562,7 @@ void __init uv_system_init(void)
         union uvh_node_id_u node_id;
         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
-        int max_pnode = 0;
+        int gnode_extra, max_pnode = 0;
         unsigned long mmr_base, present, paddr;
         unsigned short pnode_mask;
 
@@ -574,6 +574,13 @@ void __init uv_system_init(void)
         mmr_base =
             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
             ~UV_MMR_ENABLE;
+        pnode_mask = (1 << n_val) - 1;
+        node_id.v = uv_read_local_mmr(UVH_NODE_ID);
+        gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
+        gnode_upper = ((unsigned long)gnode_extra  << m_val);
+        printk(KERN_DEBUG "UV: N %d, M %d, gnode_upper 0x%lx, gnode_extra 0x%x\n",
+                        n_val, m_val, gnode_upper, gnode_extra);
+
         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 
         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
@@ -583,15 +590,18 @@ void __init uv_system_init(void)
 
         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
+        BUG_ON(!uv_blade_info);
 
         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 
         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
+        BUG_ON(!uv_node_to_blade);
         memset(uv_node_to_blade, 255, bytes);
 
         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
+        BUG_ON(!uv_cpu_to_blade);
         memset(uv_cpu_to_blade, 255, bytes);
 
         blade = 0;
@@ -607,11 +617,6 @@ void __init uv_system_init(void)
                 }
         }
 
-        pnode_mask = (1 << n_val) - 1;
-        node_id.v = uv_read_local_mmr(UVH_NODE_ID);
-        gnode_upper = (((unsigned long)node_id.s.node_id) &
-                       ~((1 << n_val) - 1)) << m_val;
-
         uv_bios_init();
         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
                             &sn_coherency_id, &sn_region_size);
@@ -634,6 +639,7 @@ void __init uv_system_init(void)
                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
                 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
+                uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
                 uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu;