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authorRobert Richter <robert.richter@amd.com>2011-05-30 10:31:11 -0400
committerRobert Richter <robert.richter@amd.com>2011-05-30 10:36:54 -0400
commitcbf74cea070fa1f705de4712e25d9e56ae6543c7 (patch)
treedce39e94a735df4953415720d85d7ed106f71075 /arch/x86/kernel/apic
parentb76a06e08d94b2a63e47837dfe46bbbf0a3af6c2 (diff)
oprofile, x86: Add comments to IBS LVT offset initialization
Adding a comment in the code as IBS LVT setup is not obvious at all ... Signed-off-by: Robert Richter <robert.richter@amd.com>
Diffstat (limited to 'arch/x86/kernel/apic')
-rw-r--r--arch/x86/kernel/apic/apic.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index fabf01eff771..a0bf78a0918c 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -390,7 +390,8 @@ static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
390 390
391/* 391/*
392 * If mask=1, the LVT entry does not generate interrupts while mask=0 392 * If mask=1, the LVT entry does not generate interrupts while mask=0
393 * enables the vector. See also the BKDGs. 393 * enables the vector. See also the BKDGs. Must be called with
394 * preemption disabled.
394 */ 395 */
395 396
396int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 397int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)