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authorThomas Gleixner <tglx@linutronix.de>2010-09-28 11:28:38 -0400
committerThomas Gleixner <tglx@linutronix.de>2010-10-12 10:53:38 -0400
commit60c69948e5b6357ac0d5ef2a2d0ce31c173c3c64 (patch)
tree53a35f2285bf80b80062734f2429c186907137b3 /arch/x86/kernel/apic/io_apic.c
parente9f7ac664bfc36685a8eb3315ec21c067d0cee36 (diff)
x86: ioapic: Clean up the direct access to irq_desc
Most of it is useless pseudo optimization. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/apic/io_apic.c')
-rw-r--r--arch/x86/kernel/apic/io_apic.c79
1 files changed, 28 insertions, 51 deletions
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 5579f3f5943a..82c3c66e333f 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -150,10 +150,7 @@ static struct irq_cfg irq_cfgx[NR_IRQS];
150int __init arch_early_irq_init(void) 150int __init arch_early_irq_init(void)
151{ 151{
152 struct irq_cfg *cfg; 152 struct irq_cfg *cfg;
153 struct irq_desc *desc; 153 int count, node, i;
154 int count;
155 int node;
156 int i;
157 154
158 if (!legacy_pic->nr_legacy_irqs) { 155 if (!legacy_pic->nr_legacy_irqs) {
159 nr_irqs_gsi = 0; 156 nr_irqs_gsi = 0;
@@ -165,8 +162,7 @@ int __init arch_early_irq_init(void)
165 node = cpu_to_node(0); 162 node = cpu_to_node(0);
166 163
167 for (i = 0; i < count; i++) { 164 for (i = 0; i < count; i++) {
168 desc = irq_to_desc(i); 165 set_irq_chip_data(i, &cfg[i]);
169 desc->chip_data = &cfg[i];
170 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node); 166 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
171 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node); 167 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
172 /* 168 /*
@@ -185,14 +181,7 @@ int __init arch_early_irq_init(void)
185#ifdef CONFIG_SPARSE_IRQ 181#ifdef CONFIG_SPARSE_IRQ
186struct irq_cfg *irq_cfg(unsigned int irq) 182struct irq_cfg *irq_cfg(unsigned int irq)
187{ 183{
188 struct irq_cfg *cfg = NULL; 184 return get_irq_chip_data(irq);
189 struct irq_desc *desc;
190
191 desc = irq_to_desc(irq);
192 if (desc)
193 cfg = get_irq_desc_chip_data(desc);
194
195 return cfg;
196} 185}
197 186
198static struct irq_cfg *get_one_free_irq_cfg(int node) 187static struct irq_cfg *get_one_free_irq_cfg(int node)
@@ -1316,17 +1305,17 @@ static inline int IO_APIC_irq_trigger(int irq)
1316} 1305}
1317#endif 1306#endif
1318 1307
1319static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) 1308static void ioapic_register_intr(unsigned int irq, unsigned long trigger)
1320{ 1309{
1321 1310
1322 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || 1311 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1323 trigger == IOAPIC_LEVEL) 1312 trigger == IOAPIC_LEVEL)
1324 desc->status |= IRQ_LEVEL; 1313 irq_set_status_flags(irq, IRQ_LEVEL);
1325 else 1314 else
1326 desc->status &= ~IRQ_LEVEL; 1315 irq_clear_status_flags(irq, IRQ_LEVEL);
1327 1316
1328 if (irq_remapped(irq)) { 1317 if (irq_remapped(irq)) {
1329 desc->status |= IRQ_MOVE_PCNTXT; 1318 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1330 if (trigger) 1319 if (trigger)
1331 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, 1320 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1332 handle_fasteoi_irq, 1321 handle_fasteoi_irq,
@@ -1406,18 +1395,14 @@ int setup_ioapic_entry(int apic_id, int irq,
1406 return 0; 1395 return 0;
1407} 1396}
1408 1397
1409static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, 1398static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq,
1410 int trigger, int polarity) 1399 struct irq_cfg *cfg, int trigger, int polarity)
1411{ 1400{
1412 struct irq_cfg *cfg;
1413 struct IO_APIC_route_entry entry; 1401 struct IO_APIC_route_entry entry;
1414 unsigned int dest; 1402 unsigned int dest;
1415 1403
1416 if (!IO_APIC_IRQ(irq)) 1404 if (!IO_APIC_IRQ(irq))
1417 return; 1405 return;
1418
1419 cfg = get_irq_desc_chip_data(desc);
1420
1421 /* 1406 /*
1422 * For legacy irqs, cfg->domain starts with cpu 0 for legacy 1407 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1423 * controllers like 8259. Now that IO-APIC can handle this irq, update 1408 * controllers like 8259. Now that IO-APIC can handle this irq, update
@@ -1446,7 +1431,7 @@ static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq
1446 return; 1431 return;
1447 } 1432 }
1448 1433
1449 ioapic_register_intr(irq, desc, trigger); 1434 ioapic_register_intr(irq, trigger);
1450 if (irq < legacy_pic->nr_legacy_irqs) 1435 if (irq < legacy_pic->nr_legacy_irqs)
1451 legacy_pic->mask(irq); 1436 legacy_pic->mask(irq);
1452 1437
@@ -1511,8 +1496,8 @@ static void __init setup_IO_APIC_irqs(void)
1511 * don't mark it in pin_programmed, so later acpi could 1496 * don't mark it in pin_programmed, so later acpi could
1512 * set it correctly when irq < 16 1497 * set it correctly when irq < 16
1513 */ 1498 */
1514 setup_IO_APIC_irq(apic_id, pin, irq, desc, 1499 setup_ioapic_irq(apic_id, pin, irq, cfg, irq_trigger(idx),
1515 irq_trigger(idx), irq_polarity(idx)); 1500 irq_polarity(idx));
1516 } 1501 }
1517 1502
1518 if (notcon) 1503 if (notcon)
@@ -1566,7 +1551,7 @@ void setup_IO_APIC_irq_extra(u32 gsi)
1566 } 1551 }
1567 set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed); 1552 set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
1568 1553
1569 setup_IO_APIC_irq(apic_id, pin, irq, desc, 1554 setup_ioapic_irq(apic_id, pin, irq, cfg,
1570 irq_trigger(idx), irq_polarity(idx)); 1555 irq_trigger(idx), irq_polarity(idx));
1571} 1556}
1572 1557
@@ -2776,9 +2761,9 @@ static struct irq_chip lapic_chip __read_mostly = {
2776 .irq_ack = ack_lapic_irq, 2761 .irq_ack = ack_lapic_irq,
2777}; 2762};
2778 2763
2779static void lapic_register_intr(int irq, struct irq_desc *desc) 2764static void lapic_register_intr(int irq)
2780{ 2765{
2781 desc->status &= ~IRQ_LEVEL; 2766 irq_clear_status_flags(irq, IRQ_LEVEL);
2782 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, 2767 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2783 "edge"); 2768 "edge");
2784} 2769}
@@ -2881,8 +2866,7 @@ int timer_through_8259 __initdata;
2881 */ 2866 */
2882static inline void __init check_timer(void) 2867static inline void __init check_timer(void)
2883{ 2868{
2884 struct irq_desc *desc = irq_to_desc(0); 2869 struct irq_cfg *cfg = get_irq_chip_data(0);
2885 struct irq_cfg *cfg = get_irq_desc_chip_data(desc);
2886 int node = cpu_to_node(0); 2870 int node = cpu_to_node(0);
2887 int apic1, pin1, apic2, pin2; 2871 int apic1, pin1, apic2, pin2;
2888 unsigned long flags; 2872 unsigned long flags;
@@ -2952,7 +2936,7 @@ static inline void __init check_timer(void)
2952 add_pin_to_irq_node(cfg, node, apic1, pin1); 2936 add_pin_to_irq_node(cfg, node, apic1, pin1);
2953 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); 2937 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2954 } else { 2938 } else {
2955 /* for edge trigger, setup_IO_APIC_irq already 2939 /* for edge trigger, setup_ioapic_irq already
2956 * leave it unmasked. 2940 * leave it unmasked.
2957 * so only need to unmask if it is level-trigger 2941 * so only need to unmask if it is level-trigger
2958 * do we really have level trigger timer? 2942 * do we really have level trigger timer?
@@ -3020,7 +3004,7 @@ static inline void __init check_timer(void)
3020 apic_printk(APIC_QUIET, KERN_INFO 3004 apic_printk(APIC_QUIET, KERN_INFO
3021 "...trying to set up timer as Virtual Wire IRQ...\n"); 3005 "...trying to set up timer as Virtual Wire IRQ...\n");
3022 3006
3023 lapic_register_intr(0, desc); 3007 lapic_register_intr(0);
3024 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ 3008 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3025 legacy_pic->unmask(0); 3009 legacy_pic->unmask(0);
3026 3010
@@ -3457,8 +3441,8 @@ static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3457 3441
3458static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) 3442static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3459{ 3443{
3460 int ret;
3461 struct msi_msg msg; 3444 struct msi_msg msg;
3445 int ret;
3462 3446
3463 ret = msi_compose_msg(dev, irq, &msg, -1); 3447 ret = msi_compose_msg(dev, irq, &msg, -1);
3464 if (ret < 0) 3448 if (ret < 0)
@@ -3468,11 +3452,7 @@ static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3468 write_msi_msg(irq, &msg); 3452 write_msi_msg(irq, &msg);
3469 3453
3470 if (irq_remapped(irq)) { 3454 if (irq_remapped(irq)) {
3471 struct irq_desc *desc = irq_to_desc(irq); 3455 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3472 /*
3473 * irq migration in process context
3474 */
3475 desc->status |= IRQ_MOVE_PCNTXT;
3476 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); 3456 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3477 } else 3457 } else
3478 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); 3458 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
@@ -3484,13 +3464,10 @@ static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3484 3464
3485int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 3465int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3486{ 3466{
3487 unsigned int irq; 3467 int node, ret, sub_handle, index = 0;
3488 int ret, sub_handle; 3468 unsigned int irq, irq_want;
3489 struct msi_desc *msidesc; 3469 struct msi_desc *msidesc;
3490 unsigned int irq_want;
3491 struct intel_iommu *iommu = NULL; 3470 struct intel_iommu *iommu = NULL;
3492 int index = 0;
3493 int node;
3494 3471
3495 /* x86 doesn't support multiple MSI yet */ 3472 /* x86 doesn't support multiple MSI yet */
3496 if (type == PCI_CAP_ID_MSI && nvec > 1) 3473 if (type == PCI_CAP_ID_MSI && nvec > 1)
@@ -3676,7 +3653,7 @@ int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3676 return ret; 3653 return ret;
3677 3654
3678 hpet_msi_write(get_irq_data(irq), &msg); 3655 hpet_msi_write(get_irq_data(irq), &msg);
3679 irq_set_status_flags(irq,IRQ_MOVE_PCNTXT); 3656 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3680 if (irq_remapped(irq)) 3657 if (irq_remapped(irq))
3681 set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type, 3658 set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
3682 handle_edge_irq, "edge"); 3659 handle_edge_irq, "edge");
@@ -3862,11 +3839,12 @@ static int __io_apic_set_pci_routing(struct device *dev, int irq,
3862 trigger = irq_attr->trigger; 3839 trigger = irq_attr->trigger;
3863 polarity = irq_attr->polarity; 3840 polarity = irq_attr->polarity;
3864 3841
3842 cfg = get_irq_desc_chip_data(desc);
3843
3865 /* 3844 /*
3866 * IRQs < 16 are already in the irq_2_pin[] map 3845 * IRQs < 16 are already in the irq_2_pin[] map
3867 */ 3846 */
3868 if (irq >= legacy_pic->nr_legacy_irqs) { 3847 if (irq >= legacy_pic->nr_legacy_irqs) {
3869 cfg = get_irq_desc_chip_data(desc);
3870 if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) { 3848 if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
3871 printk(KERN_INFO "can not add pin %d for irq %d\n", 3849 printk(KERN_INFO "can not add pin %d for irq %d\n",
3872 pin, irq); 3850 pin, irq);
@@ -3874,7 +3852,7 @@ static int __io_apic_set_pci_routing(struct device *dev, int irq,
3874 } 3852 }
3875 } 3853 }
3876 3854
3877 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity); 3855 setup_ioapic_irq(ioapic, pin, irq, cfg, trigger, polarity);
3878 3856
3879 return 0; 3857 return 0;
3880} 3858}
@@ -4258,13 +4236,12 @@ void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4258void __init pre_init_apic_IRQ0(void) 4236void __init pre_init_apic_IRQ0(void)
4259{ 4237{
4260 struct irq_cfg *cfg; 4238 struct irq_cfg *cfg;
4261 struct irq_desc *desc;
4262 4239
4263 printk(KERN_INFO "Early APIC setup for system timer0\n"); 4240 printk(KERN_INFO "Early APIC setup for system timer0\n");
4264#ifndef CONFIG_SMP 4241#ifndef CONFIG_SMP
4265 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); 4242 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
4266#endif 4243#endif
4267 desc = irq_to_desc_alloc_node(0, 0); 4244 irq_to_desc_alloc_node(0, 0);
4268 4245
4269 setup_local_APIC(); 4246 setup_local_APIC();
4270 4247
@@ -4272,5 +4249,5 @@ void __init pre_init_apic_IRQ0(void)
4272 add_pin_to_irq_node(cfg, 0, 0, 0); 4249 add_pin_to_irq_node(cfg, 0, 0, 0);
4273 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); 4250 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
4274 4251
4275 setup_IO_APIC_irq(0, 0, 0, desc, 0, 0); 4252 setup_ioapic_irq(0, 0, 0, cfg, 0, 0);
4276} 4253}