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authorThomas Gleixner <tglx@linutronix.de>2011-03-12 06:20:43 -0500
committerThomas Gleixner <tglx@linutronix.de>2011-03-12 08:12:00 -0500
commit2c778651f73d92edb847e65d371bb29b17c7ca60 (patch)
tree1ddea54ef26bc40c4abc6594ca3f394aed91e17a /arch/x86/kernel/apic/io_apic.c
parentc1c5e4d463f844e5d44cafab752049267c102ca3 (diff)
x86: Cleanup the genirq name space
genirq is switching to a consistent name space for the irq related functions. Convert x86. Conversion was done with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/kernel/apic/io_apic.c')
-rw-r--r--arch/x86/kernel/apic/io_apic.c75
1 files changed, 39 insertions, 36 deletions
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 8d23e831a45e..7a88b04202e2 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -187,7 +187,7 @@ int __init arch_early_irq_init(void)
187 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs); 187 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
188 188
189 for (i = 0; i < count; i++) { 189 for (i = 0; i < count; i++) {
190 set_irq_chip_data(i, &cfg[i]); 190 irq_set_chip_data(i, &cfg[i]);
191 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node); 191 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
192 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node); 192 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
193 /* 193 /*
@@ -206,7 +206,7 @@ int __init arch_early_irq_init(void)
206#ifdef CONFIG_SPARSE_IRQ 206#ifdef CONFIG_SPARSE_IRQ
207static struct irq_cfg *irq_cfg(unsigned int irq) 207static struct irq_cfg *irq_cfg(unsigned int irq)
208{ 208{
209 return get_irq_chip_data(irq); 209 return irq_get_chip_data(irq);
210} 210}
211 211
212static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) 212static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
@@ -232,7 +232,7 @@ static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
232{ 232{
233 if (!cfg) 233 if (!cfg)
234 return; 234 return;
235 set_irq_chip_data(at, NULL); 235 irq_set_chip_data(at, NULL);
236 free_cpumask_var(cfg->domain); 236 free_cpumask_var(cfg->domain);
237 free_cpumask_var(cfg->old_domain); 237 free_cpumask_var(cfg->old_domain);
238 kfree(cfg); 238 kfree(cfg);
@@ -262,14 +262,14 @@ static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
262 if (res < 0) { 262 if (res < 0) {
263 if (res != -EEXIST) 263 if (res != -EEXIST)
264 return NULL; 264 return NULL;
265 cfg = get_irq_chip_data(at); 265 cfg = irq_get_chip_data(at);
266 if (cfg) 266 if (cfg)
267 return cfg; 267 return cfg;
268 } 268 }
269 269
270 cfg = alloc_irq_cfg(at, node); 270 cfg = alloc_irq_cfg(at, node);
271 if (cfg) 271 if (cfg)
272 set_irq_chip_data(at, cfg); 272 irq_set_chip_data(at, cfg);
273 else 273 else
274 irq_free_desc(at); 274 irq_free_desc(at);
275 return cfg; 275 return cfg;
@@ -1185,7 +1185,7 @@ void __setup_vector_irq(int cpu)
1185 raw_spin_lock(&vector_lock); 1185 raw_spin_lock(&vector_lock);
1186 /* Mark the inuse vectors */ 1186 /* Mark the inuse vectors */
1187 for_each_active_irq(irq) { 1187 for_each_active_irq(irq) {
1188 cfg = get_irq_chip_data(irq); 1188 cfg = irq_get_chip_data(irq);
1189 if (!cfg) 1189 if (!cfg)
1190 continue; 1190 continue;
1191 /* 1191 /*
@@ -1249,25 +1249,24 @@ static void ioapic_register_intr(unsigned int irq, unsigned long trigger)
1249 else 1249 else
1250 irq_clear_status_flags(irq, IRQ_LEVEL); 1250 irq_clear_status_flags(irq, IRQ_LEVEL);
1251 1251
1252 if (irq_remapped(get_irq_chip_data(irq))) { 1252 if (irq_remapped(irq_get_chip_data(irq))) {
1253 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); 1253 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1254 if (trigger) 1254 if (trigger)
1255 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, 1255 irq_set_chip_and_handler_name(irq, &ir_ioapic_chip,
1256 handle_fasteoi_irq, 1256 handle_fasteoi_irq,
1257 "fasteoi"); 1257 "fasteoi");
1258 else 1258 else
1259 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, 1259 irq_set_chip_and_handler_name(irq, &ir_ioapic_chip,
1260 handle_edge_irq, "edge"); 1260 handle_edge_irq, "edge");
1261 return; 1261 return;
1262 } 1262 }
1263 1263
1264 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || 1264 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1265 trigger == IOAPIC_LEVEL) 1265 trigger == IOAPIC_LEVEL)
1266 set_irq_chip_and_handler_name(irq, &ioapic_chip, 1266 irq_set_chip_and_handler_name(irq, &ioapic_chip,
1267 handle_fasteoi_irq, 1267 handle_fasteoi_irq, "fasteoi");
1268 "fasteoi");
1269 else 1268 else
1270 set_irq_chip_and_handler_name(irq, &ioapic_chip, 1269 irq_set_chip_and_handler_name(irq, &ioapic_chip,
1271 handle_edge_irq, "edge"); 1270 handle_edge_irq, "edge");
1272} 1271}
1273 1272
@@ -1491,7 +1490,8 @@ static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1491 * The timer IRQ doesn't have to know that behind the 1490 * The timer IRQ doesn't have to know that behind the
1492 * scene we may have a 8259A-master in AEOI mode ... 1491 * scene we may have a 8259A-master in AEOI mode ...
1493 */ 1492 */
1494 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); 1493 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1494 "edge");
1495 1495
1496 /* 1496 /*
1497 * Add it to the IO-APIC irq-routing table: 1497 * Add it to the IO-APIC irq-routing table:
@@ -1598,7 +1598,7 @@ __apicdebuginit(void) print_IO_APIC(void)
1598 for_each_active_irq(irq) { 1598 for_each_active_irq(irq) {
1599 struct irq_pin_list *entry; 1599 struct irq_pin_list *entry;
1600 1600
1601 cfg = get_irq_chip_data(irq); 1601 cfg = irq_get_chip_data(irq);
1602 if (!cfg) 1602 if (!cfg)
1603 continue; 1603 continue;
1604 entry = cfg->irq_2_pin; 1604 entry = cfg->irq_2_pin;
@@ -2364,7 +2364,7 @@ static void irq_complete_move(struct irq_cfg *cfg)
2364 2364
2365void irq_force_complete_move(int irq) 2365void irq_force_complete_move(int irq)
2366{ 2366{
2367 struct irq_cfg *cfg = get_irq_chip_data(irq); 2367 struct irq_cfg *cfg = irq_get_chip_data(irq);
2368 2368
2369 if (!cfg) 2369 if (!cfg)
2370 return; 2370 return;
@@ -2587,7 +2587,7 @@ static inline void init_IO_APIC_traps(void)
2587 * 0x80, because int 0x80 is hm, kind of importantish. ;) 2587 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2588 */ 2588 */
2589 for_each_active_irq(irq) { 2589 for_each_active_irq(irq) {
2590 cfg = get_irq_chip_data(irq); 2590 cfg = irq_get_chip_data(irq);
2591 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { 2591 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2592 /* 2592 /*
2593 * Hmm.. We don't have an entry for this, 2593 * Hmm.. We don't have an entry for this,
@@ -2598,7 +2598,7 @@ static inline void init_IO_APIC_traps(void)
2598 legacy_pic->make_irq(irq); 2598 legacy_pic->make_irq(irq);
2599 else 2599 else
2600 /* Strange. Oh, well.. */ 2600 /* Strange. Oh, well.. */
2601 set_irq_chip(irq, &no_irq_chip); 2601 irq_set_chip(irq, &no_irq_chip);
2602 } 2602 }
2603 } 2603 }
2604} 2604}
@@ -2638,7 +2638,7 @@ static struct irq_chip lapic_chip __read_mostly = {
2638static void lapic_register_intr(int irq) 2638static void lapic_register_intr(int irq)
2639{ 2639{
2640 irq_clear_status_flags(irq, IRQ_LEVEL); 2640 irq_clear_status_flags(irq, IRQ_LEVEL);
2641 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, 2641 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2642 "edge"); 2642 "edge");
2643} 2643}
2644 2644
@@ -2722,7 +2722,7 @@ int timer_through_8259 __initdata;
2722 */ 2722 */
2723static inline void __init check_timer(void) 2723static inline void __init check_timer(void)
2724{ 2724{
2725 struct irq_cfg *cfg = get_irq_chip_data(0); 2725 struct irq_cfg *cfg = irq_get_chip_data(0);
2726 int node = cpu_to_node(0); 2726 int node = cpu_to_node(0);
2727 int apic1, pin1, apic2, pin2; 2727 int apic1, pin1, apic2, pin2;
2728 unsigned long flags; 2728 unsigned long flags;
@@ -3033,7 +3033,7 @@ unsigned int create_irq_nr(unsigned int from, int node)
3033 raw_spin_unlock_irqrestore(&vector_lock, flags); 3033 raw_spin_unlock_irqrestore(&vector_lock, flags);
3034 3034
3035 if (ret) { 3035 if (ret) {
3036 set_irq_chip_data(irq, cfg); 3036 irq_set_chip_data(irq, cfg);
3037 irq_clear_status_flags(irq, IRQ_NOREQUEST); 3037 irq_clear_status_flags(irq, IRQ_NOREQUEST);
3038 } else { 3038 } else {
3039 free_irq_at(irq, cfg); 3039 free_irq_at(irq, cfg);
@@ -3058,7 +3058,7 @@ int create_irq(void)
3058 3058
3059void destroy_irq(unsigned int irq) 3059void destroy_irq(unsigned int irq)
3060{ 3060{
3061 struct irq_cfg *cfg = get_irq_chip_data(irq); 3061 struct irq_cfg *cfg = irq_get_chip_data(irq);
3062 unsigned long flags; 3062 unsigned long flags;
3063 3063
3064 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE); 3064 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
@@ -3092,7 +3092,7 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3092 3092
3093 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); 3093 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3094 3094
3095 if (irq_remapped(get_irq_chip_data(irq))) { 3095 if (irq_remapped(irq_get_chip_data(irq))) {
3096 struct irte irte; 3096 struct irte irte;
3097 int ir_index; 3097 int ir_index;
3098 u16 sub_handle; 3098 u16 sub_handle;
@@ -3271,14 +3271,16 @@ static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3271 if (ret < 0) 3271 if (ret < 0)
3272 return ret; 3272 return ret;
3273 3273
3274 set_irq_msi(irq, msidesc); 3274 irq_set_msi_desc(irq, msidesc);
3275 write_msi_msg(irq, &msg); 3275 write_msi_msg(irq, &msg);
3276 3276
3277 if (irq_remapped(get_irq_chip_data(irq))) { 3277 if (irq_remapped(irq_get_chip_data(irq))) {
3278 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); 3278 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3279 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); 3279 irq_set_chip_and_handler_name(irq, &msi_ir_chip,
3280 handle_edge_irq, "edge");
3280 } else 3281 } else
3281 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); 3282 irq_set_chip_and_handler_name(irq, &msi_chip,
3283 handle_edge_irq, "edge");
3282 3284
3283 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); 3285 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3284 3286
@@ -3396,8 +3398,8 @@ int arch_setup_dmar_msi(unsigned int irq)
3396 if (ret < 0) 3398 if (ret < 0)
3397 return ret; 3399 return ret;
3398 dmar_msi_write(irq, &msg); 3400 dmar_msi_write(irq, &msg);
3399 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, 3401 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3400 "edge"); 3402 "edge");
3401 return 0; 3403 return 0;
3402} 3404}
3403#endif 3405#endif
@@ -3474,13 +3476,13 @@ int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3474 if (ret < 0) 3476 if (ret < 0)
3475 return ret; 3477 return ret;
3476 3478
3477 hpet_msi_write(get_irq_data(irq), &msg); 3479 hpet_msi_write(irq_get_handler_data(irq), &msg);
3478 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); 3480 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3479 if (irq_remapped(get_irq_chip_data(irq))) 3481 if (irq_remapped(irq_get_chip_data(irq)))
3480 set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type, 3482 irq_set_chip_and_handler_name(irq, &ir_hpet_msi_type,
3481 handle_edge_irq, "edge"); 3483 handle_edge_irq, "edge");
3482 else 3484 else
3483 set_irq_chip_and_handler_name(irq, &hpet_msi_type, 3485 irq_set_chip_and_handler_name(irq, &hpet_msi_type,
3484 handle_edge_irq, "edge"); 3486 handle_edge_irq, "edge");
3485 3487
3486 return 0; 3488 return 0;
@@ -3569,7 +3571,7 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3569 3571
3570 write_ht_irq_msg(irq, &msg); 3572 write_ht_irq_msg(irq, &msg);
3571 3573
3572 set_irq_chip_and_handler_name(irq, &ht_irq_chip, 3574 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3573 handle_edge_irq, "edge"); 3575 handle_edge_irq, "edge");
3574 3576
3575 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); 3577 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
@@ -4054,5 +4056,6 @@ void __init pre_init_apic_IRQ0(void)
4054 setup_local_APIC(); 4056 setup_local_APIC();
4055 4057
4056 io_apic_setup_irq_pin(0, 0, &attr); 4058 io_apic_setup_irq_pin(0, 0, &attr);
4057 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); 4059 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
4060 "edge");
4058} 4061}