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authorDavid S. Miller <davem@davemloft.net>2010-01-23 01:45:46 -0500
committerDavid S. Miller <davem@davemloft.net>2010-01-23 01:45:46 -0500
commit6be325719b3e54624397e413efd4b33a997e55a3 (patch)
tree57f321a56794cab2222e179b16731e0d76a4a68a /arch/x86/kernel/apic/apic.c
parent26d92f9276a56d55511a427fb70bd70886af647a (diff)
parent92dcffb916d309aa01778bf8963a6932e4014d07 (diff)
Merge branch 'master' of /home/davem/src/GIT/linux-2.6/
Diffstat (limited to 'arch/x86/kernel/apic/apic.c')
-rw-r--r--arch/x86/kernel/apic/apic.c25
1 files changed, 11 insertions, 14 deletions
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index efb2b9cd132c..3987e4408f75 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -61,12 +61,6 @@ unsigned int boot_cpu_physical_apicid = -1U;
61 61
62/* 62/*
63 * The highest APIC ID seen during enumeration. 63 * The highest APIC ID seen during enumeration.
64 *
65 * On AMD, this determines the messaging protocol we can use: if all APIC IDs
66 * are in the 0 ... 7 range, then we can use logical addressing which
67 * has some performance advantages (better broadcasting).
68 *
69 * If there's an APIC ID above 8, we use physical addressing.
70 */ 64 */
71unsigned int max_physical_apicid; 65unsigned int max_physical_apicid;
72 66
@@ -1341,7 +1335,7 @@ void enable_x2apic(void)
1341 1335
1342 rdmsr(MSR_IA32_APICBASE, msr, msr2); 1336 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1343 if (!(msr & X2APIC_ENABLE)) { 1337 if (!(msr & X2APIC_ENABLE)) {
1344 pr_info("Enabling x2apic\n"); 1338 printk_once(KERN_INFO "Enabling x2apic\n");
1345 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); 1339 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1346 } 1340 }
1347} 1341}
@@ -1898,14 +1892,17 @@ void __cpuinit generic_processor_info(int apicid, int version)
1898 max_physical_apicid = apicid; 1892 max_physical_apicid = apicid;
1899 1893
1900#ifdef CONFIG_X86_32 1894#ifdef CONFIG_X86_32
1901 switch (boot_cpu_data.x86_vendor) { 1895 if (num_processors > 8) {
1902 case X86_VENDOR_INTEL: 1896 switch (boot_cpu_data.x86_vendor) {
1903 if (num_processors > 8) 1897 case X86_VENDOR_INTEL:
1904 def_to_bigsmp = 1; 1898 if (!APIC_XAPIC(version)) {
1905 break; 1899 def_to_bigsmp = 0;
1906 case X86_VENDOR_AMD: 1900 break;
1907 if (max_physical_apicid >= 8) 1901 }
1902 /* If P4 and above fall through */
1903 case X86_VENDOR_AMD:
1908 def_to_bigsmp = 1; 1904 def_to_bigsmp = 1;
1905 }
1909 } 1906 }
1910#endif 1907#endif
1911 1908