diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-12-28 15:07:57 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-12-28 15:07:57 -0500 |
commit | be9c5ae4eeec2e85527e95647348b8ea4eb25128 (patch) | |
tree | 59383b15bc0891b8a44500a0ac172a8850f1068d /arch/x86/kernel/apic.c | |
parent | bb26c6c29b7cc9f39e491b074b09f3c284738d36 (diff) | |
parent | 79a66b96c339626a3e4b226fefc0e45244cfe6ff (diff) |
Merge branch 'x86-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (246 commits)
x86: traps.c replace #if CONFIG_X86_32 with #ifdef CONFIG_X86_32
x86: PAT: fix address types in track_pfn_vma_new()
x86: prioritize the FPU traps for the error code
x86: PAT: pfnmap documentation update changes
x86: PAT: move track untrack pfnmap stubs to asm-generic
x86: PAT: remove follow_pfnmap_pte in favor of follow_phys
x86: PAT: modify follow_phys to return phys_addr prot and return value
x86: PAT: clarify is_linear_pfn_mapping() interface
x86: ia32_signal: remove unnecessary declaration
x86: common.c boot_cpu_stack and boot_exception_stacks should be static
x86: fix intel x86_64 llc_shared_map/cpu_llc_id anomolies
x86: fix warning in arch/x86/kernel/microcode_amd.c
x86: ia32.h: remove unused struct sigfram32 and rt_sigframe32
x86: asm-offset_64: use rt_sigframe_ia32
x86: sigframe.h: include headers for dependency
x86: traps.c declare functions before they get used
x86: PAT: update documentation to cover pgprot and remap_pfn related changes - v3
x86: PAT: add pgprot_writecombine() interface for drivers - v3
x86: PAT: change pgprot_noncached to uc_minus instead of strong uc - v3
x86: PAT: implement track/untrack of pfnmap regions for x86 - v3
...
Diffstat (limited to 'arch/x86/kernel/apic.c')
-rw-r--r-- | arch/x86/kernel/apic.c | 140 |
1 files changed, 57 insertions, 83 deletions
diff --git a/arch/x86/kernel/apic.c b/arch/x86/kernel/apic.c index 16f94879b525..7397911f8478 100644 --- a/arch/x86/kernel/apic.c +++ b/arch/x86/kernel/apic.c | |||
@@ -441,6 +441,7 @@ static void lapic_timer_setup(enum clock_event_mode mode, | |||
441 | v = apic_read(APIC_LVTT); | 441 | v = apic_read(APIC_LVTT); |
442 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | 442 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); |
443 | apic_write(APIC_LVTT, v); | 443 | apic_write(APIC_LVTT, v); |
444 | apic_write(APIC_TMICT, 0xffffffff); | ||
444 | break; | 445 | break; |
445 | case CLOCK_EVT_MODE_RESUME: | 446 | case CLOCK_EVT_MODE_RESUME: |
446 | /* Nothing to do here */ | 447 | /* Nothing to do here */ |
@@ -559,13 +560,13 @@ static int __init calibrate_by_pmtimer(long deltapm, long *delta) | |||
559 | } else { | 560 | } else { |
560 | res = (((u64)deltapm) * mult) >> 22; | 561 | res = (((u64)deltapm) * mult) >> 22; |
561 | do_div(res, 1000000); | 562 | do_div(res, 1000000); |
562 | printk(KERN_WARNING "APIC calibration not consistent " | 563 | pr_warning("APIC calibration not consistent " |
563 | "with PM Timer: %ldms instead of 100ms\n", | 564 | "with PM Timer: %ldms instead of 100ms\n", |
564 | (long)res); | 565 | (long)res); |
565 | /* Correct the lapic counter value */ | 566 | /* Correct the lapic counter value */ |
566 | res = (((u64)(*delta)) * pm_100ms); | 567 | res = (((u64)(*delta)) * pm_100ms); |
567 | do_div(res, deltapm); | 568 | do_div(res, deltapm); |
568 | printk(KERN_INFO "APIC delta adjusted to PM-Timer: " | 569 | pr_info("APIC delta adjusted to PM-Timer: " |
569 | "%lu (%ld)\n", (unsigned long)res, *delta); | 570 | "%lu (%ld)\n", (unsigned long)res, *delta); |
570 | *delta = (long)res; | 571 | *delta = (long)res; |
571 | } | 572 | } |
@@ -645,8 +646,7 @@ static int __init calibrate_APIC_clock(void) | |||
645 | */ | 646 | */ |
646 | if (calibration_result < (1000000 / HZ)) { | 647 | if (calibration_result < (1000000 / HZ)) { |
647 | local_irq_enable(); | 648 | local_irq_enable(); |
648 | printk(KERN_WARNING | 649 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
649 | "APIC frequency too slow, disabling apic timer\n"); | ||
650 | return -1; | 650 | return -1; |
651 | } | 651 | } |
652 | 652 | ||
@@ -672,13 +672,9 @@ static int __init calibrate_APIC_clock(void) | |||
672 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | 672 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
673 | cpu_relax(); | 673 | cpu_relax(); |
674 | 674 | ||
675 | local_irq_disable(); | ||
676 | |||
677 | /* Stop the lapic timer */ | 675 | /* Stop the lapic timer */ |
678 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | 676 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); |
679 | 677 | ||
680 | local_irq_enable(); | ||
681 | |||
682 | /* Jiffies delta */ | 678 | /* Jiffies delta */ |
683 | deltaj = lapic_cal_j2 - lapic_cal_j1; | 679 | deltaj = lapic_cal_j2 - lapic_cal_j1; |
684 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | 680 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); |
@@ -692,8 +688,7 @@ static int __init calibrate_APIC_clock(void) | |||
692 | local_irq_enable(); | 688 | local_irq_enable(); |
693 | 689 | ||
694 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | 690 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { |
695 | printk(KERN_WARNING | 691 | pr_warning("APIC timer disabled due to verification failure.\n"); |
696 | "APIC timer disabled due to verification failure.\n"); | ||
697 | return -1; | 692 | return -1; |
698 | } | 693 | } |
699 | 694 | ||
@@ -714,7 +709,7 @@ void __init setup_boot_APIC_clock(void) | |||
714 | * broadcast mechanism is used. On UP systems simply ignore it. | 709 | * broadcast mechanism is used. On UP systems simply ignore it. |
715 | */ | 710 | */ |
716 | if (disable_apic_timer) { | 711 | if (disable_apic_timer) { |
717 | printk(KERN_INFO "Disabling APIC timer\n"); | 712 | pr_info("Disabling APIC timer\n"); |
718 | /* No broadcast on UP ! */ | 713 | /* No broadcast on UP ! */ |
719 | if (num_possible_cpus() > 1) { | 714 | if (num_possible_cpus() > 1) { |
720 | lapic_clockevent.mult = 1; | 715 | lapic_clockevent.mult = 1; |
@@ -741,7 +736,7 @@ void __init setup_boot_APIC_clock(void) | |||
741 | if (nmi_watchdog != NMI_IO_APIC) | 736 | if (nmi_watchdog != NMI_IO_APIC) |
742 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | 737 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
743 | else | 738 | else |
744 | printk(KERN_WARNING "APIC timer registered as dummy," | 739 | pr_warning("APIC timer registered as dummy," |
745 | " due to nmi_watchdog=%d!\n", nmi_watchdog); | 740 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
746 | 741 | ||
747 | /* Setup the lapic or request the broadcast */ | 742 | /* Setup the lapic or request the broadcast */ |
@@ -773,8 +768,7 @@ static void local_apic_timer_interrupt(void) | |||
773 | * spurious. | 768 | * spurious. |
774 | */ | 769 | */ |
775 | if (!evt->event_handler) { | 770 | if (!evt->event_handler) { |
776 | printk(KERN_WARNING | 771 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
777 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | ||
778 | /* Switch it off */ | 772 | /* Switch it off */ |
779 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | 773 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); |
780 | return; | 774 | return; |
@@ -783,11 +777,7 @@ static void local_apic_timer_interrupt(void) | |||
783 | /* | 777 | /* |
784 | * the NMI deadlock-detector uses this. | 778 | * the NMI deadlock-detector uses this. |
785 | */ | 779 | */ |
786 | #ifdef CONFIG_X86_64 | 780 | inc_irq_stat(apic_timer_irqs); |
787 | add_pda(apic_timer_irqs, 1); | ||
788 | #else | ||
789 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | ||
790 | #endif | ||
791 | 781 | ||
792 | evt->event_handler(evt); | 782 | evt->event_handler(evt); |
793 | } | 783 | } |
@@ -814,9 +804,7 @@ void smp_apic_timer_interrupt(struct pt_regs *regs) | |||
814 | * Besides, if we don't timer interrupts ignore the global | 804 | * Besides, if we don't timer interrupts ignore the global |
815 | * interrupt lock, which is the WrongThing (tm) to do. | 805 | * interrupt lock, which is the WrongThing (tm) to do. |
816 | */ | 806 | */ |
817 | #ifdef CONFIG_X86_64 | ||
818 | exit_idle(); | 807 | exit_idle(); |
819 | #endif | ||
820 | irq_enter(); | 808 | irq_enter(); |
821 | local_apic_timer_interrupt(); | 809 | local_apic_timer_interrupt(); |
822 | irq_exit(); | 810 | irq_exit(); |
@@ -1093,7 +1081,7 @@ static void __cpuinit lapic_setup_esr(void) | |||
1093 | unsigned int oldvalue, value, maxlvt; | 1081 | unsigned int oldvalue, value, maxlvt; |
1094 | 1082 | ||
1095 | if (!lapic_is_integrated()) { | 1083 | if (!lapic_is_integrated()) { |
1096 | printk(KERN_INFO "No ESR for 82489DX.\n"); | 1084 | pr_info("No ESR for 82489DX.\n"); |
1097 | return; | 1085 | return; |
1098 | } | 1086 | } |
1099 | 1087 | ||
@@ -1104,7 +1092,7 @@ static void __cpuinit lapic_setup_esr(void) | |||
1104 | * ESR disabled - we can't do anything useful with the | 1092 | * ESR disabled - we can't do anything useful with the |
1105 | * errors anyway - mbligh | 1093 | * errors anyway - mbligh |
1106 | */ | 1094 | */ |
1107 | printk(KERN_INFO "Leaving ESR disabled.\n"); | 1095 | pr_info("Leaving ESR disabled.\n"); |
1108 | return; | 1096 | return; |
1109 | } | 1097 | } |
1110 | 1098 | ||
@@ -1298,7 +1286,7 @@ void check_x2apic(void) | |||
1298 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | 1286 | rdmsr(MSR_IA32_APICBASE, msr, msr2); |
1299 | 1287 | ||
1300 | if (msr & X2APIC_ENABLE) { | 1288 | if (msr & X2APIC_ENABLE) { |
1301 | printk("x2apic enabled by BIOS, switching to x2apic ops\n"); | 1289 | pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); |
1302 | x2apic_preenabled = x2apic = 1; | 1290 | x2apic_preenabled = x2apic = 1; |
1303 | apic_ops = &x2apic_ops; | 1291 | apic_ops = &x2apic_ops; |
1304 | } | 1292 | } |
@@ -1310,7 +1298,7 @@ void enable_x2apic(void) | |||
1310 | 1298 | ||
1311 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | 1299 | rdmsr(MSR_IA32_APICBASE, msr, msr2); |
1312 | if (!(msr & X2APIC_ENABLE)) { | 1300 | if (!(msr & X2APIC_ENABLE)) { |
1313 | printk("Enabling x2apic\n"); | 1301 | pr_info("Enabling x2apic\n"); |
1314 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); | 1302 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); |
1315 | } | 1303 | } |
1316 | } | 1304 | } |
@@ -1325,9 +1313,8 @@ void __init enable_IR_x2apic(void) | |||
1325 | return; | 1313 | return; |
1326 | 1314 | ||
1327 | if (!x2apic_preenabled && disable_x2apic) { | 1315 | if (!x2apic_preenabled && disable_x2apic) { |
1328 | printk(KERN_INFO | 1316 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1329 | "Skipped enabling x2apic and Interrupt-remapping " | 1317 | "because of nox2apic\n"); |
1330 | "because of nox2apic\n"); | ||
1331 | return; | 1318 | return; |
1332 | } | 1319 | } |
1333 | 1320 | ||
@@ -1335,22 +1322,19 @@ void __init enable_IR_x2apic(void) | |||
1335 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | 1322 | panic("Bios already enabled x2apic, can't enforce nox2apic"); |
1336 | 1323 | ||
1337 | if (!x2apic_preenabled && skip_ioapic_setup) { | 1324 | if (!x2apic_preenabled && skip_ioapic_setup) { |
1338 | printk(KERN_INFO | 1325 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1339 | "Skipped enabling x2apic and Interrupt-remapping " | 1326 | "because of skipping io-apic setup\n"); |
1340 | "because of skipping io-apic setup\n"); | ||
1341 | return; | 1327 | return; |
1342 | } | 1328 | } |
1343 | 1329 | ||
1344 | ret = dmar_table_init(); | 1330 | ret = dmar_table_init(); |
1345 | if (ret) { | 1331 | if (ret) { |
1346 | printk(KERN_INFO | 1332 | pr_info("dmar_table_init() failed with %d:\n", ret); |
1347 | "dmar_table_init() failed with %d:\n", ret); | ||
1348 | 1333 | ||
1349 | if (x2apic_preenabled) | 1334 | if (x2apic_preenabled) |
1350 | panic("x2apic enabled by bios. But IR enabling failed"); | 1335 | panic("x2apic enabled by bios. But IR enabling failed"); |
1351 | else | 1336 | else |
1352 | printk(KERN_INFO | 1337 | pr_info("Not enabling x2apic,Intr-remapping\n"); |
1353 | "Not enabling x2apic,Intr-remapping\n"); | ||
1354 | return; | 1338 | return; |
1355 | } | 1339 | } |
1356 | 1340 | ||
@@ -1359,7 +1343,7 @@ void __init enable_IR_x2apic(void) | |||
1359 | 1343 | ||
1360 | ret = save_mask_IO_APIC_setup(); | 1344 | ret = save_mask_IO_APIC_setup(); |
1361 | if (ret) { | 1345 | if (ret) { |
1362 | printk(KERN_INFO "Saving IO-APIC state failed: %d\n", ret); | 1346 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
1363 | goto end; | 1347 | goto end; |
1364 | } | 1348 | } |
1365 | 1349 | ||
@@ -1394,14 +1378,11 @@ end: | |||
1394 | 1378 | ||
1395 | if (!ret) { | 1379 | if (!ret) { |
1396 | if (!x2apic_preenabled) | 1380 | if (!x2apic_preenabled) |
1397 | printk(KERN_INFO | 1381 | pr_info("Enabled x2apic and interrupt-remapping\n"); |
1398 | "Enabled x2apic and interrupt-remapping\n"); | ||
1399 | else | 1382 | else |
1400 | printk(KERN_INFO | 1383 | pr_info("Enabled Interrupt-remapping\n"); |
1401 | "Enabled Interrupt-remapping\n"); | ||
1402 | } else | 1384 | } else |
1403 | printk(KERN_ERR | 1385 | pr_err("Failed to enable Interrupt-remapping and x2apic\n"); |
1404 | "Failed to enable Interrupt-remapping and x2apic\n"); | ||
1405 | #else | 1386 | #else |
1406 | if (!cpu_has_x2apic) | 1387 | if (!cpu_has_x2apic) |
1407 | return; | 1388 | return; |
@@ -1410,8 +1391,8 @@ end: | |||
1410 | panic("x2apic enabled prior OS handover," | 1391 | panic("x2apic enabled prior OS handover," |
1411 | " enable CONFIG_INTR_REMAP"); | 1392 | " enable CONFIG_INTR_REMAP"); |
1412 | 1393 | ||
1413 | printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping " | 1394 | pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping " |
1414 | " and x2apic\n"); | 1395 | " and x2apic\n"); |
1415 | #endif | 1396 | #endif |
1416 | 1397 | ||
1417 | return; | 1398 | return; |
@@ -1428,7 +1409,7 @@ end: | |||
1428 | static int __init detect_init_APIC(void) | 1409 | static int __init detect_init_APIC(void) |
1429 | { | 1410 | { |
1430 | if (!cpu_has_apic) { | 1411 | if (!cpu_has_apic) { |
1431 | printk(KERN_INFO "No local APIC present\n"); | 1412 | pr_info("No local APIC present\n"); |
1432 | return -1; | 1413 | return -1; |
1433 | } | 1414 | } |
1434 | 1415 | ||
@@ -1469,8 +1450,8 @@ static int __init detect_init_APIC(void) | |||
1469 | * "lapic" specified. | 1450 | * "lapic" specified. |
1470 | */ | 1451 | */ |
1471 | if (!force_enable_local_apic) { | 1452 | if (!force_enable_local_apic) { |
1472 | printk(KERN_INFO "Local APIC disabled by BIOS -- " | 1453 | pr_info("Local APIC disabled by BIOS -- " |
1473 | "you can enable it with \"lapic\"\n"); | 1454 | "you can enable it with \"lapic\"\n"); |
1474 | return -1; | 1455 | return -1; |
1475 | } | 1456 | } |
1476 | /* | 1457 | /* |
@@ -1480,8 +1461,7 @@ static int __init detect_init_APIC(void) | |||
1480 | */ | 1461 | */ |
1481 | rdmsr(MSR_IA32_APICBASE, l, h); | 1462 | rdmsr(MSR_IA32_APICBASE, l, h); |
1482 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | 1463 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { |
1483 | printk(KERN_INFO | 1464 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); |
1484 | "Local APIC disabled by BIOS -- reenabling.\n"); | ||
1485 | l &= ~MSR_IA32_APICBASE_BASE; | 1465 | l &= ~MSR_IA32_APICBASE_BASE; |
1486 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | 1466 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; |
1487 | wrmsr(MSR_IA32_APICBASE, l, h); | 1467 | wrmsr(MSR_IA32_APICBASE, l, h); |
@@ -1494,7 +1474,7 @@ static int __init detect_init_APIC(void) | |||
1494 | */ | 1474 | */ |
1495 | features = cpuid_edx(1); | 1475 | features = cpuid_edx(1); |
1496 | if (!(features & (1 << X86_FEATURE_APIC))) { | 1476 | if (!(features & (1 << X86_FEATURE_APIC))) { |
1497 | printk(KERN_WARNING "Could not enable APIC!\n"); | 1477 | pr_warning("Could not enable APIC!\n"); |
1498 | return -1; | 1478 | return -1; |
1499 | } | 1479 | } |
1500 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | 1480 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
@@ -1505,14 +1485,14 @@ static int __init detect_init_APIC(void) | |||
1505 | if (l & MSR_IA32_APICBASE_ENABLE) | 1485 | if (l & MSR_IA32_APICBASE_ENABLE) |
1506 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | 1486 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; |
1507 | 1487 | ||
1508 | printk(KERN_INFO "Found and enabled local APIC!\n"); | 1488 | pr_info("Found and enabled local APIC!\n"); |
1509 | 1489 | ||
1510 | apic_pm_activate(); | 1490 | apic_pm_activate(); |
1511 | 1491 | ||
1512 | return 0; | 1492 | return 0; |
1513 | 1493 | ||
1514 | no_apic: | 1494 | no_apic: |
1515 | printk(KERN_INFO "No local APIC present or hardware disabled\n"); | 1495 | pr_info("No local APIC present or hardware disabled\n"); |
1516 | return -1; | 1496 | return -1; |
1517 | } | 1497 | } |
1518 | #endif | 1498 | #endif |
@@ -1588,12 +1568,12 @@ int __init APIC_init_uniprocessor(void) | |||
1588 | { | 1568 | { |
1589 | #ifdef CONFIG_X86_64 | 1569 | #ifdef CONFIG_X86_64 |
1590 | if (disable_apic) { | 1570 | if (disable_apic) { |
1591 | printk(KERN_INFO "Apic disabled\n"); | 1571 | pr_info("Apic disabled\n"); |
1592 | return -1; | 1572 | return -1; |
1593 | } | 1573 | } |
1594 | if (!cpu_has_apic) { | 1574 | if (!cpu_has_apic) { |
1595 | disable_apic = 1; | 1575 | disable_apic = 1; |
1596 | printk(KERN_INFO "Apic disabled by BIOS\n"); | 1576 | pr_info("Apic disabled by BIOS\n"); |
1597 | return -1; | 1577 | return -1; |
1598 | } | 1578 | } |
1599 | #else | 1579 | #else |
@@ -1605,8 +1585,8 @@ int __init APIC_init_uniprocessor(void) | |||
1605 | */ | 1585 | */ |
1606 | if (!cpu_has_apic && | 1586 | if (!cpu_has_apic && |
1607 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | 1587 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
1608 | printk(KERN_ERR "BIOS bug, local APIC 0x%x not detected!...\n", | 1588 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
1609 | boot_cpu_physical_apicid); | 1589 | boot_cpu_physical_apicid); |
1610 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | 1590 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1611 | return -1; | 1591 | return -1; |
1612 | } | 1592 | } |
@@ -1682,9 +1662,7 @@ void smp_spurious_interrupt(struct pt_regs *regs) | |||
1682 | { | 1662 | { |
1683 | u32 v; | 1663 | u32 v; |
1684 | 1664 | ||
1685 | #ifdef CONFIG_X86_64 | ||
1686 | exit_idle(); | 1665 | exit_idle(); |
1687 | #endif | ||
1688 | irq_enter(); | 1666 | irq_enter(); |
1689 | /* | 1667 | /* |
1690 | * Check if this really is a spurious interrupt and ACK it | 1668 | * Check if this really is a spurious interrupt and ACK it |
@@ -1695,14 +1673,11 @@ void smp_spurious_interrupt(struct pt_regs *regs) | |||
1695 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | 1673 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) |
1696 | ack_APIC_irq(); | 1674 | ack_APIC_irq(); |
1697 | 1675 | ||
1698 | #ifdef CONFIG_X86_64 | 1676 | inc_irq_stat(irq_spurious_count); |
1699 | add_pda(irq_spurious_count, 1); | 1677 | |
1700 | #else | ||
1701 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | 1678 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
1702 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, " | 1679 | pr_info("spurious APIC interrupt on CPU#%d, " |
1703 | "should never happen.\n", smp_processor_id()); | 1680 | "should never happen.\n", smp_processor_id()); |
1704 | __get_cpu_var(irq_stat).irq_spurious_count++; | ||
1705 | #endif | ||
1706 | irq_exit(); | 1681 | irq_exit(); |
1707 | } | 1682 | } |
1708 | 1683 | ||
@@ -1713,9 +1688,7 @@ void smp_error_interrupt(struct pt_regs *regs) | |||
1713 | { | 1688 | { |
1714 | u32 v, v1; | 1689 | u32 v, v1; |
1715 | 1690 | ||
1716 | #ifdef CONFIG_X86_64 | ||
1717 | exit_idle(); | 1691 | exit_idle(); |
1718 | #endif | ||
1719 | irq_enter(); | 1692 | irq_enter(); |
1720 | /* First tickle the hardware, only then report what went on. -- REW */ | 1693 | /* First tickle the hardware, only then report what went on. -- REW */ |
1721 | v = apic_read(APIC_ESR); | 1694 | v = apic_read(APIC_ESR); |
@@ -1724,17 +1697,18 @@ void smp_error_interrupt(struct pt_regs *regs) | |||
1724 | ack_APIC_irq(); | 1697 | ack_APIC_irq(); |
1725 | atomic_inc(&irq_err_count); | 1698 | atomic_inc(&irq_err_count); |
1726 | 1699 | ||
1727 | /* Here is what the APIC error bits mean: | 1700 | /* |
1728 | 0: Send CS error | 1701 | * Here is what the APIC error bits mean: |
1729 | 1: Receive CS error | 1702 | * 0: Send CS error |
1730 | 2: Send accept error | 1703 | * 1: Receive CS error |
1731 | 3: Receive accept error | 1704 | * 2: Send accept error |
1732 | 4: Reserved | 1705 | * 3: Receive accept error |
1733 | 5: Send illegal vector | 1706 | * 4: Reserved |
1734 | 6: Received illegal vector | 1707 | * 5: Send illegal vector |
1735 | 7: Illegal register address | 1708 | * 6: Received illegal vector |
1736 | */ | 1709 | * 7: Illegal register address |
1737 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | 1710 | */ |
1711 | pr_debug("APIC error on CPU%d: %02x(%02x)\n", | ||
1738 | smp_processor_id(), v , v1); | 1712 | smp_processor_id(), v , v1); |
1739 | irq_exit(); | 1713 | irq_exit(); |
1740 | } | 1714 | } |
@@ -1838,15 +1812,15 @@ void __cpuinit generic_processor_info(int apicid, int version) | |||
1838 | * Validate version | 1812 | * Validate version |
1839 | */ | 1813 | */ |
1840 | if (version == 0x0) { | 1814 | if (version == 0x0) { |
1841 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " | 1815 | pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " |
1842 | "fixing up to 0x10. (tell your hw vendor)\n", | 1816 | "fixing up to 0x10. (tell your hw vendor)\n", |
1843 | version); | 1817 | version); |
1844 | version = 0x10; | 1818 | version = 0x10; |
1845 | } | 1819 | } |
1846 | apic_version[apicid] = version; | 1820 | apic_version[apicid] = version; |
1847 | 1821 | ||
1848 | if (num_processors >= NR_CPUS) { | 1822 | if (num_processors >= NR_CPUS) { |
1849 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | 1823 | pr_warning("WARNING: NR_CPUS limit of %i reached." |
1850 | " Processor ignored.\n", NR_CPUS); | 1824 | " Processor ignored.\n", NR_CPUS); |
1851 | return; | 1825 | return; |
1852 | } | 1826 | } |
@@ -2209,7 +2183,7 @@ static int __init apic_set_verbosity(char *arg) | |||
2209 | else if (strcmp("verbose", arg) == 0) | 2183 | else if (strcmp("verbose", arg) == 0) |
2210 | apic_verbosity = APIC_VERBOSE; | 2184 | apic_verbosity = APIC_VERBOSE; |
2211 | else { | 2185 | else { |
2212 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | 2186 | pr_warning("APIC Verbosity level %s not recognised" |
2213 | " use apic=verbose or apic=debug\n", arg); | 2187 | " use apic=verbose or apic=debug\n", arg); |
2214 | return -EINVAL; | 2188 | return -EINVAL; |
2215 | } | 2189 | } |