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authorIngo Molnar <mingo@elte.hu>2009-02-17 12:09:24 -0500
committerIngo Molnar <mingo@elte.hu>2009-02-17 12:17:36 -0500
commitf62bae5009c1ba596cd475cafbc83e0570a36e26 (patch)
tree0c5a3000c566f42a7cc25d6c03d69d20b9bd0166 /arch/x86/kernel/apic.c
parentbe163a159b223e94b3180afdd47a8d468eb9a492 (diff)
x86, apic: move APIC drivers to arch/x86/kernel/apic/*
arch/x86/kernel/ is getting a bit crowded, and the APIC drivers are scattered into various different files. Move them to arch/x86/kernel/apic/*, and also remove the 'gen' prefix from those which had it. Also move APIC related functionality: the IO-APIC driver, the NMI and the IPI code. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/apic.c')
-rw-r--r--arch/x86/kernel/apic.c2212
1 files changed, 0 insertions, 2212 deletions
diff --git a/arch/x86/kernel/apic.c b/arch/x86/kernel/apic.c
deleted file mode 100644
index c12823eb55b5..000000000000
--- a/arch/x86/kernel/apic.c
+++ /dev/null
@@ -1,2212 +0,0 @@
1/*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
17#include <linux/kernel_stat.h>
18#include <linux/mc146818rtc.h>
19#include <linux/acpi_pmtmr.h>
20#include <linux/clockchips.h>
21#include <linux/interrupt.h>
22#include <linux/bootmem.h>
23#include <linux/ftrace.h>
24#include <linux/ioport.h>
25#include <linux/module.h>
26#include <linux/sysdev.h>
27#include <linux/delay.h>
28#include <linux/timex.h>
29#include <linux/dmar.h>
30#include <linux/init.h>
31#include <linux/cpu.h>
32#include <linux/dmi.h>
33#include <linux/nmi.h>
34#include <linux/smp.h>
35#include <linux/mm.h>
36
37#include <asm/arch_hooks.h>
38#include <asm/pgalloc.h>
39#include <asm/atomic.h>
40#include <asm/mpspec.h>
41#include <asm/i8253.h>
42#include <asm/i8259.h>
43#include <asm/proto.h>
44#include <asm/apic.h>
45#include <asm/desc.h>
46#include <asm/hpet.h>
47#include <asm/idle.h>
48#include <asm/mtrr.h>
49#include <asm/smp.h>
50
51unsigned int num_processors;
52
53unsigned disabled_cpus __cpuinitdata;
54
55/* Processor that is doing the boot up */
56unsigned int boot_cpu_physical_apicid = -1U;
57
58/*
59 * The highest APIC ID seen during enumeration.
60 *
61 * This determines the messaging protocol we can use: if all APIC IDs
62 * are in the 0 ... 7 range, then we can use logical addressing which
63 * has some performance advantages (better broadcasting).
64 *
65 * If there's an APIC ID above 8, we use physical addressing.
66 */
67unsigned int max_physical_apicid;
68
69/*
70 * Bitmask of physically existing CPUs:
71 */
72physid_mask_t phys_cpu_present_map;
73
74/*
75 * Map cpu index to physical APIC ID
76 */
77DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
78DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
79EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
80EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
81
82#ifdef CONFIG_X86_32
83/*
84 * Knob to control our willingness to enable the local APIC.
85 *
86 * +1=force-enable
87 */
88static int force_enable_local_apic;
89/*
90 * APIC command line parameters
91 */
92static int __init parse_lapic(char *arg)
93{
94 force_enable_local_apic = 1;
95 return 0;
96}
97early_param("lapic", parse_lapic);
98/* Local APIC was disabled by the BIOS and enabled by the kernel */
99static int enabled_via_apicbase;
100
101#endif
102
103#ifdef CONFIG_X86_64
104static int apic_calibrate_pmtmr __initdata;
105static __init int setup_apicpmtimer(char *s)
106{
107 apic_calibrate_pmtmr = 1;
108 notsc_setup(NULL);
109 return 0;
110}
111__setup("apicpmtimer", setup_apicpmtimer);
112#endif
113
114#ifdef CONFIG_X86_X2APIC
115int x2apic;
116/* x2apic enabled before OS handover */
117static int x2apic_preenabled;
118static int disable_x2apic;
119static __init int setup_nox2apic(char *str)
120{
121 disable_x2apic = 1;
122 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
123 return 0;
124}
125early_param("nox2apic", setup_nox2apic);
126#endif
127
128unsigned long mp_lapic_addr;
129int disable_apic;
130/* Disable local APIC timer from the kernel commandline or via dmi quirk */
131static int disable_apic_timer __cpuinitdata;
132/* Local APIC timer works in C2 */
133int local_apic_timer_c2_ok;
134EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
135
136int first_system_vector = 0xfe;
137
138/*
139 * Debug level, exported for io_apic.c
140 */
141unsigned int apic_verbosity;
142
143int pic_mode;
144
145/* Have we found an MP table */
146int smp_found_config;
147
148static struct resource lapic_resource = {
149 .name = "Local APIC",
150 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
151};
152
153static unsigned int calibration_result;
154
155static int lapic_next_event(unsigned long delta,
156 struct clock_event_device *evt);
157static void lapic_timer_setup(enum clock_event_mode mode,
158 struct clock_event_device *evt);
159static void lapic_timer_broadcast(const struct cpumask *mask);
160static void apic_pm_activate(void);
161
162/*
163 * The local apic timer can be used for any function which is CPU local.
164 */
165static struct clock_event_device lapic_clockevent = {
166 .name = "lapic",
167 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
168 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
169 .shift = 32,
170 .set_mode = lapic_timer_setup,
171 .set_next_event = lapic_next_event,
172 .broadcast = lapic_timer_broadcast,
173 .rating = 100,
174 .irq = -1,
175};
176static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
177
178static unsigned long apic_phys;
179
180/*
181 * Get the LAPIC version
182 */
183static inline int lapic_get_version(void)
184{
185 return GET_APIC_VERSION(apic_read(APIC_LVR));
186}
187
188/*
189 * Check, if the APIC is integrated or a separate chip
190 */
191static inline int lapic_is_integrated(void)
192{
193#ifdef CONFIG_X86_64
194 return 1;
195#else
196 return APIC_INTEGRATED(lapic_get_version());
197#endif
198}
199
200/*
201 * Check, whether this is a modern or a first generation APIC
202 */
203static int modern_apic(void)
204{
205 /* AMD systems use old APIC versions, so check the CPU */
206 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
207 boot_cpu_data.x86 >= 0xf)
208 return 1;
209 return lapic_get_version() >= 0x14;
210}
211
212void native_apic_wait_icr_idle(void)
213{
214 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
215 cpu_relax();
216}
217
218u32 native_safe_apic_wait_icr_idle(void)
219{
220 u32 send_status;
221 int timeout;
222
223 timeout = 0;
224 do {
225 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
226 if (!send_status)
227 break;
228 udelay(100);
229 } while (timeout++ < 1000);
230
231 return send_status;
232}
233
234void native_apic_icr_write(u32 low, u32 id)
235{
236 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
237 apic_write(APIC_ICR, low);
238}
239
240u64 native_apic_icr_read(void)
241{
242 u32 icr1, icr2;
243
244 icr2 = apic_read(APIC_ICR2);
245 icr1 = apic_read(APIC_ICR);
246
247 return icr1 | ((u64)icr2 << 32);
248}
249
250/**
251 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
252 */
253void __cpuinit enable_NMI_through_LVT0(void)
254{
255 unsigned int v;
256
257 /* unmask and set to NMI */
258 v = APIC_DM_NMI;
259
260 /* Level triggered for 82489DX (32bit mode) */
261 if (!lapic_is_integrated())
262 v |= APIC_LVT_LEVEL_TRIGGER;
263
264 apic_write(APIC_LVT0, v);
265}
266
267#ifdef CONFIG_X86_32
268/**
269 * get_physical_broadcast - Get number of physical broadcast IDs
270 */
271int get_physical_broadcast(void)
272{
273 return modern_apic() ? 0xff : 0xf;
274}
275#endif
276
277/**
278 * lapic_get_maxlvt - get the maximum number of local vector table entries
279 */
280int lapic_get_maxlvt(void)
281{
282 unsigned int v;
283
284 v = apic_read(APIC_LVR);
285 /*
286 * - we always have APIC integrated on 64bit mode
287 * - 82489DXs do not report # of LVT entries
288 */
289 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
290}
291
292/*
293 * Local APIC timer
294 */
295
296/* Clock divisor */
297#define APIC_DIVISOR 16
298
299/*
300 * This function sets up the local APIC timer, with a timeout of
301 * 'clocks' APIC bus clock. During calibration we actually call
302 * this function twice on the boot CPU, once with a bogus timeout
303 * value, second time for real. The other (noncalibrating) CPUs
304 * call this function only once, with the real, calibrated value.
305 *
306 * We do reads before writes even if unnecessary, to get around the
307 * P5 APIC double write bug.
308 */
309static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
310{
311 unsigned int lvtt_value, tmp_value;
312
313 lvtt_value = LOCAL_TIMER_VECTOR;
314 if (!oneshot)
315 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
316 if (!lapic_is_integrated())
317 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
318
319 if (!irqen)
320 lvtt_value |= APIC_LVT_MASKED;
321
322 apic_write(APIC_LVTT, lvtt_value);
323
324 /*
325 * Divide PICLK by 16
326 */
327 tmp_value = apic_read(APIC_TDCR);
328 apic_write(APIC_TDCR,
329 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
330 APIC_TDR_DIV_16);
331
332 if (!oneshot)
333 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
334}
335
336/*
337 * Setup extended LVT, AMD specific (K8, family 10h)
338 *
339 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
340 * MCE interrupts are supported. Thus MCE offset must be set to 0.
341 *
342 * If mask=1, the LVT entry does not generate interrupts while mask=0
343 * enables the vector. See also the BKDGs.
344 */
345
346#define APIC_EILVT_LVTOFF_MCE 0
347#define APIC_EILVT_LVTOFF_IBS 1
348
349static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
350{
351 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
352 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
353
354 apic_write(reg, v);
355}
356
357u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
358{
359 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
360 return APIC_EILVT_LVTOFF_MCE;
361}
362
363u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
364{
365 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
366 return APIC_EILVT_LVTOFF_IBS;
367}
368EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
369
370/*
371 * Program the next event, relative to now
372 */
373static int lapic_next_event(unsigned long delta,
374 struct clock_event_device *evt)
375{
376 apic_write(APIC_TMICT, delta);
377 return 0;
378}
379
380/*
381 * Setup the lapic timer in periodic or oneshot mode
382 */
383static void lapic_timer_setup(enum clock_event_mode mode,
384 struct clock_event_device *evt)
385{
386 unsigned long flags;
387 unsigned int v;
388
389 /* Lapic used as dummy for broadcast ? */
390 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
391 return;
392
393 local_irq_save(flags);
394
395 switch (mode) {
396 case CLOCK_EVT_MODE_PERIODIC:
397 case CLOCK_EVT_MODE_ONESHOT:
398 __setup_APIC_LVTT(calibration_result,
399 mode != CLOCK_EVT_MODE_PERIODIC, 1);
400 break;
401 case CLOCK_EVT_MODE_UNUSED:
402 case CLOCK_EVT_MODE_SHUTDOWN:
403 v = apic_read(APIC_LVTT);
404 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
405 apic_write(APIC_LVTT, v);
406 apic_write(APIC_TMICT, 0xffffffff);
407 break;
408 case CLOCK_EVT_MODE_RESUME:
409 /* Nothing to do here */
410 break;
411 }
412
413 local_irq_restore(flags);
414}
415
416/*
417 * Local APIC timer broadcast function
418 */
419static void lapic_timer_broadcast(const struct cpumask *mask)
420{
421#ifdef CONFIG_SMP
422 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
423#endif
424}
425
426/*
427 * Setup the local APIC timer for this CPU. Copy the initilized values
428 * of the boot CPU and register the clock event in the framework.
429 */
430static void __cpuinit setup_APIC_timer(void)
431{
432 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
433
434 memcpy(levt, &lapic_clockevent, sizeof(*levt));
435 levt->cpumask = cpumask_of(smp_processor_id());
436
437 clockevents_register_device(levt);
438}
439
440/*
441 * In this functions we calibrate APIC bus clocks to the external timer.
442 *
443 * We want to do the calibration only once since we want to have local timer
444 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
445 * frequency.
446 *
447 * This was previously done by reading the PIT/HPET and waiting for a wrap
448 * around to find out, that a tick has elapsed. I have a box, where the PIT
449 * readout is broken, so it never gets out of the wait loop again. This was
450 * also reported by others.
451 *
452 * Monitoring the jiffies value is inaccurate and the clockevents
453 * infrastructure allows us to do a simple substitution of the interrupt
454 * handler.
455 *
456 * The calibration routine also uses the pm_timer when possible, as the PIT
457 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
458 * back to normal later in the boot process).
459 */
460
461#define LAPIC_CAL_LOOPS (HZ/10)
462
463static __initdata int lapic_cal_loops = -1;
464static __initdata long lapic_cal_t1, lapic_cal_t2;
465static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
466static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
467static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
468
469/*
470 * Temporary interrupt handler.
471 */
472static void __init lapic_cal_handler(struct clock_event_device *dev)
473{
474 unsigned long long tsc = 0;
475 long tapic = apic_read(APIC_TMCCT);
476 unsigned long pm = acpi_pm_read_early();
477
478 if (cpu_has_tsc)
479 rdtscll(tsc);
480
481 switch (lapic_cal_loops++) {
482 case 0:
483 lapic_cal_t1 = tapic;
484 lapic_cal_tsc1 = tsc;
485 lapic_cal_pm1 = pm;
486 lapic_cal_j1 = jiffies;
487 break;
488
489 case LAPIC_CAL_LOOPS:
490 lapic_cal_t2 = tapic;
491 lapic_cal_tsc2 = tsc;
492 if (pm < lapic_cal_pm1)
493 pm += ACPI_PM_OVRRUN;
494 lapic_cal_pm2 = pm;
495 lapic_cal_j2 = jiffies;
496 break;
497 }
498}
499
500static int __init
501calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
502{
503 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
504 const long pm_thresh = pm_100ms / 100;
505 unsigned long mult;
506 u64 res;
507
508#ifndef CONFIG_X86_PM_TIMER
509 return -1;
510#endif
511
512 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
513
514 /* Check, if the PM timer is available */
515 if (!deltapm)
516 return -1;
517
518 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
519
520 if (deltapm > (pm_100ms - pm_thresh) &&
521 deltapm < (pm_100ms + pm_thresh)) {
522 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
523 return 0;
524 }
525
526 res = (((u64)deltapm) * mult) >> 22;
527 do_div(res, 1000000);
528 pr_warning("APIC calibration not consistent "
529 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
530
531 /* Correct the lapic counter value */
532 res = (((u64)(*delta)) * pm_100ms);
533 do_div(res, deltapm);
534 pr_info("APIC delta adjusted to PM-Timer: "
535 "%lu (%ld)\n", (unsigned long)res, *delta);
536 *delta = (long)res;
537
538 /* Correct the tsc counter value */
539 if (cpu_has_tsc) {
540 res = (((u64)(*deltatsc)) * pm_100ms);
541 do_div(res, deltapm);
542 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
543 "PM-Timer: %lu (%ld) \n",
544 (unsigned long)res, *deltatsc);
545 *deltatsc = (long)res;
546 }
547
548 return 0;
549}
550
551static int __init calibrate_APIC_clock(void)
552{
553 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
554 void (*real_handler)(struct clock_event_device *dev);
555 unsigned long deltaj;
556 long delta, deltatsc;
557 int pm_referenced = 0;
558
559 local_irq_disable();
560
561 /* Replace the global interrupt handler */
562 real_handler = global_clock_event->event_handler;
563 global_clock_event->event_handler = lapic_cal_handler;
564
565 /*
566 * Setup the APIC counter to maximum. There is no way the lapic
567 * can underflow in the 100ms detection time frame
568 */
569 __setup_APIC_LVTT(0xffffffff, 0, 0);
570
571 /* Let the interrupts run */
572 local_irq_enable();
573
574 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
575 cpu_relax();
576
577 local_irq_disable();
578
579 /* Restore the real event handler */
580 global_clock_event->event_handler = real_handler;
581
582 /* Build delta t1-t2 as apic timer counts down */
583 delta = lapic_cal_t1 - lapic_cal_t2;
584 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
585
586 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
587
588 /* we trust the PM based calibration if possible */
589 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
590 &delta, &deltatsc);
591
592 /* Calculate the scaled math multiplication factor */
593 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
594 lapic_clockevent.shift);
595 lapic_clockevent.max_delta_ns =
596 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
597 lapic_clockevent.min_delta_ns =
598 clockevent_delta2ns(0xF, &lapic_clockevent);
599
600 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
601
602 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
603 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
604 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
605 calibration_result);
606
607 if (cpu_has_tsc) {
608 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
609 "%ld.%04ld MHz.\n",
610 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
611 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
612 }
613
614 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
615 "%u.%04u MHz.\n",
616 calibration_result / (1000000 / HZ),
617 calibration_result % (1000000 / HZ));
618
619 /*
620 * Do a sanity check on the APIC calibration result
621 */
622 if (calibration_result < (1000000 / HZ)) {
623 local_irq_enable();
624 pr_warning("APIC frequency too slow, disabling apic timer\n");
625 return -1;
626 }
627
628 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
629
630 /*
631 * PM timer calibration failed or not turned on
632 * so lets try APIC timer based calibration
633 */
634 if (!pm_referenced) {
635 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
636
637 /*
638 * Setup the apic timer manually
639 */
640 levt->event_handler = lapic_cal_handler;
641 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
642 lapic_cal_loops = -1;
643
644 /* Let the interrupts run */
645 local_irq_enable();
646
647 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
648 cpu_relax();
649
650 /* Stop the lapic timer */
651 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
652
653 /* Jiffies delta */
654 deltaj = lapic_cal_j2 - lapic_cal_j1;
655 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
656
657 /* Check, if the jiffies result is consistent */
658 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
659 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
660 else
661 levt->features |= CLOCK_EVT_FEAT_DUMMY;
662 } else
663 local_irq_enable();
664
665 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
666 pr_warning("APIC timer disabled due to verification failure\n");
667 return -1;
668 }
669
670 return 0;
671}
672
673/*
674 * Setup the boot APIC
675 *
676 * Calibrate and verify the result.
677 */
678void __init setup_boot_APIC_clock(void)
679{
680 /*
681 * The local apic timer can be disabled via the kernel
682 * commandline or from the CPU detection code. Register the lapic
683 * timer as a dummy clock event source on SMP systems, so the
684 * broadcast mechanism is used. On UP systems simply ignore it.
685 */
686 if (disable_apic_timer) {
687 pr_info("Disabling APIC timer\n");
688 /* No broadcast on UP ! */
689 if (num_possible_cpus() > 1) {
690 lapic_clockevent.mult = 1;
691 setup_APIC_timer();
692 }
693 return;
694 }
695
696 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
697 "calibrating APIC timer ...\n");
698
699 if (calibrate_APIC_clock()) {
700 /* No broadcast on UP ! */
701 if (num_possible_cpus() > 1)
702 setup_APIC_timer();
703 return;
704 }
705
706 /*
707 * If nmi_watchdog is set to IO_APIC, we need the
708 * PIT/HPET going. Otherwise register lapic as a dummy
709 * device.
710 */
711 if (nmi_watchdog != NMI_IO_APIC)
712 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
713 else
714 pr_warning("APIC timer registered as dummy,"
715 " due to nmi_watchdog=%d!\n", nmi_watchdog);
716
717 /* Setup the lapic or request the broadcast */
718 setup_APIC_timer();
719}
720
721void __cpuinit setup_secondary_APIC_clock(void)
722{
723 setup_APIC_timer();
724}
725
726/*
727 * The guts of the apic timer interrupt
728 */
729static void local_apic_timer_interrupt(void)
730{
731 int cpu = smp_processor_id();
732 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
733
734 /*
735 * Normally we should not be here till LAPIC has been initialized but
736 * in some cases like kdump, its possible that there is a pending LAPIC
737 * timer interrupt from previous kernel's context and is delivered in
738 * new kernel the moment interrupts are enabled.
739 *
740 * Interrupts are enabled early and LAPIC is setup much later, hence
741 * its possible that when we get here evt->event_handler is NULL.
742 * Check for event_handler being NULL and discard the interrupt as
743 * spurious.
744 */
745 if (!evt->event_handler) {
746 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
747 /* Switch it off */
748 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
749 return;
750 }
751
752 /*
753 * the NMI deadlock-detector uses this.
754 */
755 inc_irq_stat(apic_timer_irqs);
756
757 evt->event_handler(evt);
758}
759
760/*
761 * Local APIC timer interrupt. This is the most natural way for doing
762 * local interrupts, but local timer interrupts can be emulated by
763 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
764 *
765 * [ if a single-CPU system runs an SMP kernel then we call the local
766 * interrupt as well. Thus we cannot inline the local irq ... ]
767 */
768void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
769{
770 struct pt_regs *old_regs = set_irq_regs(regs);
771
772 /*
773 * NOTE! We'd better ACK the irq immediately,
774 * because timer handling can be slow.
775 */
776 ack_APIC_irq();
777 /*
778 * update_process_times() expects us to have done irq_enter().
779 * Besides, if we don't timer interrupts ignore the global
780 * interrupt lock, which is the WrongThing (tm) to do.
781 */
782 exit_idle();
783 irq_enter();
784 local_apic_timer_interrupt();
785 irq_exit();
786
787 set_irq_regs(old_regs);
788}
789
790int setup_profiling_timer(unsigned int multiplier)
791{
792 return -EINVAL;
793}
794
795/*
796 * Local APIC start and shutdown
797 */
798
799/**
800 * clear_local_APIC - shutdown the local APIC
801 *
802 * This is called, when a CPU is disabled and before rebooting, so the state of
803 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
804 * leftovers during boot.
805 */
806void clear_local_APIC(void)
807{
808 int maxlvt;
809 u32 v;
810
811 /* APIC hasn't been mapped yet */
812 if (!apic_phys)
813 return;
814
815 maxlvt = lapic_get_maxlvt();
816 /*
817 * Masking an LVT entry can trigger a local APIC error
818 * if the vector is zero. Mask LVTERR first to prevent this.
819 */
820 if (maxlvt >= 3) {
821 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
822 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
823 }
824 /*
825 * Careful: we have to set masks only first to deassert
826 * any level-triggered sources.
827 */
828 v = apic_read(APIC_LVTT);
829 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
830 v = apic_read(APIC_LVT0);
831 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
832 v = apic_read(APIC_LVT1);
833 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
834 if (maxlvt >= 4) {
835 v = apic_read(APIC_LVTPC);
836 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
837 }
838
839 /* lets not touch this if we didn't frob it */
840#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
841 if (maxlvt >= 5) {
842 v = apic_read(APIC_LVTTHMR);
843 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
844 }
845#endif
846 /*
847 * Clean APIC state for other OSs:
848 */
849 apic_write(APIC_LVTT, APIC_LVT_MASKED);
850 apic_write(APIC_LVT0, APIC_LVT_MASKED);
851 apic_write(APIC_LVT1, APIC_LVT_MASKED);
852 if (maxlvt >= 3)
853 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
854 if (maxlvt >= 4)
855 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
856
857 /* Integrated APIC (!82489DX) ? */
858 if (lapic_is_integrated()) {
859 if (maxlvt > 3)
860 /* Clear ESR due to Pentium errata 3AP and 11AP */
861 apic_write(APIC_ESR, 0);
862 apic_read(APIC_ESR);
863 }
864}
865
866/**
867 * disable_local_APIC - clear and disable the local APIC
868 */
869void disable_local_APIC(void)
870{
871 unsigned int value;
872
873 /* APIC hasn't been mapped yet */
874 if (!apic_phys)
875 return;
876
877 clear_local_APIC();
878
879 /*
880 * Disable APIC (implies clearing of registers
881 * for 82489DX!).
882 */
883 value = apic_read(APIC_SPIV);
884 value &= ~APIC_SPIV_APIC_ENABLED;
885 apic_write(APIC_SPIV, value);
886
887#ifdef CONFIG_X86_32
888 /*
889 * When LAPIC was disabled by the BIOS and enabled by the kernel,
890 * restore the disabled state.
891 */
892 if (enabled_via_apicbase) {
893 unsigned int l, h;
894
895 rdmsr(MSR_IA32_APICBASE, l, h);
896 l &= ~MSR_IA32_APICBASE_ENABLE;
897 wrmsr(MSR_IA32_APICBASE, l, h);
898 }
899#endif
900}
901
902/*
903 * If Linux enabled the LAPIC against the BIOS default disable it down before
904 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
905 * not power-off. Additionally clear all LVT entries before disable_local_APIC
906 * for the case where Linux didn't enable the LAPIC.
907 */
908void lapic_shutdown(void)
909{
910 unsigned long flags;
911
912 if (!cpu_has_apic)
913 return;
914
915 local_irq_save(flags);
916
917#ifdef CONFIG_X86_32
918 if (!enabled_via_apicbase)
919 clear_local_APIC();
920 else
921#endif
922 disable_local_APIC();
923
924
925 local_irq_restore(flags);
926}
927
928/*
929 * This is to verify that we're looking at a real local APIC.
930 * Check these against your board if the CPUs aren't getting
931 * started for no apparent reason.
932 */
933int __init verify_local_APIC(void)
934{
935 unsigned int reg0, reg1;
936
937 /*
938 * The version register is read-only in a real APIC.
939 */
940 reg0 = apic_read(APIC_LVR);
941 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
942 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
943 reg1 = apic_read(APIC_LVR);
944 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
945
946 /*
947 * The two version reads above should print the same
948 * numbers. If the second one is different, then we
949 * poke at a non-APIC.
950 */
951 if (reg1 != reg0)
952 return 0;
953
954 /*
955 * Check if the version looks reasonably.
956 */
957 reg1 = GET_APIC_VERSION(reg0);
958 if (reg1 == 0x00 || reg1 == 0xff)
959 return 0;
960 reg1 = lapic_get_maxlvt();
961 if (reg1 < 0x02 || reg1 == 0xff)
962 return 0;
963
964 /*
965 * The ID register is read/write in a real APIC.
966 */
967 reg0 = apic_read(APIC_ID);
968 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
969 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
970 reg1 = apic_read(APIC_ID);
971 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
972 apic_write(APIC_ID, reg0);
973 if (reg1 != (reg0 ^ apic->apic_id_mask))
974 return 0;
975
976 /*
977 * The next two are just to see if we have sane values.
978 * They're only really relevant if we're in Virtual Wire
979 * compatibility mode, but most boxes are anymore.
980 */
981 reg0 = apic_read(APIC_LVT0);
982 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
983 reg1 = apic_read(APIC_LVT1);
984 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
985
986 return 1;
987}
988
989/**
990 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
991 */
992void __init sync_Arb_IDs(void)
993{
994 /*
995 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
996 * needed on AMD.
997 */
998 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
999 return;
1000
1001 /*
1002 * Wait for idle.
1003 */
1004 apic_wait_icr_idle();
1005
1006 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1007 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1008 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1009}
1010
1011/*
1012 * An initial setup of the virtual wire mode.
1013 */
1014void __init init_bsp_APIC(void)
1015{
1016 unsigned int value;
1017
1018 /*
1019 * Don't do the setup now if we have a SMP BIOS as the
1020 * through-I/O-APIC virtual wire mode might be active.
1021 */
1022 if (smp_found_config || !cpu_has_apic)
1023 return;
1024
1025 /*
1026 * Do not trust the local APIC being empty at bootup.
1027 */
1028 clear_local_APIC();
1029
1030 /*
1031 * Enable APIC.
1032 */
1033 value = apic_read(APIC_SPIV);
1034 value &= ~APIC_VECTOR_MASK;
1035 value |= APIC_SPIV_APIC_ENABLED;
1036
1037#ifdef CONFIG_X86_32
1038 /* This bit is reserved on P4/Xeon and should be cleared */
1039 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1040 (boot_cpu_data.x86 == 15))
1041 value &= ~APIC_SPIV_FOCUS_DISABLED;
1042 else
1043#endif
1044 value |= APIC_SPIV_FOCUS_DISABLED;
1045 value |= SPURIOUS_APIC_VECTOR;
1046 apic_write(APIC_SPIV, value);
1047
1048 /*
1049 * Set up the virtual wire mode.
1050 */
1051 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1052 value = APIC_DM_NMI;
1053 if (!lapic_is_integrated()) /* 82489DX */
1054 value |= APIC_LVT_LEVEL_TRIGGER;
1055 apic_write(APIC_LVT1, value);
1056}
1057
1058static void __cpuinit lapic_setup_esr(void)
1059{
1060 unsigned int oldvalue, value, maxlvt;
1061
1062 if (!lapic_is_integrated()) {
1063 pr_info("No ESR for 82489DX.\n");
1064 return;
1065 }
1066
1067 if (apic->disable_esr) {
1068 /*
1069 * Something untraceable is creating bad interrupts on
1070 * secondary quads ... for the moment, just leave the
1071 * ESR disabled - we can't do anything useful with the
1072 * errors anyway - mbligh
1073 */
1074 pr_info("Leaving ESR disabled.\n");
1075 return;
1076 }
1077
1078 maxlvt = lapic_get_maxlvt();
1079 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1080 apic_write(APIC_ESR, 0);
1081 oldvalue = apic_read(APIC_ESR);
1082
1083 /* enables sending errors */
1084 value = ERROR_APIC_VECTOR;
1085 apic_write(APIC_LVTERR, value);
1086
1087 /*
1088 * spec says clear errors after enabling vector.
1089 */
1090 if (maxlvt > 3)
1091 apic_write(APIC_ESR, 0);
1092 value = apic_read(APIC_ESR);
1093 if (value != oldvalue)
1094 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1095 "vector: 0x%08x after: 0x%08x\n",
1096 oldvalue, value);
1097}
1098
1099
1100/**
1101 * setup_local_APIC - setup the local APIC
1102 */
1103void __cpuinit setup_local_APIC(void)
1104{
1105 unsigned int value;
1106 int i, j;
1107
1108 if (disable_apic) {
1109 arch_disable_smp_support();
1110 return;
1111 }
1112
1113#ifdef CONFIG_X86_32
1114 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1115 if (lapic_is_integrated() && apic->disable_esr) {
1116 apic_write(APIC_ESR, 0);
1117 apic_write(APIC_ESR, 0);
1118 apic_write(APIC_ESR, 0);
1119 apic_write(APIC_ESR, 0);
1120 }
1121#endif
1122
1123 preempt_disable();
1124
1125 /*
1126 * Double-check whether this APIC is really registered.
1127 * This is meaningless in clustered apic mode, so we skip it.
1128 */
1129 if (!apic->apic_id_registered())
1130 BUG();
1131
1132 /*
1133 * Intel recommends to set DFR, LDR and TPR before enabling
1134 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1135 * document number 292116). So here it goes...
1136 */
1137 apic->init_apic_ldr();
1138
1139 /*
1140 * Set Task Priority to 'accept all'. We never change this
1141 * later on.
1142 */
1143 value = apic_read(APIC_TASKPRI);
1144 value &= ~APIC_TPRI_MASK;
1145 apic_write(APIC_TASKPRI, value);
1146
1147 /*
1148 * After a crash, we no longer service the interrupts and a pending
1149 * interrupt from previous kernel might still have ISR bit set.
1150 *
1151 * Most probably by now CPU has serviced that pending interrupt and
1152 * it might not have done the ack_APIC_irq() because it thought,
1153 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1154 * does not clear the ISR bit and cpu thinks it has already serivced
1155 * the interrupt. Hence a vector might get locked. It was noticed
1156 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1157 */
1158 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1159 value = apic_read(APIC_ISR + i*0x10);
1160 for (j = 31; j >= 0; j--) {
1161 if (value & (1<<j))
1162 ack_APIC_irq();
1163 }
1164 }
1165
1166 /*
1167 * Now that we are all set up, enable the APIC
1168 */
1169 value = apic_read(APIC_SPIV);
1170 value &= ~APIC_VECTOR_MASK;
1171 /*
1172 * Enable APIC
1173 */
1174 value |= APIC_SPIV_APIC_ENABLED;
1175
1176#ifdef CONFIG_X86_32
1177 /*
1178 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1179 * certain networking cards. If high frequency interrupts are
1180 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1181 * entry is masked/unmasked at a high rate as well then sooner or
1182 * later IOAPIC line gets 'stuck', no more interrupts are received
1183 * from the device. If focus CPU is disabled then the hang goes
1184 * away, oh well :-(
1185 *
1186 * [ This bug can be reproduced easily with a level-triggered
1187 * PCI Ne2000 networking cards and PII/PIII processors, dual
1188 * BX chipset. ]
1189 */
1190 /*
1191 * Actually disabling the focus CPU check just makes the hang less
1192 * frequent as it makes the interrupt distributon model be more
1193 * like LRU than MRU (the short-term load is more even across CPUs).
1194 * See also the comment in end_level_ioapic_irq(). --macro
1195 */
1196
1197 /*
1198 * - enable focus processor (bit==0)
1199 * - 64bit mode always use processor focus
1200 * so no need to set it
1201 */
1202 value &= ~APIC_SPIV_FOCUS_DISABLED;
1203#endif
1204
1205 /*
1206 * Set spurious IRQ vector
1207 */
1208 value |= SPURIOUS_APIC_VECTOR;
1209 apic_write(APIC_SPIV, value);
1210
1211 /*
1212 * Set up LVT0, LVT1:
1213 *
1214 * set up through-local-APIC on the BP's LINT0. This is not
1215 * strictly necessary in pure symmetric-IO mode, but sometimes
1216 * we delegate interrupts to the 8259A.
1217 */
1218 /*
1219 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1220 */
1221 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1222 if (!smp_processor_id() && (pic_mode || !value)) {
1223 value = APIC_DM_EXTINT;
1224 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1225 smp_processor_id());
1226 } else {
1227 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1228 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1229 smp_processor_id());
1230 }
1231 apic_write(APIC_LVT0, value);
1232
1233 /*
1234 * only the BP should see the LINT1 NMI signal, obviously.
1235 */
1236 if (!smp_processor_id())
1237 value = APIC_DM_NMI;
1238 else
1239 value = APIC_DM_NMI | APIC_LVT_MASKED;
1240 if (!lapic_is_integrated()) /* 82489DX */
1241 value |= APIC_LVT_LEVEL_TRIGGER;
1242 apic_write(APIC_LVT1, value);
1243
1244 preempt_enable();
1245}
1246
1247void __cpuinit end_local_APIC_setup(void)
1248{
1249 lapic_setup_esr();
1250
1251#ifdef CONFIG_X86_32
1252 {
1253 unsigned int value;
1254 /* Disable the local apic timer */
1255 value = apic_read(APIC_LVTT);
1256 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1257 apic_write(APIC_LVTT, value);
1258 }
1259#endif
1260
1261 setup_apic_nmi_watchdog(NULL);
1262 apic_pm_activate();
1263}
1264
1265#ifdef CONFIG_X86_X2APIC
1266void check_x2apic(void)
1267{
1268 int msr, msr2;
1269
1270 if (!cpu_has_x2apic)
1271 return;
1272
1273 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1274
1275 if (msr & X2APIC_ENABLE) {
1276 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1277 x2apic_preenabled = x2apic = 1;
1278 }
1279}
1280
1281void enable_x2apic(void)
1282{
1283 int msr, msr2;
1284
1285 if (!x2apic)
1286 return;
1287
1288 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1289 if (!(msr & X2APIC_ENABLE)) {
1290 pr_info("Enabling x2apic\n");
1291 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1292 }
1293}
1294
1295void __init enable_IR_x2apic(void)
1296{
1297#ifdef CONFIG_INTR_REMAP
1298 int ret;
1299 unsigned long flags;
1300
1301 if (!cpu_has_x2apic)
1302 return;
1303
1304 if (!x2apic_preenabled && disable_x2apic) {
1305 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1306 "because of nox2apic\n");
1307 return;
1308 }
1309
1310 if (x2apic_preenabled && disable_x2apic)
1311 panic("Bios already enabled x2apic, can't enforce nox2apic");
1312
1313 if (!x2apic_preenabled && skip_ioapic_setup) {
1314 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1315 "because of skipping io-apic setup\n");
1316 return;
1317 }
1318
1319 ret = dmar_table_init();
1320 if (ret) {
1321 pr_info("dmar_table_init() failed with %d:\n", ret);
1322
1323 if (x2apic_preenabled)
1324 panic("x2apic enabled by bios. But IR enabling failed");
1325 else
1326 pr_info("Not enabling x2apic,Intr-remapping\n");
1327 return;
1328 }
1329
1330 local_irq_save(flags);
1331 mask_8259A();
1332
1333 ret = save_mask_IO_APIC_setup();
1334 if (ret) {
1335 pr_info("Saving IO-APIC state failed: %d\n", ret);
1336 goto end;
1337 }
1338
1339 ret = enable_intr_remapping(1);
1340
1341 if (ret && x2apic_preenabled) {
1342 local_irq_restore(flags);
1343 panic("x2apic enabled by bios. But IR enabling failed");
1344 }
1345
1346 if (ret)
1347 goto end_restore;
1348
1349 if (!x2apic) {
1350 x2apic = 1;
1351 enable_x2apic();
1352 }
1353
1354end_restore:
1355 if (ret)
1356 /*
1357 * IR enabling failed
1358 */
1359 restore_IO_APIC_setup();
1360 else
1361 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1362
1363end:
1364 unmask_8259A();
1365 local_irq_restore(flags);
1366
1367 if (!ret) {
1368 if (!x2apic_preenabled)
1369 pr_info("Enabled x2apic and interrupt-remapping\n");
1370 else
1371 pr_info("Enabled Interrupt-remapping\n");
1372 } else
1373 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1374#else
1375 if (!cpu_has_x2apic)
1376 return;
1377
1378 if (x2apic_preenabled)
1379 panic("x2apic enabled prior OS handover,"
1380 " enable CONFIG_INTR_REMAP");
1381
1382 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1383 " and x2apic\n");
1384#endif
1385
1386 return;
1387}
1388#endif /* CONFIG_X86_X2APIC */
1389
1390#ifdef CONFIG_X86_64
1391/*
1392 * Detect and enable local APICs on non-SMP boards.
1393 * Original code written by Keir Fraser.
1394 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1395 * not correctly set up (usually the APIC timer won't work etc.)
1396 */
1397static int __init detect_init_APIC(void)
1398{
1399 if (!cpu_has_apic) {
1400 pr_info("No local APIC present\n");
1401 return -1;
1402 }
1403
1404 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1405 boot_cpu_physical_apicid = 0;
1406 return 0;
1407}
1408#else
1409/*
1410 * Detect and initialize APIC
1411 */
1412static int __init detect_init_APIC(void)
1413{
1414 u32 h, l, features;
1415
1416 /* Disabled by kernel option? */
1417 if (disable_apic)
1418 return -1;
1419
1420 switch (boot_cpu_data.x86_vendor) {
1421 case X86_VENDOR_AMD:
1422 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1423 (boot_cpu_data.x86 >= 15))
1424 break;
1425 goto no_apic;
1426 case X86_VENDOR_INTEL:
1427 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1428 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1429 break;
1430 goto no_apic;
1431 default:
1432 goto no_apic;
1433 }
1434
1435 if (!cpu_has_apic) {
1436 /*
1437 * Over-ride BIOS and try to enable the local APIC only if
1438 * "lapic" specified.
1439 */
1440 if (!force_enable_local_apic) {
1441 pr_info("Local APIC disabled by BIOS -- "
1442 "you can enable it with \"lapic\"\n");
1443 return -1;
1444 }
1445 /*
1446 * Some BIOSes disable the local APIC in the APIC_BASE
1447 * MSR. This can only be done in software for Intel P6 or later
1448 * and AMD K7 (Model > 1) or later.
1449 */
1450 rdmsr(MSR_IA32_APICBASE, l, h);
1451 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1452 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1453 l &= ~MSR_IA32_APICBASE_BASE;
1454 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1455 wrmsr(MSR_IA32_APICBASE, l, h);
1456 enabled_via_apicbase = 1;
1457 }
1458 }
1459 /*
1460 * The APIC feature bit should now be enabled
1461 * in `cpuid'
1462 */
1463 features = cpuid_edx(1);
1464 if (!(features & (1 << X86_FEATURE_APIC))) {
1465 pr_warning("Could not enable APIC!\n");
1466 return -1;
1467 }
1468 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1469 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1470
1471 /* The BIOS may have set up the APIC at some other address */
1472 rdmsr(MSR_IA32_APICBASE, l, h);
1473 if (l & MSR_IA32_APICBASE_ENABLE)
1474 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1475
1476 pr_info("Found and enabled local APIC!\n");
1477
1478 apic_pm_activate();
1479
1480 return 0;
1481
1482no_apic:
1483 pr_info("No local APIC present or hardware disabled\n");
1484 return -1;
1485}
1486#endif
1487
1488#ifdef CONFIG_X86_64
1489void __init early_init_lapic_mapping(void)
1490{
1491 unsigned long phys_addr;
1492
1493 /*
1494 * If no local APIC can be found then go out
1495 * : it means there is no mpatable and MADT
1496 */
1497 if (!smp_found_config)
1498 return;
1499
1500 phys_addr = mp_lapic_addr;
1501
1502 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1503 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1504 APIC_BASE, phys_addr);
1505
1506 /*
1507 * Fetch the APIC ID of the BSP in case we have a
1508 * default configuration (or the MP table is broken).
1509 */
1510 boot_cpu_physical_apicid = read_apic_id();
1511}
1512#endif
1513
1514/**
1515 * init_apic_mappings - initialize APIC mappings
1516 */
1517void __init init_apic_mappings(void)
1518{
1519#ifdef CONFIG_X86_X2APIC
1520 if (x2apic) {
1521 boot_cpu_physical_apicid = read_apic_id();
1522 return;
1523 }
1524#endif
1525
1526 /*
1527 * If no local APIC can be found then set up a fake all
1528 * zeroes page to simulate the local APIC and another
1529 * one for the IO-APIC.
1530 */
1531 if (!smp_found_config && detect_init_APIC()) {
1532 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1533 apic_phys = __pa(apic_phys);
1534 } else
1535 apic_phys = mp_lapic_addr;
1536
1537 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1538 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
1539 APIC_BASE, apic_phys);
1540
1541 /*
1542 * Fetch the APIC ID of the BSP in case we have a
1543 * default configuration (or the MP table is broken).
1544 */
1545 if (boot_cpu_physical_apicid == -1U)
1546 boot_cpu_physical_apicid = read_apic_id();
1547}
1548
1549/*
1550 * This initializes the IO-APIC and APIC hardware if this is
1551 * a UP kernel.
1552 */
1553int apic_version[MAX_APICS];
1554
1555int __init APIC_init_uniprocessor(void)
1556{
1557 if (disable_apic) {
1558 pr_info("Apic disabled\n");
1559 return -1;
1560 }
1561#ifdef CONFIG_X86_64
1562 if (!cpu_has_apic) {
1563 disable_apic = 1;
1564 pr_info("Apic disabled by BIOS\n");
1565 return -1;
1566 }
1567#else
1568 if (!smp_found_config && !cpu_has_apic)
1569 return -1;
1570
1571 /*
1572 * Complain if the BIOS pretends there is one.
1573 */
1574 if (!cpu_has_apic &&
1575 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1576 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1577 boot_cpu_physical_apicid);
1578 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1579 return -1;
1580 }
1581#endif
1582
1583 enable_IR_x2apic();
1584#ifdef CONFIG_X86_64
1585 default_setup_apic_routing();
1586#endif
1587
1588 verify_local_APIC();
1589 connect_bsp_APIC();
1590
1591#ifdef CONFIG_X86_64
1592 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1593#else
1594 /*
1595 * Hack: In case of kdump, after a crash, kernel might be booting
1596 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1597 * might be zero if read from MP tables. Get it from LAPIC.
1598 */
1599# ifdef CONFIG_CRASH_DUMP
1600 boot_cpu_physical_apicid = read_apic_id();
1601# endif
1602#endif
1603 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1604 setup_local_APIC();
1605
1606#ifdef CONFIG_X86_IO_APIC
1607 /*
1608 * Now enable IO-APICs, actually call clear_IO_APIC
1609 * We need clear_IO_APIC before enabling error vector
1610 */
1611 if (!skip_ioapic_setup && nr_ioapics)
1612 enable_IO_APIC();
1613#endif
1614
1615 end_local_APIC_setup();
1616
1617#ifdef CONFIG_X86_IO_APIC
1618 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1619 setup_IO_APIC();
1620 else {
1621 nr_ioapics = 0;
1622 localise_nmi_watchdog();
1623 }
1624#else
1625 localise_nmi_watchdog();
1626#endif
1627
1628 setup_boot_clock();
1629#ifdef CONFIG_X86_64
1630 check_nmi_watchdog();
1631#endif
1632
1633 return 0;
1634}
1635
1636/*
1637 * Local APIC interrupts
1638 */
1639
1640/*
1641 * This interrupt should _never_ happen with our APIC/SMP architecture
1642 */
1643void smp_spurious_interrupt(struct pt_regs *regs)
1644{
1645 u32 v;
1646
1647 exit_idle();
1648 irq_enter();
1649 /*
1650 * Check if this really is a spurious interrupt and ACK it
1651 * if it is a vectored one. Just in case...
1652 * Spurious interrupts should not be ACKed.
1653 */
1654 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1655 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1656 ack_APIC_irq();
1657
1658 inc_irq_stat(irq_spurious_count);
1659
1660 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1661 pr_info("spurious APIC interrupt on CPU#%d, "
1662 "should never happen.\n", smp_processor_id());
1663 irq_exit();
1664}
1665
1666/*
1667 * This interrupt should never happen with our APIC/SMP architecture
1668 */
1669void smp_error_interrupt(struct pt_regs *regs)
1670{
1671 u32 v, v1;
1672
1673 exit_idle();
1674 irq_enter();
1675 /* First tickle the hardware, only then report what went on. -- REW */
1676 v = apic_read(APIC_ESR);
1677 apic_write(APIC_ESR, 0);
1678 v1 = apic_read(APIC_ESR);
1679 ack_APIC_irq();
1680 atomic_inc(&irq_err_count);
1681
1682 /*
1683 * Here is what the APIC error bits mean:
1684 * 0: Send CS error
1685 * 1: Receive CS error
1686 * 2: Send accept error
1687 * 3: Receive accept error
1688 * 4: Reserved
1689 * 5: Send illegal vector
1690 * 6: Received illegal vector
1691 * 7: Illegal register address
1692 */
1693 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1694 smp_processor_id(), v , v1);
1695 irq_exit();
1696}
1697
1698/**
1699 * connect_bsp_APIC - attach the APIC to the interrupt system
1700 */
1701void __init connect_bsp_APIC(void)
1702{
1703#ifdef CONFIG_X86_32
1704 if (pic_mode) {
1705 /*
1706 * Do not trust the local APIC being empty at bootup.
1707 */
1708 clear_local_APIC();
1709 /*
1710 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1711 * local APIC to INT and NMI lines.
1712 */
1713 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1714 "enabling APIC mode.\n");
1715 outb(0x70, 0x22);
1716 outb(0x01, 0x23);
1717 }
1718#endif
1719 if (apic->enable_apic_mode)
1720 apic->enable_apic_mode();
1721}
1722
1723/**
1724 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1725 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1726 *
1727 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1728 * APIC is disabled.
1729 */
1730void disconnect_bsp_APIC(int virt_wire_setup)
1731{
1732 unsigned int value;
1733
1734#ifdef CONFIG_X86_32
1735 if (pic_mode) {
1736 /*
1737 * Put the board back into PIC mode (has an effect only on
1738 * certain older boards). Note that APIC interrupts, including
1739 * IPIs, won't work beyond this point! The only exception are
1740 * INIT IPIs.
1741 */
1742 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1743 "entering PIC mode.\n");
1744 outb(0x70, 0x22);
1745 outb(0x00, 0x23);
1746 return;
1747 }
1748#endif
1749
1750 /* Go back to Virtual Wire compatibility mode */
1751
1752 /* For the spurious interrupt use vector F, and enable it */
1753 value = apic_read(APIC_SPIV);
1754 value &= ~APIC_VECTOR_MASK;
1755 value |= APIC_SPIV_APIC_ENABLED;
1756 value |= 0xf;
1757 apic_write(APIC_SPIV, value);
1758
1759 if (!virt_wire_setup) {
1760 /*
1761 * For LVT0 make it edge triggered, active high,
1762 * external and enabled
1763 */
1764 value = apic_read(APIC_LVT0);
1765 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1766 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1767 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1768 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1769 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1770 apic_write(APIC_LVT0, value);
1771 } else {
1772 /* Disable LVT0 */
1773 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1774 }
1775
1776 /*
1777 * For LVT1 make it edge triggered, active high,
1778 * nmi and enabled
1779 */
1780 value = apic_read(APIC_LVT1);
1781 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1782 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1783 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1784 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1785 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1786 apic_write(APIC_LVT1, value);
1787}
1788
1789void __cpuinit generic_processor_info(int apicid, int version)
1790{
1791 int cpu;
1792
1793 /*
1794 * Validate version
1795 */
1796 if (version == 0x0) {
1797 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1798 "fixing up to 0x10. (tell your hw vendor)\n",
1799 version);
1800 version = 0x10;
1801 }
1802 apic_version[apicid] = version;
1803
1804 if (num_processors >= nr_cpu_ids) {
1805 int max = nr_cpu_ids;
1806 int thiscpu = max + disabled_cpus;
1807
1808 pr_warning(
1809 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1810 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1811
1812 disabled_cpus++;
1813 return;
1814 }
1815
1816 num_processors++;
1817 cpu = cpumask_next_zero(-1, cpu_present_mask);
1818
1819 if (version != apic_version[boot_cpu_physical_apicid])
1820 WARN_ONCE(1,
1821 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1822 apic_version[boot_cpu_physical_apicid], cpu, version);
1823
1824 physid_set(apicid, phys_cpu_present_map);
1825 if (apicid == boot_cpu_physical_apicid) {
1826 /*
1827 * x86_bios_cpu_apicid is required to have processors listed
1828 * in same order as logical cpu numbers. Hence the first
1829 * entry is BSP, and so on.
1830 */
1831 cpu = 0;
1832 }
1833 if (apicid > max_physical_apicid)
1834 max_physical_apicid = apicid;
1835
1836#ifdef CONFIG_X86_32
1837 /*
1838 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1839 * but we need to work other dependencies like SMP_SUSPEND etc
1840 * before this can be done without some confusion.
1841 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1842 * - Ashok Raj <ashok.raj@intel.com>
1843 */
1844 if (max_physical_apicid >= 8) {
1845 switch (boot_cpu_data.x86_vendor) {
1846 case X86_VENDOR_INTEL:
1847 if (!APIC_XAPIC(version)) {
1848 def_to_bigsmp = 0;
1849 break;
1850 }
1851 /* If P4 and above fall through */
1852 case X86_VENDOR_AMD:
1853 def_to_bigsmp = 1;
1854 }
1855 }
1856#endif
1857
1858#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1859 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1860 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1861#endif
1862
1863 set_cpu_possible(cpu, true);
1864 set_cpu_present(cpu, true);
1865}
1866
1867int hard_smp_processor_id(void)
1868{
1869 return read_apic_id();
1870}
1871
1872void default_init_apic_ldr(void)
1873{
1874 unsigned long val;
1875
1876 apic_write(APIC_DFR, APIC_DFR_VALUE);
1877 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
1878 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1879 apic_write(APIC_LDR, val);
1880}
1881
1882#ifdef CONFIG_X86_32
1883int default_apicid_to_node(int logical_apicid)
1884{
1885#ifdef CONFIG_SMP
1886 return apicid_2_node[hard_smp_processor_id()];
1887#else
1888 return 0;
1889#endif
1890}
1891#endif
1892
1893/*
1894 * Power management
1895 */
1896#ifdef CONFIG_PM
1897
1898static struct {
1899 /*
1900 * 'active' is true if the local APIC was enabled by us and
1901 * not the BIOS; this signifies that we are also responsible
1902 * for disabling it before entering apm/acpi suspend
1903 */
1904 int active;
1905 /* r/w apic fields */
1906 unsigned int apic_id;
1907 unsigned int apic_taskpri;
1908 unsigned int apic_ldr;
1909 unsigned int apic_dfr;
1910 unsigned int apic_spiv;
1911 unsigned int apic_lvtt;
1912 unsigned int apic_lvtpc;
1913 unsigned int apic_lvt0;
1914 unsigned int apic_lvt1;
1915 unsigned int apic_lvterr;
1916 unsigned int apic_tmict;
1917 unsigned int apic_tdcr;
1918 unsigned int apic_thmr;
1919} apic_pm_state;
1920
1921static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1922{
1923 unsigned long flags;
1924 int maxlvt;
1925
1926 if (!apic_pm_state.active)
1927 return 0;
1928
1929 maxlvt = lapic_get_maxlvt();
1930
1931 apic_pm_state.apic_id = apic_read(APIC_ID);
1932 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1933 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1934 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1935 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1936 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1937 if (maxlvt >= 4)
1938 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1939 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1940 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1941 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1942 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1943 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1944#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1945 if (maxlvt >= 5)
1946 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1947#endif
1948
1949 local_irq_save(flags);
1950 disable_local_APIC();
1951 local_irq_restore(flags);
1952 return 0;
1953}
1954
1955static int lapic_resume(struct sys_device *dev)
1956{
1957 unsigned int l, h;
1958 unsigned long flags;
1959 int maxlvt;
1960
1961 if (!apic_pm_state.active)
1962 return 0;
1963
1964 maxlvt = lapic_get_maxlvt();
1965
1966 local_irq_save(flags);
1967
1968#ifdef CONFIG_X86_X2APIC
1969 if (x2apic)
1970 enable_x2apic();
1971 else
1972#endif
1973 {
1974 /*
1975 * Make sure the APICBASE points to the right address
1976 *
1977 * FIXME! This will be wrong if we ever support suspend on
1978 * SMP! We'll need to do this as part of the CPU restore!
1979 */
1980 rdmsr(MSR_IA32_APICBASE, l, h);
1981 l &= ~MSR_IA32_APICBASE_BASE;
1982 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1983 wrmsr(MSR_IA32_APICBASE, l, h);
1984 }
1985
1986 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1987 apic_write(APIC_ID, apic_pm_state.apic_id);
1988 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1989 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1990 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1991 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1992 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1993 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1994#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1995 if (maxlvt >= 5)
1996 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1997#endif
1998 if (maxlvt >= 4)
1999 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2000 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2001 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2002 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2003 apic_write(APIC_ESR, 0);
2004 apic_read(APIC_ESR);
2005 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2006 apic_write(APIC_ESR, 0);
2007 apic_read(APIC_ESR);
2008
2009 local_irq_restore(flags);
2010
2011 return 0;
2012}
2013
2014/*
2015 * This device has no shutdown method - fully functioning local APICs
2016 * are needed on every CPU up until machine_halt/restart/poweroff.
2017 */
2018
2019static struct sysdev_class lapic_sysclass = {
2020 .name = "lapic",
2021 .resume = lapic_resume,
2022 .suspend = lapic_suspend,
2023};
2024
2025static struct sys_device device_lapic = {
2026 .id = 0,
2027 .cls = &lapic_sysclass,
2028};
2029
2030static void __cpuinit apic_pm_activate(void)
2031{
2032 apic_pm_state.active = 1;
2033}
2034
2035static int __init init_lapic_sysfs(void)
2036{
2037 int error;
2038
2039 if (!cpu_has_apic)
2040 return 0;
2041 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2042
2043 error = sysdev_class_register(&lapic_sysclass);
2044 if (!error)
2045 error = sysdev_register(&device_lapic);
2046 return error;
2047}
2048device_initcall(init_lapic_sysfs);
2049
2050#else /* CONFIG_PM */
2051
2052static void apic_pm_activate(void) { }
2053
2054#endif /* CONFIG_PM */
2055
2056#ifdef CONFIG_X86_64
2057/*
2058 * apic_is_clustered_box() -- Check if we can expect good TSC
2059 *
2060 * Thus far, the major user of this is IBM's Summit2 series:
2061 *
2062 * Clustered boxes may have unsynced TSC problems if they are
2063 * multi-chassis. Use available data to take a good guess.
2064 * If in doubt, go HPET.
2065 */
2066__cpuinit int apic_is_clustered_box(void)
2067{
2068 int i, clusters, zeros;
2069 unsigned id;
2070 u16 *bios_cpu_apicid;
2071 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2072
2073 /*
2074 * there is not this kind of box with AMD CPU yet.
2075 * Some AMD box with quadcore cpu and 8 sockets apicid
2076 * will be [4, 0x23] or [8, 0x27] could be thought to
2077 * vsmp box still need checking...
2078 */
2079 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
2080 return 0;
2081
2082 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2083 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2084
2085 for (i = 0; i < nr_cpu_ids; i++) {
2086 /* are we being called early in kernel startup? */
2087 if (bios_cpu_apicid) {
2088 id = bios_cpu_apicid[i];
2089 } else if (i < nr_cpu_ids) {
2090 if (cpu_present(i))
2091 id = per_cpu(x86_bios_cpu_apicid, i);
2092 else
2093 continue;
2094 } else
2095 break;
2096
2097 if (id != BAD_APICID)
2098 __set_bit(APIC_CLUSTERID(id), clustermap);
2099 }
2100
2101 /* Problem: Partially populated chassis may not have CPUs in some of
2102 * the APIC clusters they have been allocated. Only present CPUs have
2103 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2104 * Since clusters are allocated sequentially, count zeros only if
2105 * they are bounded by ones.
2106 */
2107 clusters = 0;
2108 zeros = 0;
2109 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2110 if (test_bit(i, clustermap)) {
2111 clusters += 1 + zeros;
2112 zeros = 0;
2113 } else
2114 ++zeros;
2115 }
2116
2117 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2118 * not guaranteed to be synced between boards
2119 */
2120 if (is_vsmp_box() && clusters > 1)
2121 return 1;
2122
2123 /*
2124 * If clusters > 2, then should be multi-chassis.
2125 * May have to revisit this when multi-core + hyperthreaded CPUs come
2126 * out, but AFAIK this will work even for them.
2127 */
2128 return (clusters > 2);
2129}
2130#endif
2131
2132/*
2133 * APIC command line parameters
2134 */
2135static int __init setup_disableapic(char *arg)
2136{
2137 disable_apic = 1;
2138 setup_clear_cpu_cap(X86_FEATURE_APIC);
2139 return 0;
2140}
2141early_param("disableapic", setup_disableapic);
2142
2143/* same as disableapic, for compatibility */
2144static int __init setup_nolapic(char *arg)
2145{
2146 return setup_disableapic(arg);
2147}
2148early_param("nolapic", setup_nolapic);
2149
2150static int __init parse_lapic_timer_c2_ok(char *arg)
2151{
2152 local_apic_timer_c2_ok = 1;
2153 return 0;
2154}
2155early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2156
2157static int __init parse_disable_apic_timer(char *arg)
2158{
2159 disable_apic_timer = 1;
2160 return 0;
2161}
2162early_param("noapictimer", parse_disable_apic_timer);
2163
2164static int __init parse_nolapic_timer(char *arg)
2165{
2166 disable_apic_timer = 1;
2167 return 0;
2168}
2169early_param("nolapic_timer", parse_nolapic_timer);
2170
2171static int __init apic_set_verbosity(char *arg)
2172{
2173 if (!arg) {
2174#ifdef CONFIG_X86_64
2175 skip_ioapic_setup = 0;
2176 return 0;
2177#endif
2178 return -EINVAL;
2179 }
2180
2181 if (strcmp("debug", arg) == 0)
2182 apic_verbosity = APIC_DEBUG;
2183 else if (strcmp("verbose", arg) == 0)
2184 apic_verbosity = APIC_VERBOSE;
2185 else {
2186 pr_warning("APIC Verbosity level %s not recognised"
2187 " use apic=verbose or apic=debug\n", arg);
2188 return -EINVAL;
2189 }
2190
2191 return 0;
2192}
2193early_param("apic", apic_set_verbosity);
2194
2195static int __init lapic_insert_resource(void)
2196{
2197 if (!apic_phys)
2198 return -1;
2199
2200 /* Put local APIC into the resource map. */
2201 lapic_resource.start = apic_phys;
2202 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2203 insert_resource(&iomem_resource, &lapic_resource);
2204
2205 return 0;
2206}
2207
2208/*
2209 * need call insert after e820_reserve_resources()
2210 * that is using request_resource
2211 */
2212late_initcall(lapic_insert_resource);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 15:39:13 -0500