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authorJoerg Roedel <joerg.roedel@amd.com>2011-04-07 02:16:10 -0400
committerJoerg Roedel <joerg.roedel@amd.com>2011-04-07 05:04:32 -0400
commit7d0c5cc5be73f7ce26fdcca7b8ec2203f661eb93 (patch)
treefbe4ff16580783316f3b2435130865f45387a4c3 /arch/x86/kernel/amd_iommu_init.c
parentd8c13085775c72e2d46edc54ed0c803c3a944ddb (diff)
x86/amd-iommu: Flush all internal TLBs when IOMMUs are enabled
The old code only flushed a DTE or a domain TLB before it is actually used by the IOMMU driver. While this is efficient and works when done right it is more likely to introduce new bugs when changing code (which happened in the past). This patch adds code to flush all DTEs and all domain TLBs in each IOMMU right after it is enabled (at boot and after resume). This reduces the complexity of the driver and makes it less likely to introduce stale-TLB bugs in the future. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'arch/x86/kernel/amd_iommu_init.c')
-rw-r--r--arch/x86/kernel/amd_iommu_init.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/x86/kernel/amd_iommu_init.c b/arch/x86/kernel/amd_iommu_init.c
index 246d727b65b7..8848dda808e2 100644
--- a/arch/x86/kernel/amd_iommu_init.c
+++ b/arch/x86/kernel/amd_iommu_init.c
@@ -180,6 +180,12 @@ static u32 dev_table_size; /* size of the device table */
180static u32 alias_table_size; /* size of the alias table */ 180static u32 alias_table_size; /* size of the alias table */
181static u32 rlookup_table_size; /* size if the rlookup table */ 181static u32 rlookup_table_size; /* size if the rlookup table */
182 182
183/*
184 * This function flushes all internal caches of
185 * the IOMMU used by this driver.
186 */
187extern void iommu_flush_all_caches(struct amd_iommu *iommu);
188
183static inline void update_last_devid(u16 devid) 189static inline void update_last_devid(u16 devid)
184{ 190{
185 if (devid > amd_iommu_last_bdf) 191 if (devid > amd_iommu_last_bdf)
@@ -1244,6 +1250,7 @@ static void enable_iommus(void)
1244 iommu_set_exclusion_range(iommu); 1250 iommu_set_exclusion_range(iommu);
1245 iommu_init_msi(iommu); 1251 iommu_init_msi(iommu);
1246 iommu_enable(iommu); 1252 iommu_enable(iommu);
1253 iommu_flush_all_caches(iommu);
1247 } 1254 }
1248} 1255}
1249 1256
@@ -1274,8 +1281,8 @@ static void amd_iommu_resume(void)
1274 * we have to flush after the IOMMUs are enabled because a 1281 * we have to flush after the IOMMUs are enabled because a
1275 * disabled IOMMU will never execute the commands we send 1282 * disabled IOMMU will never execute the commands we send
1276 */ 1283 */
1277 amd_iommu_flush_all_devices(); 1284 for_each_iommu(iommu)
1278 amd_iommu_flush_all_domains(); 1285 iommu_flush_all_caches(iommu);
1279} 1286}
1280 1287
1281static int amd_iommu_suspend(void) 1288static int amd_iommu_suspend(void)