diff options
| author | Pallipadi, Venkatesh <venkatesh.pallipadi@intel.com> | 2009-02-06 19:52:05 -0500 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-02-09 05:15:15 -0500 |
| commit | e736ad548db152776de61d7a26805cfae77ce5ce (patch) | |
| tree | bab2cb6560f2e038ccebf891cd847f37fd61a1b8 /arch/x86/include | |
| parent | 0cd5c3c80a0ebd68c08312fa7d8c13149cc61c4c (diff) | |
x86: add clflush before monitor for Intel 7400 series
For Intel 7400 series CPUs, the recommendation is to use a clflush on the
monitored address just before monitor and mwait pair [1].
This clflush makes sure that there are no false wakeups from mwait when the
monitored address was recently written to.
[1] "MONITOR/MWAIT Recommendations for Intel Xeon Processor 7400 series"
section in specification update document of 7400 series
http://download.intel.com/design/xeon/specupdt/32033601.pdf
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/asm/cpufeature.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index ea408dcba513..7301e60dc4a8 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h | |||
| @@ -93,6 +93,7 @@ | |||
| 93 | #define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */ | 93 | #define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */ |
| 94 | #define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */ | 94 | #define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */ |
| 95 | #define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */ | 95 | #define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */ |
| 96 | #define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */ | ||
| 96 | 97 | ||
| 97 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | 98 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
| 98 | #define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ | 99 | #define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ |