Merge branch 'x86/asm' into tracing/syscalls

We need the wider TIF work-mask checks in entry_32.S.

Signed-off-by: Ingo Molnar <mingo@elte.hu>

6 files changed, 208 insertions, 19 deletions

diff --git a/arch/x86/include/asm/boot.h b/arch/x86/include/asm/boot.h
index 6526cf08b0e4..6ba23dd9fc92 100644
--- a/arch/x86/include/asm/boot.h
+++ b/arch/x86/include/asm/boot.h
@@ -1,10 +1,6 @@
 #ifndef _ASM_X86_BOOT_H
 #define _ASM_X86_BOOT_H
 
-/* Don't touch these, unless you really know what you're doing. */
-#define DEF_SYSSEG      0x1000
-#define DEF_SYSSIZE     0x7F00
-
 /* Internal svga startup constants */
 #define NORMAL_VGA      0xffff          /* 80x25 mode */
 #define EXTENDED_VGA    0xfffe          /* 80x50 mode */
diff --git a/arch/x86/include/asm/cpu_debug.h b/arch/x86/include/asm/cpu_debug.h
new file mode 100755
index 000000000000..d24d64fcee04
--- /dev/null
+++ b/arch/x86/include/asm/cpu_debug.h
@@ -0,0 +1,193 @@
+#ifndef _ASM_X86_CPU_DEBUG_H
+#define _ASM_X86_CPU_DEBUG_H
+
+/*
+ * CPU x86 architecture debug
+ *
+ * Copyright(C) 2009 Jaswinder Singh Rajput
+ */
+
+/* Register flags */
+enum cpu_debug_bit {
+/* Model Specific Registers (MSRs)                                      */
+        CPU_MC_BIT,                             /* Machine Check        */
+        CPU_MONITOR_BIT,                        /* Monitor              */
+        CPU_TIME_BIT,                           /* Time                 */
+        CPU_PMC_BIT,                            /* Performance Monitor  */
+        CPU_PLATFORM_BIT,                       /* Platform             */
+        CPU_APIC_BIT,                           /* APIC                 */
+        CPU_POWERON_BIT,                        /* Power-on             */
+        CPU_CONTROL_BIT,                        /* Control              */
+        CPU_FEATURES_BIT,                       /* Features control     */
+        CPU_LBRANCH_BIT,                        /* Last Branch          */
+        CPU_BIOS_BIT,                           /* BIOS                 */
+        CPU_FREQ_BIT,                           /* Frequency            */
+        CPU_MTTR_BIT,                           /* MTRR                 */
+        CPU_PERF_BIT,                           /* Performance          */
+        CPU_CACHE_BIT,                          /* Cache                */
+        CPU_SYSENTER_BIT,                       /* Sysenter             */
+        CPU_THERM_BIT,                          /* Thermal              */
+        CPU_MISC_BIT,                           /* Miscellaneous        */
+        CPU_DEBUG_BIT,                          /* Debug                */
+        CPU_PAT_BIT,                            /* PAT                  */
+        CPU_VMX_BIT,                            /* VMX                  */
+        CPU_CALL_BIT,                           /* System Call          */
+        CPU_BASE_BIT,                           /* BASE Address         */
+        CPU_SMM_BIT,                            /* System mgmt mode     */
+        CPU_SVM_BIT,                            /*Secure Virtual Machine*/
+        CPU_OSVM_BIT,                           /* OS-Visible Workaround*/
+/* Standard Registers                                                   */
+        CPU_TSS_BIT,                            /* Task Stack Segment   */
+        CPU_CR_BIT,                             /* Control Registers    */
+        CPU_DT_BIT,                             /* Descriptor Table     */
+/* End of Registers flags                                               */
+        CPU_REG_ALL_BIT,                        /* Select all Registers */
+};
+
+#define CPU_REG_ALL             (~0)            /* Select all Registers */
+
+#define CPU_MC                  (1 << CPU_MC_BIT)
+#define CPU_MONITOR             (1 << CPU_MONITOR_BIT)
+#define CPU_TIME                (1 << CPU_TIME_BIT)
+#define CPU_PMC                 (1 << CPU_PMC_BIT)
+#define CPU_PLATFORM            (1 << CPU_PLATFORM_BIT)
+#define CPU_APIC                (1 << CPU_APIC_BIT)
+#define CPU_POWERON             (1 << CPU_POWERON_BIT)
+#define CPU_CONTROL             (1 << CPU_CONTROL_BIT)
+#define CPU_FEATURES            (1 << CPU_FEATURES_BIT)
+#define CPU_LBRANCH             (1 << CPU_LBRANCH_BIT)
+#define CPU_BIOS                (1 << CPU_BIOS_BIT)
+#define CPU_FREQ                (1 << CPU_FREQ_BIT)
+#define CPU_MTRR                (1 << CPU_MTTR_BIT)
+#define CPU_PERF                (1 << CPU_PERF_BIT)
+#define CPU_CACHE               (1 << CPU_CACHE_BIT)
+#define CPU_SYSENTER            (1 << CPU_SYSENTER_BIT)
+#define CPU_THERM               (1 << CPU_THERM_BIT)
+#define CPU_MISC                (1 << CPU_MISC_BIT)
+#define CPU_DEBUG               (1 << CPU_DEBUG_BIT)
+#define CPU_PAT                 (1 << CPU_PAT_BIT)
+#define CPU_VMX                 (1 << CPU_VMX_BIT)
+#define CPU_CALL                (1 << CPU_CALL_BIT)
+#define CPU_BASE                (1 << CPU_BASE_BIT)
+#define CPU_SMM                 (1 << CPU_SMM_BIT)
+#define CPU_SVM                 (1 << CPU_SVM_BIT)
+#define CPU_OSVM                (1 << CPU_OSVM_BIT)
+#define CPU_TSS                 (1 << CPU_TSS_BIT)
+#define CPU_CR                  (1 << CPU_CR_BIT)
+#define CPU_DT                  (1 << CPU_DT_BIT)
+
+/* Register file flags */
+enum cpu_file_bit {
+        CPU_INDEX_BIT,                          /* index                */
+        CPU_VALUE_BIT,                          /* value                */
+};
+
+#define CPU_FILE_VALUE                  (1 << CPU_VALUE_BIT)
+
+/*
+ * DisplayFamily_DisplayModel   Processor Families/Processor Number Series
+ * --------------------------   ------------------------------------------
+ * 05_01, 05_02, 05_04          Pentium, Pentium with MMX
+ *
+ * 06_01                        Pentium Pro
+ * 06_03, 06_05                 Pentium II Xeon, Pentium II
+ * 06_07, 06_08, 06_0A, 06_0B   Pentium III Xeon, Pentum III
+ *
+ * 06_09, 060D                  Pentium M
+ *
+ * 06_0E                        Core Duo, Core Solo
+ *
+ * 06_0F                        Xeon 3000, 3200, 5100, 5300, 7300 series,
+ *                              Core 2 Quad, Core 2 Extreme, Core 2 Duo,
+ *                              Pentium dual-core
+ * 06_17                        Xeon 5200, 5400 series, Core 2 Quad Q9650
+ *
+ * 06_1C                        Atom
+ *
+ * 0F_00, 0F_01, 0F_02          Xeon, Xeon MP, Pentium 4
+ * 0F_03, 0F_04                 Xeon, Xeon MP, Pentium 4, Pentium D
+ *
+ * 0F_06                        Xeon 7100, 5000 Series, Xeon MP,
+ *                              Pentium 4, Pentium D
+ */
+
+/* Register processors bits */
+enum cpu_processor_bit {
+        CPU_NONE,
+/* Intel */
+        CPU_INTEL_PENTIUM_BIT,
+        CPU_INTEL_P6_BIT,
+        CPU_INTEL_PENTIUM_M_BIT,
+        CPU_INTEL_CORE_BIT,
+        CPU_INTEL_CORE2_BIT,
+        CPU_INTEL_ATOM_BIT,
+        CPU_INTEL_XEON_P4_BIT,
+        CPU_INTEL_XEON_MP_BIT,
+};
+
+#define CPU_ALL                 (~0)            /* Select all CPUs      */
+
+#define CPU_INTEL_PENTIUM       (1 << CPU_INTEL_PENTIUM_BIT)
+#define CPU_INTEL_P6            (1 << CPU_INTEL_P6_BIT)
+#define CPU_INTEL_PENTIUM_M     (1 << CPU_INTEL_PENTIUM_M_BIT)
+#define CPU_INTEL_CORE          (1 << CPU_INTEL_CORE_BIT)
+#define CPU_INTEL_CORE2         (1 << CPU_INTEL_CORE2_BIT)
+#define CPU_INTEL_ATOM          (1 << CPU_INTEL_ATOM_BIT)
+#define CPU_INTEL_XEON_P4       (1 << CPU_INTEL_XEON_P4_BIT)
+#define CPU_INTEL_XEON_MP       (1 << CPU_INTEL_XEON_MP_BIT)
+
+#define CPU_INTEL_PX            (CPU_INTEL_P6 | CPU_INTEL_PENTIUM_M)
+#define CPU_INTEL_COREX         (CPU_INTEL_CORE | CPU_INTEL_CORE2)
+#define CPU_INTEL_XEON          (CPU_INTEL_XEON_P4 | CPU_INTEL_XEON_MP)
+#define CPU_CO_AT               (CPU_INTEL_CORE | CPU_INTEL_ATOM)
+#define CPU_C2_AT               (CPU_INTEL_CORE2 | CPU_INTEL_ATOM)
+#define CPU_CX_AT               (CPU_INTEL_COREX | CPU_INTEL_ATOM)
+#define CPU_CX_XE               (CPU_INTEL_COREX | CPU_INTEL_XEON)
+#define CPU_P6_XE               (CPU_INTEL_P6 | CPU_INTEL_XEON)
+#define CPU_PM_CO_AT            (CPU_INTEL_PENTIUM_M | CPU_CO_AT)
+#define CPU_C2_AT_XE            (CPU_C2_AT | CPU_INTEL_XEON)
+#define CPU_CX_AT_XE            (CPU_CX_AT | CPU_INTEL_XEON)
+#define CPU_P6_CX_AT            (CPU_INTEL_P6 | CPU_CX_AT)
+#define CPU_P6_CX_XE            (CPU_P6_XE | CPU_INTEL_COREX)
+#define CPU_P6_CX_AT_XE         (CPU_INTEL_P6 | CPU_CX_AT_XE)
+#define CPU_PM_CX_AT_XE         (CPU_INTEL_PENTIUM_M | CPU_CX_AT_XE)
+#define CPU_PM_CX_AT            (CPU_INTEL_PENTIUM_M | CPU_CX_AT)
+#define CPU_PM_CX_XE            (CPU_INTEL_PENTIUM_M | CPU_CX_XE)
+#define CPU_PX_CX_AT            (CPU_INTEL_PX | CPU_CX_AT)
+#define CPU_PX_CX_AT_XE         (CPU_INTEL_PX | CPU_CX_AT_XE)
+
+/* Select all Intel CPUs*/
+#define CPU_INTEL_ALL           (CPU_INTEL_PENTIUM | CPU_PX_CX_AT_XE)
+
+#define MAX_CPU_FILES           512
+
+struct cpu_private {
+        unsigned                cpu;
+        unsigned                type;
+        unsigned                reg;
+        unsigned                file;
+};
+
+struct cpu_debug_base {
+        char                    *name;          /* Register name        */
+        unsigned                flag;           /* Register flag        */
+};
+
+struct cpu_cpuX_base {
+        struct dentry           *dentry;        /* Register dentry      */
+        int                     init;           /* Register index file  */
+};
+
+struct cpu_file_base {
+        char                    *name;          /* Register file name   */
+        unsigned                flag;           /* Register file flag   */
+};
+
+struct cpu_debug_range {
+        unsigned                min;            /* Register range min   */
+        unsigned                max;            /* Register range max   */
+        unsigned                flag;           /* Supported flags      */
+        unsigned                model;          /* Supported models     */
+};
+
+#endif /* _ASM_X86_CPU_DEBUG_H */
diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h
index dc27705f5443..5623c50d67b2 100644
--- a/arch/x86/include/asm/desc.h
+++ b/arch/x86/include/asm/desc.h
@@ -91,7 +91,6 @@ static inline int desc_empty(const void *ptr)
 #define store_gdt(dtr) native_store_gdt(dtr)
 #define store_idt(dtr) native_store_idt(dtr)
 #define store_tr(tr) (tr = native_store_tr())
-#define store_ldt(ldt) asm("sldt %0":"=m" (ldt))
 
 #define load_TLS(t, cpu) native_load_tls(t, cpu)
 #define set_ldt native_set_ldt
@@ -112,6 +111,8 @@ static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
 }
 #endif  /* CONFIG_PARAVIRT */
 
+#define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))
+
 static inline void native_write_idt_entry(gate_desc *idt, int entry,
                                           const gate_desc *gate)
 {
diff --git a/arch/x86/include/asm/highmem.h b/arch/x86/include/asm/highmem.h
index bf9276bea660..014c2b85ae45 100644
--- a/arch/x86/include/asm/highmem.h
+++ b/arch/x86/include/asm/highmem.h
@@ -63,6 +63,7 @@ void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot);
 void *kmap_atomic(struct page *page, enum km_type type);
 void kunmap_atomic(void *kvaddr, enum km_type type);
 void *kmap_atomic_pfn(unsigned long pfn, enum km_type type);
+void *kmap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot);
 struct page *kmap_atomic_to_page(void *ptr);
 
 #ifndef CONFIG_PARAVIRT
diff --git a/arch/x86/include/asm/kexec.h b/arch/x86/include/asm/kexec.h
index 0ceb6d19ed30..317ff1703d0b 100644
--- a/arch/x86/include/asm/kexec.h
+++ b/arch/x86/include/asm/kexec.h
@@ -9,13 +9,13 @@
 # define PAGES_NR               4
 #else
 # define PA_CONTROL_PAGE        0
-# define PA_TABLE_PAGE          1
-# define PAGES_NR               2
+# define VA_CONTROL_PAGE        1
+# define PA_TABLE_PAGE          2
+# define PA_SWAP_PAGE           3
+# define PAGES_NR               4
 #endif
 
-#ifdef CONFIG_X86_32
 # define KEXEC_CONTROL_CODE_MAX_SIZE    2048
-#endif
 
 #ifndef __ASSEMBLY__
 
@@ -136,10 +136,11 @@ relocate_kernel(unsigned long indirection_page,
                 unsigned int has_pae,
                 unsigned int preserve_context);
 #else
-NORET_TYPE void
+unsigned long
 relocate_kernel(unsigned long indirection_page,
                 unsigned long page_list,
-                unsigned long start_address) ATTRIB_NORET;
+                unsigned long start_address,
+                unsigned int preserve_context);
 #endif
 
 #define ARCH_HAS_KIMAGE_ARCH
diff --git a/arch/x86/include/asm/linkage.h b/arch/x86/include/asm/linkage.h
index a0d70b46c27c..12d55e773eb6 100644
--- a/arch/x86/include/asm/linkage.h
+++ b/arch/x86/include/asm/linkage.h
@@ -1,6 +1,8 @@
 #ifndef _ASM_X86_LINKAGE_H
 #define _ASM_X86_LINKAGE_H
 
+#include <linux/stringify.h>
+
 #undef notrace
 #define notrace __attribute__((no_instrument_function))
 
@@ -53,14 +55,9 @@
         .globl name;    \
         name:
 
-#ifdef CONFIG_X86_64
-#define __ALIGN .p2align 4,,15
-#define __ALIGN_STR ".p2align 4,,15"
-#endif
-
-#ifdef CONFIG_X86_ALIGNMENT_16
-#define __ALIGN .align 16,0x90
-#define __ALIGN_STR ".align 16,0x90"
+#if defined(CONFIG_X86_64) || defined(CONFIG_X86_ALIGNMENT_16)
+#define __ALIGN         .p2align 4, 0x90
+#define __ALIGN_STR     __stringify(__ALIGN)
 #endif
 
 #endif /* __ASSEMBLY__ */