diff options
| author | Andres Freund <andres@anarazel.de> | 2014-05-08 21:29:17 -0400 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2014-05-09 11:42:47 -0400 |
| commit | c45f77364ba060395b7eff1bf45e6c537f913380 (patch) | |
| tree | 63fa772bf9f646a1c06c8ad86f4499802d1a6f38 /arch/x86/include | |
| parent | 722a0d22d028bd74061cf582de1764884e73674f (diff) | |
x86: Fix typo in MSR_IA32_MISC_ENABLE_LIMIT_CPUID macro
The spuriously added semicolon didn't have any effect because the
macro isn't currently in use.
c0a639ad0bc6b178b46996bd1f821a04643e2bde
Signed-off-by: Andres Freund <andres@anarazel.de>
Link: http://lkml.kernel.org/r/1399598957-7011-3-git-send-email-andres@anarazel.de
Cc: Borislav Petkov <bp@suse.de>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/uapi/asm/msr-index.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h index c827ace3121b..fcf2b3ae1bf0 100644 --- a/arch/x86/include/uapi/asm/msr-index.h +++ b/arch/x86/include/uapi/asm/msr-index.h | |||
| @@ -384,7 +384,7 @@ | |||
| 384 | #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 | 384 | #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 |
| 385 | #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) | 385 | #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) |
| 386 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 | 386 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 |
| 387 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT); | 387 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) |
| 388 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 | 388 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 |
| 389 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) | 389 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) |
| 390 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 | 390 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 |