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author | Ingo Molnar <mingo@elte.hu> | 2010-10-25 13:17:32 -0400 |
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committer | Ingo Molnar <mingo@elte.hu> | 2010-10-25 13:17:32 -0400 |
commit | 0b849ee88846e3488a34007c5b8b4249579ff159 (patch) | |
tree | f27ba8c014c05e343b0fd1c78fd72cd0aebafceb /arch/x86/include | |
parent | 43948f50276eca010a22726860dfe9a4e8130136 (diff) | |
parent | 4cafc4b8d7219b70e15f22e4a51b3ce847810caf (diff) |
Merge branch 'x86' of git://git.kernel.org/pub/scm/linux/kernel/git/rric/oprofile into perf/urgent
Diffstat (limited to 'arch/x86/include')
-rw-r--r-- | arch/x86/include/asm/msr-index.h | 1 | ||||
-rw-r--r-- | arch/x86/include/asm/perf_event.h | 19 |
2 files changed, 11 insertions, 9 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 986f7790fdb2..91ba8e6b630a 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h | |||
@@ -121,6 +121,7 @@ | |||
121 | #define MSR_AMD64_IBSDCLINAD 0xc0011038 | 121 | #define MSR_AMD64_IBSDCLINAD 0xc0011038 |
122 | #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 | 122 | #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 |
123 | #define MSR_AMD64_IBSCTL 0xc001103a | 123 | #define MSR_AMD64_IBSCTL 0xc001103a |
124 | #define MSR_AMD64_IBSBRTARGET 0xc001103b | ||
124 | 125 | ||
125 | /* Fam 10h MSRs */ | 126 | /* Fam 10h MSRs */ |
126 | #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 | 127 | #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 |
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 6e742cc4251b..550e26b1dbb3 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h | |||
@@ -111,17 +111,18 @@ union cpuid10_edx { | |||
111 | #define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16) | 111 | #define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16) |
112 | 112 | ||
113 | /* IbsFetchCtl bits/masks */ | 113 | /* IbsFetchCtl bits/masks */ |
114 | #define IBS_FETCH_RAND_EN (1ULL<<57) | 114 | #define IBS_FETCH_RAND_EN (1ULL<<57) |
115 | #define IBS_FETCH_VAL (1ULL<<49) | 115 | #define IBS_FETCH_VAL (1ULL<<49) |
116 | #define IBS_FETCH_ENABLE (1ULL<<48) | 116 | #define IBS_FETCH_ENABLE (1ULL<<48) |
117 | #define IBS_FETCH_CNT 0xFFFF0000ULL | 117 | #define IBS_FETCH_CNT 0xFFFF0000ULL |
118 | #define IBS_FETCH_MAX_CNT 0x0000FFFFULL | 118 | #define IBS_FETCH_MAX_CNT 0x0000FFFFULL |
119 | 119 | ||
120 | /* IbsOpCtl bits */ | 120 | /* IbsOpCtl bits */ |
121 | #define IBS_OP_CNT_CTL (1ULL<<19) | 121 | #define IBS_OP_CNT_CTL (1ULL<<19) |
122 | #define IBS_OP_VAL (1ULL<<18) | 122 | #define IBS_OP_VAL (1ULL<<18) |
123 | #define IBS_OP_ENABLE (1ULL<<17) | 123 | #define IBS_OP_ENABLE (1ULL<<17) |
124 | #define IBS_OP_MAX_CNT 0x0000FFFFULL | 124 | #define IBS_OP_MAX_CNT 0x0000FFFFULL |
125 | #define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */ | ||
125 | 126 | ||
126 | #ifdef CONFIG_PERF_EVENTS | 127 | #ifdef CONFIG_PERF_EVENTS |
127 | extern void init_hw_perf_events(void); | 128 | extern void init_hw_perf_events(void); |