Merge branch 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull perf updates from Ingo Molnar:
 "Features:

   - Add "uretprobes" - an optimization to uprobes, like kretprobes are
     an optimization to kprobes.  "perf probe -x file sym%return" now
     works like kretprobes.  By Oleg Nesterov.

   - Introduce per core aggregation in 'perf stat', from Stephane
     Eranian.

   - Add memory profiling via PEBS, from Stephane Eranian.

   - Event group view for 'annotate' in --stdio, --tui and --gtk, from
     Namhyung Kim.

   - Add support for AMD NB and L2I "uncore" counters, by Jacob Shin.

   - Add Ivy Bridge-EP uncore support, by Zheng Yan

   - IBM zEnterprise EC12 oprofile support patchlet from Robert Richter.

   - Add perf test entries for checking breakpoint overflow signal
     handler issues, from Jiri Olsa.

   - Add perf test entry for for checking number of EXIT events, from
     Namhyung Kim.

   - Add perf test entries for checking --cpu in record and stat, from
     Jiri Olsa.

   - Introduce perf stat --repeat forever, from Frederik Deweerdt.

   - Add --no-demangle to report/top, from Namhyung Kim.

   - PowerPC fixes plus a couple of cleanups/optimizations in uprobes
     and trace_uprobes, by Oleg Nesterov.

  Various fixes and refactorings:

   - Fix dependency of the python binding wrt libtraceevent, from
     Naohiro Aota.

   - Simplify some perf_evlist methods and to allow 'stat' to share code
     with 'record' and 'trace', by Arnaldo Carvalho de Melo.

   - Remove dead code in related to libtraceevent integration, from
     Namhyung Kim.

   - Revert "perf sched: Handle PERF_RECORD_EXIT events" to get 'perf
     sched lat' back working, by Arnaldo Carvalho de Melo

   - We don't use Newt anymore, just plain libslang, by Arnaldo Carvalho
     de Melo.

   - Kill a bunch of die() calls, from Namhyung Kim.

   - Fix build on non-glibc systems due to libio.h absence, from Cody P
     Schafer.

   - Remove some perf_session and tracing dead code, from David Ahern.

   - Honor parallel jobs, fix from Borislav Petkov

   - Introduce tools/lib/lk library, initially just removing duplication
     among tools/perf and tools/vm.  from Borislav Petkov

  ... and many more I missed to list, see the shortlog and git log for
  more details."

* 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (136 commits)
  perf/x86/intel/P4: Robistify P4 PMU types
  perf/x86/amd: Fix AMD NB and L2I "uncore" support
  perf/x86/amd: Remove old-style NB counter support from perf_event_amd.c
  perf/x86: Check all MSRs before passing hw check
  perf/x86/amd: Add support for AMD NB and L2I "uncore" counters
  perf/x86/intel: Add Ivy Bridge-EP uncore support
  perf/x86/intel: Fix SNB-EP CBO and PCU uncore PMU filter management
  perf/x86: Avoid kfree() in CPU_{STARTING,DYING}
  uprobes/perf: Avoid perf_trace_buf_prepare/submit if ->perf_events is empty
  uprobes/tracing: Don't pass addr=ip to perf_trace_buf_submit()
  uprobes/tracing: Change create_trace_uprobe() to support uretprobes
  uprobes/tracing: Make seq_printf() code uretprobe-friendly
  uprobes/tracing: Make register_uprobe_event() paths uretprobe-friendly
  uprobes/tracing: Make uprobe_{trace,perf}_print() uretprobe-friendly
  uprobes/tracing: Introduce is_ret_probe() and uretprobe_dispatcher()
  uprobes/tracing: Introduce uprobe_{trace,perf}_print() helpers
  uprobes/tracing: Generalize struct uprobe_trace_entry_head
  uprobes/tracing: Kill the pointless local_save_flags/preempt_count calls
  uprobes/tracing: Kill the pointless seq_print_ip_sym() call
  uprobes/tracing: Kill the pointless task_pt_regs() calls
  ...

3 files changed, 34 insertions, 31 deletions

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 93fe929d1cee..ac10df72925b 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -168,6 +168,7 @@
 #define X86_FEATURE_TOPOEXT     (6*32+22) /* topology extensions CPUID leafs */
 #define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
 #define X86_FEATURE_PERFCTR_NB  (6*32+24) /* NB performance counter extensions */
+#define X86_FEATURE_PERFCTR_L2  (6*32+28) /* L2 performance counter extensions */
 
 /*
  * Auxiliary flags: Linux defined - For features scattered in various
@@ -311,6 +312,7 @@ extern const char * const x86_power_flags[32];
 #define cpu_has_pclmulqdq       boot_cpu_has(X86_FEATURE_PCLMULQDQ)
 #define cpu_has_perfctr_core    boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
 #define cpu_has_perfctr_nb      boot_cpu_has(X86_FEATURE_PERFCTR_NB)
+#define cpu_has_perfctr_l2      boot_cpu_has(X86_FEATURE_PERFCTR_L2)
 #define cpu_has_cx8             boot_cpu_has(X86_FEATURE_CX8)
 #define cpu_has_cx16            boot_cpu_has(X86_FEATURE_CX16)
 #define cpu_has_eager_fpu       boot_cpu_has(X86_FEATURE_EAGER_FPU)
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index 4f7e67e2345e..85e13ccf15c4 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -24,45 +24,45 @@
 #define ARCH_P4_CNTRVAL_MASK    ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
 #define ARCH_P4_UNFLAGGED_BIT   ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))
 
-#define P4_ESCR_EVENT_MASK      0x7e000000U
+#define P4_ESCR_EVENT_MASK      0x7e000000ULL
 #define P4_ESCR_EVENT_SHIFT     25
-#define P4_ESCR_EVENTMASK_MASK  0x01fffe00U
+#define P4_ESCR_EVENTMASK_MASK  0x01fffe00ULL
 #define P4_ESCR_EVENTMASK_SHIFT 9
-#define P4_ESCR_TAG_MASK        0x000001e0U
+#define P4_ESCR_TAG_MASK        0x000001e0ULL
 #define P4_ESCR_TAG_SHIFT       5
-#define P4_ESCR_TAG_ENABLE      0x00000010U
-#define P4_ESCR_T0_OS           0x00000008U
-#define P4_ESCR_T0_USR          0x00000004U
-#define P4_ESCR_T1_OS           0x00000002U
-#define P4_ESCR_T1_USR          0x00000001U
+#define P4_ESCR_TAG_ENABLE      0x00000010ULL
+#define P4_ESCR_T0_OS           0x00000008ULL
+#define P4_ESCR_T0_USR          0x00000004ULL
+#define P4_ESCR_T1_OS           0x00000002ULL
+#define P4_ESCR_T1_USR          0x00000001ULL
 
 #define P4_ESCR_EVENT(v)        ((v) << P4_ESCR_EVENT_SHIFT)
 #define P4_ESCR_EMASK(v)        ((v) << P4_ESCR_EVENTMASK_SHIFT)
 #define P4_ESCR_TAG(v)          ((v) << P4_ESCR_TAG_SHIFT)
 
-#define P4_CCCR_OVF                     0x80000000U
-#define P4_CCCR_CASCADE                 0x40000000U
-#define P4_CCCR_OVF_PMI_T0              0x04000000U
-#define P4_CCCR_OVF_PMI_T1              0x08000000U
-#define P4_CCCR_FORCE_OVF               0x02000000U
-#define P4_CCCR_EDGE                    0x01000000U
-#define P4_CCCR_THRESHOLD_MASK          0x00f00000U
+#define P4_CCCR_OVF                     0x80000000ULL
+#define P4_CCCR_CASCADE                 0x40000000ULL
+#define P4_CCCR_OVF_PMI_T0              0x04000000ULL
+#define P4_CCCR_OVF_PMI_T1              0x08000000ULL
+#define P4_CCCR_FORCE_OVF               0x02000000ULL
+#define P4_CCCR_EDGE                    0x01000000ULL
+#define P4_CCCR_THRESHOLD_MASK          0x00f00000ULL
 #define P4_CCCR_THRESHOLD_SHIFT         20
-#define P4_CCCR_COMPLEMENT              0x00080000U
-#define P4_CCCR_COMPARE                 0x00040000U
-#define P4_CCCR_ESCR_SELECT_MASK        0x0000e000U
+#define P4_CCCR_COMPLEMENT              0x00080000ULL
+#define P4_CCCR_COMPARE                 0x00040000ULL
+#define P4_CCCR_ESCR_SELECT_MASK        0x0000e000ULL
 #define P4_CCCR_ESCR_SELECT_SHIFT       13
-#define P4_CCCR_ENABLE                  0x00001000U
-#define P4_CCCR_THREAD_SINGLE           0x00010000U
-#define P4_CCCR_THREAD_BOTH             0x00020000U
-#define P4_CCCR_THREAD_ANY              0x00030000U
-#define P4_CCCR_RESERVED                0x00000fffU
+#define P4_CCCR_ENABLE                  0x00001000ULL
+#define P4_CCCR_THREAD_SINGLE           0x00010000ULL
+#define P4_CCCR_THREAD_BOTH             0x00020000ULL
+#define P4_CCCR_THREAD_ANY              0x00030000ULL
+#define P4_CCCR_RESERVED                0x00000fffULL
 
 #define P4_CCCR_THRESHOLD(v)            ((v) << P4_CCCR_THRESHOLD_SHIFT)
 #define P4_CCCR_ESEL(v)                 ((v) << P4_CCCR_ESCR_SELECT_SHIFT)
 
 #define P4_GEN_ESCR_EMASK(class, name, bit)     \
-        class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT)
+        class##__##name = ((1ULL << bit) << P4_ESCR_EVENTMASK_SHIFT)
 #define P4_ESCR_EMASK_BIT(class, name)          class##__##name
 
 /*
@@ -107,7 +107,7 @@
  * P4_PEBS_CONFIG_MASK and related bits on
  * modification.)
  */
-#define P4_CONFIG_ALIASABLE             (1 << 9)
+#define P4_CONFIG_ALIASABLE             (1ULL << 9)
 
 /*
  * The bits we allow to pass for RAW events
@@ -784,17 +784,17 @@ enum P4_ESCR_EMASKS {
  * Note we have UOP and PEBS bits reserved for now
  * just in case if we will need them once
  */
-#define P4_PEBS_CONFIG_ENABLE           (1 << 7)
-#define P4_PEBS_CONFIG_UOP_TAG          (1 << 8)
-#define P4_PEBS_CONFIG_METRIC_MASK      0x3f
-#define P4_PEBS_CONFIG_MASK             0xff
+#define P4_PEBS_CONFIG_ENABLE           (1ULL << 7)
+#define P4_PEBS_CONFIG_UOP_TAG          (1ULL << 8)
+#define P4_PEBS_CONFIG_METRIC_MASK      0x3FLL
+#define P4_PEBS_CONFIG_MASK             0xFFLL
 
 /*
  * mem: Only counters MSR_IQ_COUNTER4 (16) and
  * MSR_IQ_COUNTER5 (17) are allowed for PEBS sampling
  */
-#define P4_PEBS_ENABLE                  0x02000000U
-#define P4_PEBS_ENABLE_UOP_TAG          0x01000000U
+#define P4_PEBS_ENABLE                  0x02000000ULL
+#define P4_PEBS_ENABLE_UOP_TAG          0x01000000ULL
 
 #define p4_config_unpack_metric(v)      (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK)
 #define p4_config_unpack_pebs(v)        (((u64)(v)) & P4_PEBS_CONFIG_MASK)
diff --git a/arch/x86/include/asm/uprobes.h b/arch/x86/include/asm/uprobes.h
index 8ff8be7835ab..6e5197910fd8 100644
--- a/arch/x86/include/asm/uprobes.h
+++ b/arch/x86/include/asm/uprobes.h
@@ -55,4 +55,5 @@ extern int  arch_uprobe_post_xol(struct arch_uprobe *aup, struct pt_regs *regs);
 extern bool arch_uprobe_xol_was_trapped(struct task_struct *tsk);
 extern int  arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data);
 extern void arch_uprobe_abort_xol(struct arch_uprobe *aup, struct pt_regs *regs);
+extern unsigned long arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs);
 #endif  /* _ASM_UPROBES_H */