diff options
author | Al Viro <viro@zeniv.linux.org.uk> | 2008-08-17 21:05:42 -0400 |
---|---|---|
committer | H. Peter Anvin <hpa@zytor.com> | 2008-10-23 01:55:20 -0400 |
commit | bb8985586b7a906e116db835c64773b7a7d51663 (patch) | |
tree | de93ae58e88cc563d95cc124a73f3930594c6100 /arch/x86/include/asm/voyager.h | |
parent | 8ede0bdb63305d3353efd97e9af6210afb05734e (diff) |
x86, um: ... and asm-x86 move
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/include/asm/voyager.h')
-rw-r--r-- | arch/x86/include/asm/voyager.h | 528 |
1 files changed, 528 insertions, 0 deletions
diff --git a/arch/x86/include/asm/voyager.h b/arch/x86/include/asm/voyager.h new file mode 100644 index 000000000000..9c811d2e6f91 --- /dev/null +++ b/arch/x86/include/asm/voyager.h | |||
@@ -0,0 +1,528 @@ | |||
1 | /* Copyright (C) 1999,2001 | ||
2 | * | ||
3 | * Author: J.E.J.Bottomley@HansenPartnership.com | ||
4 | * | ||
5 | * Standard include definitions for the NCR Voyager system */ | ||
6 | |||
7 | #undef VOYAGER_DEBUG | ||
8 | #undef VOYAGER_CAT_DEBUG | ||
9 | |||
10 | #ifdef VOYAGER_DEBUG | ||
11 | #define VDEBUG(x) printk x | ||
12 | #else | ||
13 | #define VDEBUG(x) | ||
14 | #endif | ||
15 | |||
16 | /* There are three levels of voyager machine: 3,4 and 5. The rule is | ||
17 | * if it's less than 3435 it's a Level 3 except for a 3360 which is | ||
18 | * a level 4. A 3435 or above is a Level 5 */ | ||
19 | #define VOYAGER_LEVEL5_AND_ABOVE 0x3435 | ||
20 | #define VOYAGER_LEVEL4 0x3360 | ||
21 | |||
22 | /* The L4 DINO ASIC */ | ||
23 | #define VOYAGER_DINO 0x43 | ||
24 | |||
25 | /* voyager ports in standard I/O space */ | ||
26 | #define VOYAGER_MC_SETUP 0x96 | ||
27 | |||
28 | |||
29 | #define VOYAGER_CAT_CONFIG_PORT 0x97 | ||
30 | # define VOYAGER_CAT_DESELECT 0xff | ||
31 | #define VOYAGER_SSPB_RELOCATION_PORT 0x98 | ||
32 | |||
33 | /* Valid CAT controller commands */ | ||
34 | /* start instruction register cycle */ | ||
35 | #define VOYAGER_CAT_IRCYC 0x01 | ||
36 | /* start data register cycle */ | ||
37 | #define VOYAGER_CAT_DRCYC 0x02 | ||
38 | /* move to execute state */ | ||
39 | #define VOYAGER_CAT_RUN 0x0F | ||
40 | /* end operation */ | ||
41 | #define VOYAGER_CAT_END 0x80 | ||
42 | /* hold in idle state */ | ||
43 | #define VOYAGER_CAT_HOLD 0x90 | ||
44 | /* single step an "intest" vector */ | ||
45 | #define VOYAGER_CAT_STEP 0xE0 | ||
46 | /* return cat controller to CLEMSON mode */ | ||
47 | #define VOYAGER_CAT_CLEMSON 0xFF | ||
48 | |||
49 | /* the default cat command header */ | ||
50 | #define VOYAGER_CAT_HEADER 0x7F | ||
51 | |||
52 | /* the range of possible CAT module ids in the system */ | ||
53 | #define VOYAGER_MIN_MODULE 0x10 | ||
54 | #define VOYAGER_MAX_MODULE 0x1f | ||
55 | |||
56 | /* The voyager registers per asic */ | ||
57 | #define VOYAGER_ASIC_ID_REG 0x00 | ||
58 | #define VOYAGER_ASIC_TYPE_REG 0x01 | ||
59 | /* the sub address registers can be made auto incrementing on reads */ | ||
60 | #define VOYAGER_AUTO_INC_REG 0x02 | ||
61 | # define VOYAGER_AUTO_INC 0x04 | ||
62 | # define VOYAGER_NO_AUTO_INC 0xfb | ||
63 | #define VOYAGER_SUBADDRDATA 0x03 | ||
64 | #define VOYAGER_SCANPATH 0x05 | ||
65 | # define VOYAGER_CONNECT_ASIC 0x01 | ||
66 | # define VOYAGER_DISCONNECT_ASIC 0xfe | ||
67 | #define VOYAGER_SUBADDRLO 0x06 | ||
68 | #define VOYAGER_SUBADDRHI 0x07 | ||
69 | #define VOYAGER_SUBMODSELECT 0x08 | ||
70 | #define VOYAGER_SUBMODPRESENT 0x09 | ||
71 | |||
72 | #define VOYAGER_SUBADDR_LO 0xff | ||
73 | #define VOYAGER_SUBADDR_HI 0xffff | ||
74 | |||
75 | /* the maximum size of a scan path -- used to form instructions */ | ||
76 | #define VOYAGER_MAX_SCAN_PATH 0x100 | ||
77 | /* the biggest possible register size (in bytes) */ | ||
78 | #define VOYAGER_MAX_REG_SIZE 4 | ||
79 | |||
80 | /* Total number of possible modules (including submodules) */ | ||
81 | #define VOYAGER_MAX_MODULES 16 | ||
82 | /* Largest number of asics per module */ | ||
83 | #define VOYAGER_MAX_ASICS_PER_MODULE 7 | ||
84 | |||
85 | /* the CAT asic of each module is always the first one */ | ||
86 | #define VOYAGER_CAT_ID 0 | ||
87 | #define VOYAGER_PSI 0x1a | ||
88 | |||
89 | /* voyager instruction operations and registers */ | ||
90 | #define VOYAGER_READ_CONFIG 0x1 | ||
91 | #define VOYAGER_WRITE_CONFIG 0x2 | ||
92 | #define VOYAGER_BYPASS 0xff | ||
93 | |||
94 | typedef struct voyager_asic { | ||
95 | __u8 asic_addr; /* ASIC address; Level 4 */ | ||
96 | __u8 asic_type; /* ASIC type */ | ||
97 | __u8 asic_id; /* ASIC id */ | ||
98 | __u8 jtag_id[4]; /* JTAG id */ | ||
99 | __u8 asic_location; /* Location within scan path; start w/ 0 */ | ||
100 | __u8 bit_location; /* Location within bit stream; start w/ 0 */ | ||
101 | __u8 ireg_length; /* Instruction register length */ | ||
102 | __u16 subaddr; /* Amount of sub address space */ | ||
103 | struct voyager_asic *next; /* Next asic in linked list */ | ||
104 | } voyager_asic_t; | ||
105 | |||
106 | typedef struct voyager_module { | ||
107 | __u8 module_addr; /* Module address */ | ||
108 | __u8 scan_path_connected; /* Scan path connected */ | ||
109 | __u16 ee_size; /* Size of the EEPROM */ | ||
110 | __u16 num_asics; /* Number of Asics */ | ||
111 | __u16 inst_bits; /* Instruction bits in the scan path */ | ||
112 | __u16 largest_reg; /* Largest register in the scan path */ | ||
113 | __u16 smallest_reg; /* Smallest register in the scan path */ | ||
114 | voyager_asic_t *asic; /* First ASIC in scan path (CAT_I) */ | ||
115 | struct voyager_module *submodule; /* Submodule pointer */ | ||
116 | struct voyager_module *next; /* Next module in linked list */ | ||
117 | } voyager_module_t; | ||
118 | |||
119 | typedef struct voyager_eeprom_hdr { | ||
120 | __u8 module_id[4]; | ||
121 | __u8 version_id; | ||
122 | __u8 config_id; | ||
123 | __u16 boundry_id; /* boundary scan id */ | ||
124 | __u16 ee_size; /* size of EEPROM */ | ||
125 | __u8 assembly[11]; /* assembly # */ | ||
126 | __u8 assembly_rev; /* assembly rev */ | ||
127 | __u8 tracer[4]; /* tracer number */ | ||
128 | __u16 assembly_cksum; /* asm checksum */ | ||
129 | __u16 power_consump; /* pwr requirements */ | ||
130 | __u16 num_asics; /* number of asics */ | ||
131 | __u16 bist_time; /* min. bist time */ | ||
132 | __u16 err_log_offset; /* error log offset */ | ||
133 | __u16 scan_path_offset;/* scan path offset */ | ||
134 | __u16 cct_offset; | ||
135 | __u16 log_length; /* length of err log */ | ||
136 | __u16 xsum_end; /* offset to end of | ||
137 | checksum */ | ||
138 | __u8 reserved[4]; | ||
139 | __u8 sflag; /* starting sentinal */ | ||
140 | __u8 part_number[13]; /* prom part number */ | ||
141 | __u8 version[10]; /* version number */ | ||
142 | __u8 signature[8]; | ||
143 | __u16 eeprom_chksum; | ||
144 | __u32 data_stamp_offset; | ||
145 | __u8 eflag ; /* ending sentinal */ | ||
146 | } __attribute__((packed)) voyager_eprom_hdr_t; | ||
147 | |||
148 | |||
149 | |||
150 | #define VOYAGER_EPROM_SIZE_OFFSET \ | ||
151 | ((__u16)(&(((voyager_eprom_hdr_t *)0)->ee_size))) | ||
152 | #define VOYAGER_XSUM_END_OFFSET 0x2a | ||
153 | |||
154 | /* the following three definitions are for internal table layouts | ||
155 | * in the module EPROMs. We really only care about the IDs and | ||
156 | * offsets */ | ||
157 | typedef struct voyager_sp_table { | ||
158 | __u8 asic_id; | ||
159 | __u8 bypass_flag; | ||
160 | __u16 asic_data_offset; | ||
161 | __u16 config_data_offset; | ||
162 | } __attribute__((packed)) voyager_sp_table_t; | ||
163 | |||
164 | typedef struct voyager_jtag_table { | ||
165 | __u8 icode[4]; | ||
166 | __u8 runbist[4]; | ||
167 | __u8 intest[4]; | ||
168 | __u8 samp_preld[4]; | ||
169 | __u8 ireg_len; | ||
170 | } __attribute__((packed)) voyager_jtt_t; | ||
171 | |||
172 | typedef struct voyager_asic_data_table { | ||
173 | __u8 jtag_id[4]; | ||
174 | __u16 length_bsr; | ||
175 | __u16 length_bist_reg; | ||
176 | __u32 bist_clk; | ||
177 | __u16 subaddr_bits; | ||
178 | __u16 seed_bits; | ||
179 | __u16 sig_bits; | ||
180 | __u16 jtag_offset; | ||
181 | } __attribute__((packed)) voyager_at_t; | ||
182 | |||
183 | /* Voyager Interrupt Controller (VIC) registers */ | ||
184 | |||
185 | /* Base to add to Cross Processor Interrupts (CPIs) when triggering | ||
186 | * the CPU IRQ line */ | ||
187 | /* register defines for the WCBICs (one per processor) */ | ||
188 | #define VOYAGER_WCBIC0 0x41 /* bus A node P1 processor 0 */ | ||
189 | #define VOYAGER_WCBIC1 0x49 /* bus A node P1 processor 1 */ | ||
190 | #define VOYAGER_WCBIC2 0x51 /* bus A node P2 processor 0 */ | ||
191 | #define VOYAGER_WCBIC3 0x59 /* bus A node P2 processor 1 */ | ||
192 | #define VOYAGER_WCBIC4 0x61 /* bus B node P1 processor 0 */ | ||
193 | #define VOYAGER_WCBIC5 0x69 /* bus B node P1 processor 1 */ | ||
194 | #define VOYAGER_WCBIC6 0x71 /* bus B node P2 processor 0 */ | ||
195 | #define VOYAGER_WCBIC7 0x79 /* bus B node P2 processor 1 */ | ||
196 | |||
197 | |||
198 | /* top of memory registers */ | ||
199 | #define VOYAGER_WCBIC_TOM_L 0x4 | ||
200 | #define VOYAGER_WCBIC_TOM_H 0x5 | ||
201 | |||
202 | /* register defines for Voyager Memory Contol (VMC) | ||
203 | * these are present on L4 machines only */ | ||
204 | #define VOYAGER_VMC1 0x81 | ||
205 | #define VOYAGER_VMC2 0x91 | ||
206 | #define VOYAGER_VMC3 0xa1 | ||
207 | #define VOYAGER_VMC4 0xb1 | ||
208 | |||
209 | /* VMC Ports */ | ||
210 | #define VOYAGER_VMC_MEMORY_SETUP 0x9 | ||
211 | # define VMC_Interleaving 0x01 | ||
212 | # define VMC_4Way 0x02 | ||
213 | # define VMC_EvenCacheLines 0x04 | ||
214 | # define VMC_HighLine 0x08 | ||
215 | # define VMC_Start0_Enable 0x20 | ||
216 | # define VMC_Start1_Enable 0x40 | ||
217 | # define VMC_Vremap 0x80 | ||
218 | #define VOYAGER_VMC_BANK_DENSITY 0xa | ||
219 | # define VMC_BANK_EMPTY 0 | ||
220 | # define VMC_BANK_4MB 1 | ||
221 | # define VMC_BANK_16MB 2 | ||
222 | # define VMC_BANK_64MB 3 | ||
223 | # define VMC_BANK0_MASK 0x03 | ||
224 | # define VMC_BANK1_MASK 0x0C | ||
225 | # define VMC_BANK2_MASK 0x30 | ||
226 | # define VMC_BANK3_MASK 0xC0 | ||
227 | |||
228 | /* Magellan Memory Controller (MMC) defines - present on L5 */ | ||
229 | #define VOYAGER_MMC_ASIC_ID 1 | ||
230 | /* the two memory modules corresponding to memory cards in the system */ | ||
231 | #define VOYAGER_MMC_MEMORY0_MODULE 0x14 | ||
232 | #define VOYAGER_MMC_MEMORY1_MODULE 0x15 | ||
233 | /* the Magellan Memory Address (MMA) defines */ | ||
234 | #define VOYAGER_MMA_ASIC_ID 2 | ||
235 | |||
236 | /* Submodule number for the Quad Baseboard */ | ||
237 | #define VOYAGER_QUAD_BASEBOARD 1 | ||
238 | |||
239 | /* ASIC defines for the Quad Baseboard */ | ||
240 | #define VOYAGER_QUAD_QDATA0 1 | ||
241 | #define VOYAGER_QUAD_QDATA1 2 | ||
242 | #define VOYAGER_QUAD_QABC 3 | ||
243 | |||
244 | /* Useful areas in extended CMOS */ | ||
245 | #define VOYAGER_PROCESSOR_PRESENT_MASK 0x88a | ||
246 | #define VOYAGER_MEMORY_CLICKMAP 0xa23 | ||
247 | #define VOYAGER_DUMP_LOCATION 0xb1a | ||
248 | |||
249 | /* SUS In Control bit - used to tell SUS that we don't need to be | ||
250 | * babysat anymore */ | ||
251 | #define VOYAGER_SUS_IN_CONTROL_PORT 0x3ff | ||
252 | # define VOYAGER_IN_CONTROL_FLAG 0x80 | ||
253 | |||
254 | /* Voyager PSI defines */ | ||
255 | #define VOYAGER_PSI_STATUS_REG 0x08 | ||
256 | # define PSI_DC_FAIL 0x01 | ||
257 | # define PSI_MON 0x02 | ||
258 | # define PSI_FAULT 0x04 | ||
259 | # define PSI_ALARM 0x08 | ||
260 | # define PSI_CURRENT 0x10 | ||
261 | # define PSI_DVM 0x20 | ||
262 | # define PSI_PSCFAULT 0x40 | ||
263 | # define PSI_STAT_CHG 0x80 | ||
264 | |||
265 | #define VOYAGER_PSI_SUPPLY_REG 0x8000 | ||
266 | /* read */ | ||
267 | # define PSI_FAIL_DC 0x01 | ||
268 | # define PSI_FAIL_AC 0x02 | ||
269 | # define PSI_MON_INT 0x04 | ||
270 | # define PSI_SWITCH_OFF 0x08 | ||
271 | # define PSI_HX_OFF 0x10 | ||
272 | # define PSI_SECURITY 0x20 | ||
273 | # define PSI_CMOS_BATT_LOW 0x40 | ||
274 | # define PSI_CMOS_BATT_FAIL 0x80 | ||
275 | /* write */ | ||
276 | # define PSI_CLR_SWITCH_OFF 0x13 | ||
277 | # define PSI_CLR_HX_OFF 0x14 | ||
278 | # define PSI_CLR_CMOS_BATT_FAIL 0x17 | ||
279 | |||
280 | #define VOYAGER_PSI_MASK 0x8001 | ||
281 | # define PSI_MASK_MASK 0x10 | ||
282 | |||
283 | #define VOYAGER_PSI_AC_FAIL_REG 0x8004 | ||
284 | #define AC_FAIL_STAT_CHANGE 0x80 | ||
285 | |||
286 | #define VOYAGER_PSI_GENERAL_REG 0x8007 | ||
287 | /* read */ | ||
288 | # define PSI_SWITCH_ON 0x01 | ||
289 | # define PSI_SWITCH_ENABLED 0x02 | ||
290 | # define PSI_ALARM_ENABLED 0x08 | ||
291 | # define PSI_SECURE_ENABLED 0x10 | ||
292 | # define PSI_COLD_RESET 0x20 | ||
293 | # define PSI_COLD_START 0x80 | ||
294 | /* write */ | ||
295 | # define PSI_POWER_DOWN 0x10 | ||
296 | # define PSI_SWITCH_DISABLE 0x01 | ||
297 | # define PSI_SWITCH_ENABLE 0x11 | ||
298 | # define PSI_CLEAR 0x12 | ||
299 | # define PSI_ALARM_DISABLE 0x03 | ||
300 | # define PSI_ALARM_ENABLE 0x13 | ||
301 | # define PSI_CLEAR_COLD_RESET 0x05 | ||
302 | # define PSI_SET_COLD_RESET 0x15 | ||
303 | # define PSI_CLEAR_COLD_START 0x07 | ||
304 | # define PSI_SET_COLD_START 0x17 | ||
305 | |||
306 | |||
307 | |||
308 | struct voyager_bios_info { | ||
309 | __u8 len; | ||
310 | __u8 major; | ||
311 | __u8 minor; | ||
312 | __u8 debug; | ||
313 | __u8 num_classes; | ||
314 | __u8 class_1; | ||
315 | __u8 class_2; | ||
316 | }; | ||
317 | |||
318 | /* The following structures and definitions are for the Kernel/SUS | ||
319 | * interface these are needed to find out how SUS initialised any Quad | ||
320 | * boards in the system */ | ||
321 | |||
322 | #define NUMBER_OF_MC_BUSSES 2 | ||
323 | #define SLOTS_PER_MC_BUS 8 | ||
324 | #define MAX_CPUS 16 /* 16 way CPU system */ | ||
325 | #define MAX_PROCESSOR_BOARDS 4 /* 4 processor slot system */ | ||
326 | #define MAX_CACHE_LEVELS 4 /* # of cache levels supported */ | ||
327 | #define MAX_SHARED_CPUS 4 /* # of CPUs that can share a LARC */ | ||
328 | #define NUMBER_OF_POS_REGS 8 | ||
329 | |||
330 | typedef struct { | ||
331 | __u8 MC_Slot; | ||
332 | __u8 POS_Values[NUMBER_OF_POS_REGS]; | ||
333 | } __attribute__((packed)) MC_SlotInformation_t; | ||
334 | |||
335 | struct QuadDescription { | ||
336 | __u8 Type; /* for type 0 (DYADIC or MONADIC) all fields | ||
337 | * will be zero except for slot */ | ||
338 | __u8 StructureVersion; | ||
339 | __u32 CPI_BaseAddress; | ||
340 | __u32 LARC_BankSize; | ||
341 | __u32 LocalMemoryStateBits; | ||
342 | __u8 Slot; /* Processor slots 1 - 4 */ | ||
343 | } __attribute__((packed)); | ||
344 | |||
345 | struct ProcBoardInfo { | ||
346 | __u8 Type; | ||
347 | __u8 StructureVersion; | ||
348 | __u8 NumberOfBoards; | ||
349 | struct QuadDescription QuadData[MAX_PROCESSOR_BOARDS]; | ||
350 | } __attribute__((packed)); | ||
351 | |||
352 | struct CacheDescription { | ||
353 | __u8 Level; | ||
354 | __u32 TotalSize; | ||
355 | __u16 LineSize; | ||
356 | __u8 Associativity; | ||
357 | __u8 CacheType; | ||
358 | __u8 WriteType; | ||
359 | __u8 Number_CPUs_SharedBy; | ||
360 | __u8 Shared_CPUs_Hardware_IDs[MAX_SHARED_CPUS]; | ||
361 | |||
362 | } __attribute__((packed)); | ||
363 | |||
364 | struct CPU_Description { | ||
365 | __u8 CPU_HardwareId; | ||
366 | char *FRU_String; | ||
367 | __u8 NumberOfCacheLevels; | ||
368 | struct CacheDescription CacheLevelData[MAX_CACHE_LEVELS]; | ||
369 | } __attribute__((packed)); | ||
370 | |||
371 | struct CPU_Info { | ||
372 | __u8 Type; | ||
373 | __u8 StructureVersion; | ||
374 | __u8 NumberOf_CPUs; | ||
375 | struct CPU_Description CPU_Data[MAX_CPUS]; | ||
376 | } __attribute__((packed)); | ||
377 | |||
378 | |||
379 | /* | ||
380 | * This structure will be used by SUS and the OS. | ||
381 | * The assumption about this structure is that no blank space is | ||
382 | * packed in it by our friend the compiler. | ||
383 | */ | ||
384 | typedef struct { | ||
385 | __u8 Mailbox_SUS; /* Written to by SUS to give | ||
386 | commands/response to the OS */ | ||
387 | __u8 Mailbox_OS; /* Written to by the OS to give | ||
388 | commands/response to SUS */ | ||
389 | __u8 SUS_MailboxVersion; /* Tells the OS which iteration of the | ||
390 | interface SUS supports */ | ||
391 | __u8 OS_MailboxVersion; /* Tells SUS which iteration of the | ||
392 | interface the OS supports */ | ||
393 | __u32 OS_Flags; /* Flags set by the OS as info for | ||
394 | SUS */ | ||
395 | __u32 SUS_Flags; /* Flags set by SUS as info | ||
396 | for the OS */ | ||
397 | __u32 WatchDogPeriod; /* Watchdog period (in seconds) which | ||
398 | the DP uses to see if the OS | ||
399 | is dead */ | ||
400 | __u32 WatchDogCount; /* Updated by the OS on every tic. */ | ||
401 | __u32 MemoryFor_SUS_ErrorLog; /* Flat 32 bit address which tells SUS | ||
402 | where to stuff the SUS error log | ||
403 | on a dump */ | ||
404 | MC_SlotInformation_t MC_SlotInfo[NUMBER_OF_MC_BUSSES*SLOTS_PER_MC_BUS]; | ||
405 | /* Storage for MCA POS data */ | ||
406 | /* All new SECOND_PASS_INTERFACE fields added from this point */ | ||
407 | struct ProcBoardInfo *BoardData; | ||
408 | struct CPU_Info *CPU_Data; | ||
409 | /* All new fields must be added from this point */ | ||
410 | } Voyager_KernelSUS_Mbox_t; | ||
411 | |||
412 | /* structure for finding the right memory address to send a QIC CPI to */ | ||
413 | struct voyager_qic_cpi { | ||
414 | /* Each cache line (32 bytes) can trigger a cpi. The cpi | ||
415 | * read/write may occur anywhere in the cache line---pick the | ||
416 | * middle to be safe */ | ||
417 | struct { | ||
418 | __u32 pad1[3]; | ||
419 | __u32 cpi; | ||
420 | __u32 pad2[4]; | ||
421 | } qic_cpi[8]; | ||
422 | }; | ||
423 | |||
424 | struct voyager_status { | ||
425 | __u32 power_fail:1; | ||
426 | __u32 switch_off:1; | ||
427 | __u32 request_from_kernel:1; | ||
428 | }; | ||
429 | |||
430 | struct voyager_psi_regs { | ||
431 | __u8 cat_id; | ||
432 | __u8 cat_dev; | ||
433 | __u8 cat_control; | ||
434 | __u8 subaddr; | ||
435 | __u8 dummy4; | ||
436 | __u8 checkbit; | ||
437 | __u8 subaddr_low; | ||
438 | __u8 subaddr_high; | ||
439 | __u8 intstatus; | ||
440 | __u8 stat1; | ||
441 | __u8 stat3; | ||
442 | __u8 fault; | ||
443 | __u8 tms; | ||
444 | __u8 gen; | ||
445 | __u8 sysconf; | ||
446 | __u8 dummy15; | ||
447 | }; | ||
448 | |||
449 | struct voyager_psi_subregs { | ||
450 | __u8 supply; | ||
451 | __u8 mask; | ||
452 | __u8 present; | ||
453 | __u8 DCfail; | ||
454 | __u8 ACfail; | ||
455 | __u8 fail; | ||
456 | __u8 UPSfail; | ||
457 | __u8 genstatus; | ||
458 | }; | ||
459 | |||
460 | struct voyager_psi { | ||
461 | struct voyager_psi_regs regs; | ||
462 | struct voyager_psi_subregs subregs; | ||
463 | }; | ||
464 | |||
465 | struct voyager_SUS { | ||
466 | #define VOYAGER_DUMP_BUTTON_NMI 0x1 | ||
467 | #define VOYAGER_SUS_VALID 0x2 | ||
468 | #define VOYAGER_SYSINT_COMPLETE 0x3 | ||
469 | __u8 SUS_mbox; | ||
470 | #define VOYAGER_NO_COMMAND 0x0 | ||
471 | #define VOYAGER_IGNORE_DUMP 0x1 | ||
472 | #define VOYAGER_DO_DUMP 0x2 | ||
473 | #define VOYAGER_SYSINT_HANDSHAKE 0x3 | ||
474 | #define VOYAGER_DO_MEM_DUMP 0x4 | ||
475 | #define VOYAGER_SYSINT_WAS_RECOVERED 0x5 | ||
476 | __u8 kernel_mbox; | ||
477 | #define VOYAGER_MAILBOX_VERSION 0x10 | ||
478 | __u8 SUS_version; | ||
479 | __u8 kernel_version; | ||
480 | #define VOYAGER_OS_HAS_SYSINT 0x1 | ||
481 | #define VOYAGER_OS_IN_PROGRESS 0x2 | ||
482 | #define VOYAGER_UPDATING_WDPERIOD 0x4 | ||
483 | __u32 kernel_flags; | ||
484 | #define VOYAGER_SUS_BOOTING 0x1 | ||
485 | #define VOYAGER_SUS_IN_PROGRESS 0x2 | ||
486 | __u32 SUS_flags; | ||
487 | __u32 watchdog_period; | ||
488 | __u32 watchdog_count; | ||
489 | __u32 SUS_errorlog; | ||
490 | /* lots of system configuration stuff under here */ | ||
491 | }; | ||
492 | |||
493 | /* Variables exported by voyager_smp */ | ||
494 | extern __u32 voyager_extended_vic_processors; | ||
495 | extern __u32 voyager_allowed_boot_processors; | ||
496 | extern __u32 voyager_quad_processors; | ||
497 | extern struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS]; | ||
498 | extern struct voyager_SUS *voyager_SUS; | ||
499 | |||
500 | /* variables exported always */ | ||
501 | extern struct task_struct *voyager_thread; | ||
502 | extern int voyager_level; | ||
503 | extern struct voyager_status voyager_status; | ||
504 | |||
505 | /* functions exported by the voyager and voyager_smp modules */ | ||
506 | extern int voyager_cat_readb(__u8 module, __u8 asic, int reg); | ||
507 | extern void voyager_cat_init(void); | ||
508 | extern void voyager_detect(struct voyager_bios_info *); | ||
509 | extern void voyager_trap_init(void); | ||
510 | extern void voyager_setup_irqs(void); | ||
511 | extern int voyager_memory_detect(int region, __u32 *addr, __u32 *length); | ||
512 | extern void voyager_smp_intr_init(void); | ||
513 | extern __u8 voyager_extended_cmos_read(__u16 cmos_address); | ||
514 | extern void voyager_smp_dump(void); | ||
515 | extern void voyager_timer_interrupt(void); | ||
516 | extern void smp_local_timer_interrupt(void); | ||
517 | extern void voyager_power_off(void); | ||
518 | extern void smp_voyager_power_off(void *dummy); | ||
519 | extern void voyager_restart(void); | ||
520 | extern void voyager_cat_power_off(void); | ||
521 | extern void voyager_cat_do_common_interrupt(void); | ||
522 | extern void voyager_handle_nmi(void); | ||
523 | /* Commands for the following are */ | ||
524 | #define VOYAGER_PSI_READ 0 | ||
525 | #define VOYAGER_PSI_WRITE 1 | ||
526 | #define VOYAGER_PSI_SUBREAD 2 | ||
527 | #define VOYAGER_PSI_SUBWRITE 3 | ||
528 | extern void voyager_cat_psi(__u8, __u16, __u8 *); | ||