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author | Ingo Molnar <mingo@elte.hu> | 2009-03-28 17:27:45 -0400 |
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committer | Ingo Molnar <mingo@elte.hu> | 2009-03-28 17:27:45 -0400 |
commit | 3fab191002b184e4390aa07c7149c6cc7b638ec7 (patch) | |
tree | 821382d49e47c19531bfc3bb9e1f8922486374d4 /arch/x86/include/asm/msr-index.h | |
parent | 93394a761d78503f11d05b1a7b23d5a9ccc8dad2 (diff) | |
parent | 7c730ccdc1188b97f5c8cb690906242c7ed75c22 (diff) |
Merge branch 'linus' into x86/core
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
-rw-r--r-- | arch/x86/include/asm/msr-index.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 2dbd2314139e..ec41fc16c167 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h | |||
@@ -18,11 +18,15 @@ | |||
18 | #define _EFER_LME 8 /* Long mode enable */ | 18 | #define _EFER_LME 8 /* Long mode enable */ |
19 | #define _EFER_LMA 10 /* Long mode active (read-only) */ | 19 | #define _EFER_LMA 10 /* Long mode active (read-only) */ |
20 | #define _EFER_NX 11 /* No execute enable */ | 20 | #define _EFER_NX 11 /* No execute enable */ |
21 | #define _EFER_SVME 12 /* Enable virtualization */ | ||
22 | #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ | ||
21 | 23 | ||
22 | #define EFER_SCE (1<<_EFER_SCE) | 24 | #define EFER_SCE (1<<_EFER_SCE) |
23 | #define EFER_LME (1<<_EFER_LME) | 25 | #define EFER_LME (1<<_EFER_LME) |
24 | #define EFER_LMA (1<<_EFER_LMA) | 26 | #define EFER_LMA (1<<_EFER_LMA) |
25 | #define EFER_NX (1<<_EFER_NX) | 27 | #define EFER_NX (1<<_EFER_NX) |
28 | #define EFER_SVME (1<<_EFER_SVME) | ||
29 | #define EFER_FFXSR (1<<_EFER_FFXSR) | ||
26 | 30 | ||
27 | /* Intel MSRs. Some also available on other CPUs */ | 31 | /* Intel MSRs. Some also available on other CPUs */ |
28 | #define MSR_IA32_PERFCTR0 0x000000c1 | 32 | #define MSR_IA32_PERFCTR0 0x000000c1 |
@@ -365,4 +369,9 @@ | |||
365 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b | 369 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b |
366 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c | 370 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c |
367 | 371 | ||
372 | /* AMD-V MSRs */ | ||
373 | |||
374 | #define MSR_VM_CR 0xc0010114 | ||
375 | #define MSR_VM_HSAVE_PA 0xc0010117 | ||
376 | |||
368 | #endif /* _ASM_X86_MSR_INDEX_H */ | 377 | #endif /* _ASM_X86_MSR_INDEX_H */ |