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authorIngo Molnar <mingo@elte.hu>2009-01-27 22:09:58 -0500
committerIngo Molnar <mingo@elte.hu>2009-01-28 17:20:13 -0500
commit9b5bc8dc12421a4b17047061f473d85c1797d543 (patch)
tree69799378fb9e55dd8c23ceb39c646d7bf47523f8 /arch/x86/include/asm/mach-generic
parentf8987a1093cc7a896137e264c24e04d4048e9f95 (diff)
x86, apic: remove IRQ_DEST_MODE / IRQ_DELIVERY_MODE
Remove the wrapper macros IRQ_DEST_MODE and IRQ_DELIVERY_MODE. The typical 32-bit and the 64-bit build all dereference via the genapic, so it's pointless to hide that indirection via these ugly macros. Furthermore, it also obscures subarchitecture details. So replace it with apic->irq_dest_mode / etc. accesses. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include/asm/mach-generic')
-rw-r--r--arch/x86/include/asm/mach-generic/mach_apic.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/x86/include/asm/mach-generic/mach_apic.h b/arch/x86/include/asm/mach-generic/mach_apic.h
index 03492f2219ed..387a5d00c43d 100644
--- a/arch/x86/include/asm/mach-generic/mach_apic.h
+++ b/arch/x86/include/asm/mach-generic/mach_apic.h
@@ -5,8 +5,6 @@
5 5
6#define esr_disable (apic->ESR_DISABLE) 6#define esr_disable (apic->ESR_DISABLE)
7#define NO_BALANCE_IRQ (apic->no_balance_irq) 7#define NO_BALANCE_IRQ (apic->no_balance_irq)
8#define IRQ_DELIVERY_MODE (apic->irq_delivery_mode)
9#define IRQ_DEST_MODE (apic->irq_dest_mode)
10#undef APIC_DEST_LOGICAL 8#undef APIC_DEST_LOGICAL
11#define APIC_DEST_LOGICAL (apic->apic_destination_logical) 9#define APIC_DEST_LOGICAL (apic->apic_destination_logical)
12#define TARGET_CPUS (apic->target_cpus()) 10#define TARGET_CPUS (apic->target_cpus())