diff options
author | Ingo Molnar <mingo@elte.hu> | 2009-01-28 11:55:37 -0500 |
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committer | Ingo Molnar <mingo@elte.hu> | 2009-01-29 08:16:42 -0500 |
commit | 1dcdd3d15ecea0c22a09d4d001a39d425fceff2c (patch) | |
tree | 91419ae421b2d1cac6297c9671eac2ff7723d7c2 /arch/x86/include/asm/mach-default | |
parent | 7c20dcc545d78946e40e8fab99637fe815b1d211 (diff) |
x86: remove mach_apic.h
Spread mach_apic.h definitions into genapic.h. (with some knock-on effects
on smp.h and apic.h.)
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include/asm/mach-default')
-rw-r--r-- | arch/x86/include/asm/mach-default/mach_apic.h | 144 |
1 files changed, 0 insertions, 144 deletions
diff --git a/arch/x86/include/asm/mach-default/mach_apic.h b/arch/x86/include/asm/mach-default/mach_apic.h deleted file mode 100644 index bae053cdcde5..000000000000 --- a/arch/x86/include/asm/mach-default/mach_apic.h +++ /dev/null | |||
@@ -1,144 +0,0 @@ | |||
1 | #ifndef _ASM_X86_MACH_DEFAULT_MACH_APIC_H | ||
2 | #define _ASM_X86_MACH_DEFAULT_MACH_APIC_H | ||
3 | |||
4 | #ifdef CONFIG_X86_LOCAL_APIC | ||
5 | |||
6 | #include <asm/smp.h> | ||
7 | |||
8 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) | ||
9 | |||
10 | static inline const struct cpumask *default_target_cpus(void) | ||
11 | { | ||
12 | #ifdef CONFIG_SMP | ||
13 | return cpu_online_mask; | ||
14 | #else | ||
15 | return cpumask_of(0); | ||
16 | #endif | ||
17 | } | ||
18 | |||
19 | #ifdef CONFIG_X86_64 | ||
20 | #include <asm/genapic.h> | ||
21 | #define read_apic_id() (apic->get_apic_id(apic_read(APIC_ID))) | ||
22 | extern void default_setup_apic_routing(void); | ||
23 | #else | ||
24 | /* | ||
25 | * Set up the logical destination ID. | ||
26 | * | ||
27 | * Intel recommends to set DFR, LDR and TPR before enabling | ||
28 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | ||
29 | * document number 292116). So here it goes... | ||
30 | */ | ||
31 | static inline void default_init_apic_ldr(void) | ||
32 | { | ||
33 | unsigned long val; | ||
34 | |||
35 | apic_write(APIC_DFR, APIC_DFR_VALUE); | ||
36 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | ||
37 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | ||
38 | apic_write(APIC_LDR, val); | ||
39 | } | ||
40 | |||
41 | static inline int default_apic_id_registered(void) | ||
42 | { | ||
43 | return physid_isset(read_apic_id(), phys_cpu_present_map); | ||
44 | } | ||
45 | |||
46 | static inline unsigned int | ||
47 | default_cpu_mask_to_apicid(const struct cpumask *cpumask) | ||
48 | { | ||
49 | return cpumask_bits(cpumask)[0]; | ||
50 | } | ||
51 | |||
52 | static inline unsigned int | ||
53 | default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | ||
54 | const struct cpumask *andmask) | ||
55 | { | ||
56 | unsigned long mask1 = cpumask_bits(cpumask)[0]; | ||
57 | unsigned long mask2 = cpumask_bits(andmask)[0]; | ||
58 | unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; | ||
59 | |||
60 | return (unsigned int)(mask1 & mask2 & mask3); | ||
61 | } | ||
62 | |||
63 | static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) | ||
64 | { | ||
65 | return cpuid_apic >> index_msb; | ||
66 | } | ||
67 | |||
68 | static inline void default_setup_apic_routing(void) | ||
69 | { | ||
70 | #ifdef CONFIG_X86_IO_APIC | ||
71 | printk("Enabling APIC mode: %s. Using %d I/O APICs\n", | ||
72 | "Flat", nr_ioapics); | ||
73 | #endif | ||
74 | } | ||
75 | |||
76 | static inline int default_apicid_to_node(int logical_apicid) | ||
77 | { | ||
78 | #ifdef CONFIG_SMP | ||
79 | return apicid_2_node[hard_smp_processor_id()]; | ||
80 | #else | ||
81 | return 0; | ||
82 | #endif | ||
83 | } | ||
84 | |||
85 | #endif | ||
86 | |||
87 | static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid) | ||
88 | { | ||
89 | return physid_isset(apicid, bitmap); | ||
90 | } | ||
91 | |||
92 | static inline unsigned long default_check_apicid_present(int bit) | ||
93 | { | ||
94 | return physid_isset(bit, phys_cpu_present_map); | ||
95 | } | ||
96 | |||
97 | static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map) | ||
98 | { | ||
99 | return phys_map; | ||
100 | } | ||
101 | |||
102 | /* Mapping from cpu number to logical apicid */ | ||
103 | static inline int default_cpu_to_logical_apicid(int cpu) | ||
104 | { | ||
105 | return 1 << cpu; | ||
106 | } | ||
107 | |||
108 | static inline int __default_cpu_present_to_apicid(int mps_cpu) | ||
109 | { | ||
110 | if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) | ||
111 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); | ||
112 | else | ||
113 | return BAD_APICID; | ||
114 | } | ||
115 | |||
116 | static inline int | ||
117 | __default_check_phys_apicid_present(int boot_cpu_physical_apicid) | ||
118 | { | ||
119 | return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map); | ||
120 | } | ||
121 | |||
122 | #ifdef CONFIG_X86_32 | ||
123 | static inline int default_cpu_present_to_apicid(int mps_cpu) | ||
124 | { | ||
125 | return __default_cpu_present_to_apicid(mps_cpu); | ||
126 | } | ||
127 | |||
128 | static inline int | ||
129 | default_check_phys_apicid_present(int boot_cpu_physical_apicid) | ||
130 | { | ||
131 | return __default_check_phys_apicid_present(boot_cpu_physical_apicid); | ||
132 | } | ||
133 | #else | ||
134 | extern int default_cpu_present_to_apicid(int mps_cpu); | ||
135 | extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid); | ||
136 | #endif | ||
137 | |||
138 | static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid) | ||
139 | { | ||
140 | return physid_mask_of_physid(phys_apicid); | ||
141 | } | ||
142 | |||
143 | #endif /* CONFIG_X86_LOCAL_APIC */ | ||
144 | #endif /* _ASM_X86_MACH_DEFAULT_MACH_APIC_H */ | ||