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authorIngo Molnar <mingo@elte.hu>2008-10-28 11:26:12 -0400
committerIngo Molnar <mingo@elte.hu>2008-10-28 11:26:12 -0400
commit7a9787e1eba95a166265e6a260cf30af04ef0a99 (patch)
treee730a4565e0318140d2fbd2f0415d18a339d7336 /arch/x86/include/asm/io_apic.h
parent41b9eb264c8407655db57b60b4457fe1b2ec9977 (diff)
parent0173a3265b228da319ceb9c1ec6a5682fd1b2d92 (diff)
Merge commit 'v2.6.28-rc2' into x86/pci-ioapic-boot-irq-quirks
Diffstat (limited to 'arch/x86/include/asm/io_apic.h')
-rw-r--r--arch/x86/include/asm/io_apic.h214
1 files changed, 214 insertions, 0 deletions
diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
new file mode 100644
index 000000000000..e475e009ae5d
--- /dev/null
+++ b/arch/x86/include/asm/io_apic.h
@@ -0,0 +1,214 @@
1#ifndef _ASM_X86_IO_APIC_H
2#define _ASM_X86_IO_APIC_H
3
4#include <linux/types.h>
5#include <asm/mpspec.h>
6#include <asm/apicdef.h>
7#include <asm/irq_vectors.h>
8
9/*
10 * Intel IO-APIC support for SMP and UP systems.
11 *
12 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
13 */
14
15/* I/O Unit Redirection Table */
16#define IO_APIC_REDIR_VECTOR_MASK 0x000FF
17#define IO_APIC_REDIR_DEST_LOGICAL 0x00800
18#define IO_APIC_REDIR_DEST_PHYSICAL 0x00000
19#define IO_APIC_REDIR_SEND_PENDING (1 << 12)
20#define IO_APIC_REDIR_REMOTE_IRR (1 << 14)
21#define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15)
22#define IO_APIC_REDIR_MASKED (1 << 16)
23
24/*
25 * The structure of the IO-APIC:
26 */
27union IO_APIC_reg_00 {
28 u32 raw;
29 struct {
30 u32 __reserved_2 : 14,
31 LTS : 1,
32 delivery_type : 1,
33 __reserved_1 : 8,
34 ID : 8;
35 } __attribute__ ((packed)) bits;
36};
37
38union IO_APIC_reg_01 {
39 u32 raw;
40 struct {
41 u32 version : 8,
42 __reserved_2 : 7,
43 PRQ : 1,
44 entries : 8,
45 __reserved_1 : 8;
46 } __attribute__ ((packed)) bits;
47};
48
49union IO_APIC_reg_02 {
50 u32 raw;
51 struct {
52 u32 __reserved_2 : 24,
53 arbitration : 4,
54 __reserved_1 : 4;
55 } __attribute__ ((packed)) bits;
56};
57
58union IO_APIC_reg_03 {
59 u32 raw;
60 struct {
61 u32 boot_DT : 1,
62 __reserved_1 : 31;
63 } __attribute__ ((packed)) bits;
64};
65
66enum ioapic_irq_destination_types {
67 dest_Fixed = 0,
68 dest_LowestPrio = 1,
69 dest_SMI = 2,
70 dest__reserved_1 = 3,
71 dest_NMI = 4,
72 dest_INIT = 5,
73 dest__reserved_2 = 6,
74 dest_ExtINT = 7
75};
76
77struct IO_APIC_route_entry {
78 __u32 vector : 8,
79 delivery_mode : 3, /* 000: FIXED
80 * 001: lowest prio
81 * 111: ExtINT
82 */
83 dest_mode : 1, /* 0: physical, 1: logical */
84 delivery_status : 1,
85 polarity : 1,
86 irr : 1,
87 trigger : 1, /* 0: edge, 1: level */
88 mask : 1, /* 0: enabled, 1: disabled */
89 __reserved_2 : 15;
90
91 __u32 __reserved_3 : 24,
92 dest : 8;
93} __attribute__ ((packed));
94
95struct IR_IO_APIC_route_entry {
96 __u64 vector : 8,
97 zero : 3,
98 index2 : 1,
99 delivery_status : 1,
100 polarity : 1,
101 irr : 1,
102 trigger : 1,
103 mask : 1,
104 reserved : 31,
105 format : 1,
106 index : 15;
107} __attribute__ ((packed));
108
109#ifdef CONFIG_X86_IO_APIC
110
111/*
112 * # of IO-APICs and # of IRQ routing registers
113 */
114extern int nr_ioapics;
115extern int nr_ioapic_registers[MAX_IO_APICS];
116
117/*
118 * MP-BIOS irq configuration table structures:
119 */
120
121#define MP_MAX_IOAPIC_PIN 127
122
123struct mp_config_ioapic {
124 unsigned long mp_apicaddr;
125 unsigned int mp_apicid;
126 unsigned char mp_type;
127 unsigned char mp_apicver;
128 unsigned char mp_flags;
129};
130
131struct mp_config_intsrc {
132 unsigned int mp_dstapic;
133 unsigned char mp_type;
134 unsigned char mp_irqtype;
135 unsigned short mp_irqflag;
136 unsigned char mp_srcbus;
137 unsigned char mp_srcbusirq;
138 unsigned char mp_dstirq;
139};
140
141/* I/O APIC entries */
142extern struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
143
144/* # of MP IRQ source entries */
145extern int mp_irq_entries;
146
147/* MP IRQ source entries */
148extern struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
149
150/* non-0 if default (table-less) MP configuration */
151extern int mpc_default_type;
152
153/* Older SiS APIC requires we rewrite the index register */
154extern int sis_apic_bug;
155
156/* 1 if "noapic" boot option passed */
157extern int skip_ioapic_setup;
158
159/* 1 if "noapic" boot option passed */
160extern int noioapicquirk;
161
162/* -1 if "noapic" boot option passed */
163extern int noioapicreroute;
164
165/* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */
166extern int timer_through_8259;
167
168static inline void disable_ioapic_setup(void)
169{
170#ifdef CONFIG_PCI
171 noioapicquirk = 1;
172 noioapicreroute = -1;
173#endif
174 skip_ioapic_setup = 1;
175}
176
177/*
178 * If we use the IO-APIC for IRQ routing, disable automatic
179 * assignment of PCI IRQ's.
180 */
181#define io_apic_assign_pci_irqs \
182 (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
183
184#ifdef CONFIG_ACPI
185extern int io_apic_get_unique_id(int ioapic, int apic_id);
186extern int io_apic_get_version(int ioapic);
187extern int io_apic_get_redir_entries(int ioapic);
188extern int io_apic_set_pci_routing(int ioapic, int pin, int irq,
189 int edge_level, int active_high_low);
190#endif /* CONFIG_ACPI */
191
192extern int (*ioapic_renumber_irq)(int ioapic, int irq);
193extern void ioapic_init_mappings(void);
194
195#ifdef CONFIG_X86_64
196extern int save_mask_IO_APIC_setup(void);
197extern void restore_IO_APIC_setup(void);
198extern void reinit_intr_remapped_IO_APIC(int);
199#endif
200
201extern int probe_nr_irqs(void);
202
203#else /* !CONFIG_X86_IO_APIC */
204#define io_apic_assign_pci_irqs 0
205static const int timer_through_8259 = 0;
206static inline void ioapic_init_mappings(void) { }
207
208static inline int probe_nr_irqs(void)
209{
210 return NR_IRQS;
211}
212#endif
213
214#endif /* _ASM_X86_IO_APIC_H */
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