aboutsummaryrefslogtreecommitdiffstats
path: root/arch/x86/include/asm/genapic.h
diff options
context:
space:
mode:
authorIngo Molnar <mingo@elte.hu>2009-02-17 07:52:29 -0500
committerIngo Molnar <mingo@elte.hu>2009-02-17 11:52:43 -0500
commite2780a68f889c9d7ec8e78d58a3a2be8cfebf202 (patch)
tree3ce8d1417b46805574adca60907bd8e064db1c21 /arch/x86/include/asm/genapic.h
parent28aa29eeb3918f820b914679cfc4404972f2df32 (diff)
x86, apic: merge genapic.h into apic.h
Impact: cleanup Reduce the number of include files to worry about. Also, most of the users of APIC facilities had to include genapic.h already, which embedded apic.h, so the distinction was meaningless. [ include apic.h from genapic.h for compatibility. ] Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include/asm/genapic.h')
-rw-r--r--arch/x86/include/asm/genapic.h312
1 files changed, 0 insertions, 312 deletions
diff --git a/arch/x86/include/asm/genapic.h b/arch/x86/include/asm/genapic.h
index 9b874a386837..4b8b98fa7f25 100644
--- a/arch/x86/include/asm/genapic.h
+++ b/arch/x86/include/asm/genapic.h
@@ -1,313 +1 @@
1#ifndef _ASM_X86_GENAPIC_H
2#define _ASM_X86_GENAPIC_H
3
4#include <linux/cpumask.h>
5
6#include <asm/mpspec.h>
7#include <asm/atomic.h>
8#include <asm/apic.h> #include <asm/apic.h>
9
10/*
11 * Copyright 2004 James Cleverdon, IBM.
12 * Subject to the GNU Public License, v.2
13 *
14 * Generic APIC sub-arch data struct.
15 *
16 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
17 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
18 * James Cleverdon.
19 */
20struct genapic {
21 char *name;
22
23 int (*probe)(void);
24 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
25 int (*apic_id_registered)(void);
26
27 u32 irq_delivery_mode;
28 u32 irq_dest_mode;
29
30 const struct cpumask *(*target_cpus)(void);
31
32 int disable_esr;
33
34 int dest_logical;
35 unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid);
36 unsigned long (*check_apicid_present)(int apicid);
37
38 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
39 void (*init_apic_ldr)(void);
40
41 physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map);
42
43 void (*setup_apic_routing)(void);
44 int (*multi_timer_check)(int apic, int irq);
45 int (*apicid_to_node)(int logical_apicid);
46 int (*cpu_to_logical_apicid)(int cpu);
47 int (*cpu_present_to_apicid)(int mps_cpu);
48 physid_mask_t (*apicid_to_cpu_present)(int phys_apicid);
49 void (*setup_portio_remap)(void);
50 int (*check_phys_apicid_present)(int boot_cpu_physical_apicid);
51 void (*enable_apic_mode)(void);
52 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
53
54 /*
55 * When one of the next two hooks returns 1 the genapic
56 * is switched to this. Essentially they are additional
57 * probe functions:
58 */
59 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
60
61 unsigned int (*get_apic_id)(unsigned long x);
62 unsigned long (*set_apic_id)(unsigned int id);
63 unsigned long apic_id_mask;
64
65 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
66 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
67 const struct cpumask *andmask);
68
69 /* ipi */
70 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
71 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
72 int vector);
73 void (*send_IPI_allbutself)(int vector);
74 void (*send_IPI_all)(int vector);
75 void (*send_IPI_self)(int vector);
76
77 /* wakeup_secondary_cpu */
78 int (*wakeup_cpu)(int apicid, unsigned long start_eip);
79
80 int trampoline_phys_low;
81 int trampoline_phys_high;
82
83 void (*wait_for_init_deassert)(atomic_t *deassert);
84 void (*smp_callin_clear_local_apic)(void);
85 void (*store_NMI_vector)(unsigned short *high, unsigned short *low);
86 void (*inquire_remote_apic)(int apicid);
87
88 /* apic ops */
89 u32 (*read)(u32 reg);
90 void (*write)(u32 reg, u32 v);
91 u64 (*icr_read)(void);
92 void (*icr_write)(u32 low, u32 high);
93 void (*wait_icr_idle)(void);
94 u32 (*safe_wait_icr_idle)(void);
95};
96
97extern struct genapic *apic;
98
99static inline u32 apic_read(u32 reg)
100{
101 return apic->read(reg);
102}
103
104static inline void apic_write(u32 reg, u32 val)
105{
106 apic->write(reg, val);
107}
108
109static inline u64 apic_icr_read(void)
110{
111 return apic->icr_read();
112}
113
114static inline void apic_icr_write(u32 low, u32 high)
115{
116 apic->icr_write(low, high);
117}
118
119static inline void apic_wait_icr_idle(void)
120{
121 apic->wait_icr_idle();
122}
123
124static inline u32 safe_apic_wait_icr_idle(void)
125{
126 return apic->safe_wait_icr_idle();
127}
128
129
130static inline void ack_APIC_irq(void)
131{
132 /*
133 * ack_APIC_irq() actually gets compiled as a single instruction
134 * ... yummie.
135 */
136
137 /* Docs say use 0 for future compatibility */
138 apic_write(APIC_EOI, 0);
139}
140
141static inline unsigned default_get_apic_id(unsigned long x)
142{
143 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
144
145 if (APIC_XAPIC(ver))
146 return (x >> 24) & 0xFF;
147 else
148 return (x >> 24) & 0x0F;
149}
150
151/*
152 * Warm reset vector default position:
153 */
154#define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
155#define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
156
157#ifdef CONFIG_X86_32
158extern void es7000_update_genapic_to_cluster(void);
159#else
160extern struct genapic apic_flat;
161extern struct genapic apic_physflat;
162extern struct genapic apic_x2apic_cluster;
163extern struct genapic apic_x2apic_phys;
164extern int default_acpi_madt_oem_check(char *, char *);
165
166extern void apic_send_IPI_self(int vector);
167
168extern struct genapic apic_x2apic_uv_x;
169DECLARE_PER_CPU(int, x2apic_extra_bits);
170
171extern int default_cpu_present_to_apicid(int mps_cpu);
172extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
173#endif
174
175static inline void default_wait_for_init_deassert(atomic_t *deassert)
176{
177 while (!atomic_read(deassert))
178 cpu_relax();
179 return;
180}
181
182extern void generic_bigsmp_probe(void);
183
184
185#ifdef CONFIG_X86_LOCAL_APIC
186
187#include <asm/smp.h>
188
189#define APIC_DFR_VALUE (APIC_DFR_FLAT)
190
191static inline const struct cpumask *default_target_cpus(void)
192{
193#ifdef CONFIG_SMP
194 return cpu_online_mask;
195#else
196 return cpumask_of(0);
197#endif
198}
199
200DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
201
202
203static inline unsigned int read_apic_id(void)
204{
205 unsigned int reg;
206
207 reg = apic_read(APIC_ID);
208
209 return apic->get_apic_id(reg);
210}
211
212extern void default_setup_apic_routing(void);
213
214#ifdef CONFIG_X86_32
215/*
216 * Set up the logical destination ID.
217 *
218 * Intel recommends to set DFR, LDR and TPR before enabling
219 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
220 * document number 292116). So here it goes...
221 */
222extern void default_init_apic_ldr(void);
223
224static inline int default_apic_id_registered(void)
225{
226 return physid_isset(read_apic_id(), phys_cpu_present_map);
227}
228
229static inline unsigned int
230default_cpu_mask_to_apicid(const struct cpumask *cpumask)
231{
232 return cpumask_bits(cpumask)[0];
233}
234
235static inline unsigned int
236default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
237 const struct cpumask *andmask)
238{
239 unsigned long mask1 = cpumask_bits(cpumask)[0];
240 unsigned long mask2 = cpumask_bits(andmask)[0];
241 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
242
243 return (unsigned int)(mask1 & mask2 & mask3);
244}
245
246static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
247{
248 return cpuid_apic >> index_msb;
249}
250
251extern int default_apicid_to_node(int logical_apicid);
252
253#endif
254
255static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
256{
257 return physid_isset(apicid, bitmap);
258}
259
260static inline unsigned long default_check_apicid_present(int bit)
261{
262 return physid_isset(bit, phys_cpu_present_map);
263}
264
265static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map)
266{
267 return phys_map;
268}
269
270/* Mapping from cpu number to logical apicid */
271static inline int default_cpu_to_logical_apicid(int cpu)
272{
273 return 1 << cpu;
274}
275
276static inline int __default_cpu_present_to_apicid(int mps_cpu)
277{
278 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
279 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
280 else
281 return BAD_APICID;
282}
283
284static inline int
285__default_check_phys_apicid_present(int boot_cpu_physical_apicid)
286{
287 return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
288}
289
290#ifdef CONFIG_X86_32
291static inline int default_cpu_present_to_apicid(int mps_cpu)
292{
293 return __default_cpu_present_to_apicid(mps_cpu);
294}
295
296static inline int
297default_check_phys_apicid_present(int boot_cpu_physical_apicid)
298{
299 return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
300}
301#else
302extern int default_cpu_present_to_apicid(int mps_cpu);
303extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
304#endif
305
306static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid)
307{
308 return physid_mask_of_physid(phys_apicid);
309}
310
311#endif /* CONFIG_X86_LOCAL_APIC */
312
313#endif /* _ASM_X86_GENAPIC_64_H */