aboutsummaryrefslogtreecommitdiffstats
path: root/arch/x86/include/asm/alternative.h
diff options
context:
space:
mode:
authorBorislav Petkov <borislav.petkov@amd.com>2010-03-05 11:34:46 -0500
committerH. Peter Anvin <hpa@zytor.com>2010-04-06 18:52:11 -0400
commitd61931d89be506372d01a90d1755f6d0a9fafe2d (patch)
tree652c34238edcb6c558163abc3cd9d6ce7c5f91a5 /arch/x86/include/asm/alternative.h
parent1527bc8b928dd1399c3d3467dd47d9ede210978a (diff)
x86: Add optimized popcnt variants
Add support for the hardware version of the Hamming weight function, popcnt, present in CPUs which advertize it under CPUID, Function 0x0000_0001_ECX[23]. On CPUs which don't support it, we fallback to the default lib/hweight.c sw versions. A synthetic benchmark comparing popcnt with __sw_hweight64 showed almost a 3x speedup on a F10h machine. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> LKML-Reference: <20100318112015.GC11152@aftab> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/include/asm/alternative.h')
-rw-r--r--arch/x86/include/asm/alternative.h9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/x86/include/asm/alternative.h b/arch/x86/include/asm/alternative.h
index b09ec55650b3..67dae51e7fd0 100644
--- a/arch/x86/include/asm/alternative.h
+++ b/arch/x86/include/asm/alternative.h
@@ -39,9 +39,6 @@
39#define LOCK_PREFIX "" 39#define LOCK_PREFIX ""
40#endif 40#endif
41 41
42/* This must be included *after* the definition of LOCK_PREFIX */
43#include <asm/cpufeature.h>
44
45struct alt_instr { 42struct alt_instr {
46 u8 *instr; /* original instruction */ 43 u8 *instr; /* original instruction */
47 u8 *replacement; 44 u8 *replacement;
@@ -96,6 +93,12 @@ static inline int alternatives_text_reserved(void *start, void *end)
96 ".previous" 93 ".previous"
97 94
98/* 95/*
96 * This must be included *after* the definition of ALTERNATIVE due to
97 * <asm/arch_hweight.h>
98 */
99#include <asm/cpufeature.h>
100
101/*
99 * Alternative instructions for different CPU types or capabilities. 102 * Alternative instructions for different CPU types or capabilities.
100 * 103 *
101 * This allows to use optimized instructions even on generic binary 104 * This allows to use optimized instructions even on generic binary