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authorH. Peter Anvin <hpa@zytor.com>2008-01-30 07:30:56 -0500
committerIngo Molnar <mingo@elte.hu>2008-01-30 07:30:56 -0500
commit65ea5b0349903585bfed9720fa06f5edb4f1cd25 (patch)
tree6c252228c34416b7e2077f23475de34500c2ab8a /arch/x86/ia32/ia32_aout.c
parent53756d3722172815f52272b28c6d5d5e9639adde (diff)
x86: rename the struct pt_regs members for 32/64-bit consistency
We have a lot of code which differs only by the naming of specific members of structures that contain registers. In order to enable additional unifications, this patch drops the e- or r- size prefix from the register names in struct pt_regs, and drops the x- prefixes for segment registers on the 32-bit side. This patch also performs the equivalent renames in some additional places that might be candidates for unification in the future. Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/ia32/ia32_aout.c')
-rw-r--r--arch/x86/ia32/ia32_aout.c30
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c
index a764e4e95314..f1a0f83676dc 100644
--- a/arch/x86/ia32/ia32_aout.c
+++ b/arch/x86/ia32/ia32_aout.c
@@ -53,7 +53,7 @@ static void dump_thread32(struct pt_regs *regs, struct user32 *dump)
53/* changed the size calculations - should hopefully work better. lbt */ 53/* changed the size calculations - should hopefully work better. lbt */
54 dump->magic = CMAGIC; 54 dump->magic = CMAGIC;
55 dump->start_code = 0; 55 dump->start_code = 0;
56 dump->start_stack = regs->rsp & ~(PAGE_SIZE - 1); 56 dump->start_stack = regs->sp & ~(PAGE_SIZE - 1);
57 dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT; 57 dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT;
58 dump->u_dsize = ((unsigned long) 58 dump->u_dsize = ((unsigned long)
59 (current->mm->brk + (PAGE_SIZE-1))) >> PAGE_SHIFT; 59 (current->mm->brk + (PAGE_SIZE-1))) >> PAGE_SHIFT;
@@ -75,22 +75,22 @@ static void dump_thread32(struct pt_regs *regs, struct user32 *dump)
75 dump->u_ssize = tmp >> PAGE_SHIFT; 75 dump->u_ssize = tmp >> PAGE_SHIFT;
76 } 76 }
77 77
78 dump->regs.ebx = regs->rbx; 78 dump->regs.bx = regs->bx;
79 dump->regs.ecx = regs->rcx; 79 dump->regs.cx = regs->cx;
80 dump->regs.edx = regs->rdx; 80 dump->regs.dx = regs->dx;
81 dump->regs.esi = regs->rsi; 81 dump->regs.si = regs->si;
82 dump->regs.edi = regs->rdi; 82 dump->regs.di = regs->di;
83 dump->regs.ebp = regs->rbp; 83 dump->regs.bp = regs->bp;
84 dump->regs.eax = regs->rax; 84 dump->regs.ax = regs->ax;
85 dump->regs.ds = current->thread.ds; 85 dump->regs.ds = current->thread.ds;
86 dump->regs.es = current->thread.es; 86 dump->regs.es = current->thread.es;
87 asm("movl %%fs,%0" : "=r" (fs)); dump->regs.fs = fs; 87 asm("movl %%fs,%0" : "=r" (fs)); dump->regs.fs = fs;
88 asm("movl %%gs,%0" : "=r" (gs)); dump->regs.gs = gs; 88 asm("movl %%gs,%0" : "=r" (gs)); dump->regs.gs = gs;
89 dump->regs.orig_eax = regs->orig_rax; 89 dump->regs.orig_ax = regs->orig_ax;
90 dump->regs.eip = regs->rip; 90 dump->regs.ip = regs->ip;
91 dump->regs.cs = regs->cs; 91 dump->regs.cs = regs->cs;
92 dump->regs.eflags = regs->eflags; 92 dump->regs.flags = regs->flags;
93 dump->regs.esp = regs->rsp; 93 dump->regs.sp = regs->sp;
94 dump->regs.ss = regs->ss; 94 dump->regs.ss = regs->ss;
95 95
96#if 1 /* FIXME */ 96#if 1 /* FIXME */
@@ -432,9 +432,9 @@ beyond_if:
432 asm volatile("movl %0,%%fs" :: "r" (0)); \ 432 asm volatile("movl %0,%%fs" :: "r" (0)); \
433 asm volatile("movl %0,%%es; movl %0,%%ds": :"r" (__USER32_DS)); 433 asm volatile("movl %0,%%es; movl %0,%%ds": :"r" (__USER32_DS));
434 load_gs_index(0); 434 load_gs_index(0);
435 (regs)->rip = ex.a_entry; 435 (regs)->ip = ex.a_entry;
436 (regs)->rsp = current->mm->start_stack; 436 (regs)->sp = current->mm->start_stack;
437 (regs)->eflags = 0x200; 437 (regs)->flags = 0x200;
438 (regs)->cs = __USER32_CS; 438 (regs)->cs = __USER32_CS;
439 (regs)->ss = __USER32_DS; 439 (regs)->ss = __USER32_DS;
440 regs->r8 = regs->r9 = regs->r10 = regs->r11 = 440 regs->r8 = regs->r9 = regs->r10 = regs->r11 =