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authorGuanXuetao <gxt@mprc.pku.edu.cn>2011-01-15 05:15:01 -0500
committerGuanXuetao <gxt@mprc.pku.edu.cn>2011-03-16 21:19:06 -0400
commit79725df5786d2fa48f582b116ea1d74193cc96ca (patch)
treef617d939932294048eb448649066f0d248987411 /arch/unicore32/mm
parent87c1a3fb7c07322dfd63a63dd6d42339ad52ddee (diff)
unicore32 core architecture: processor and system headers
This patch includes processor and system headers. System call interface is here. We used the syscall interface the same as asm-generic version. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/unicore32/mm')
-rw-r--r--arch/unicore32/mm/proc-macros.S145
-rw-r--r--arch/unicore32/mm/proc-ucv2.S134
2 files changed, 279 insertions, 0 deletions
diff --git a/arch/unicore32/mm/proc-macros.S b/arch/unicore32/mm/proc-macros.S
new file mode 100644
index 000000000000..51560d68c894
--- /dev/null
+++ b/arch/unicore32/mm/proc-macros.S
@@ -0,0 +1,145 @@
1/*
2 * linux/arch/unicore32/mm/proc-macros.S
3 *
4 * Code specific to PKUnity SoC and UniCore ISA
5 *
6 * Copyright (C) 2001-2010 GUAN Xue-tao
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * We need constants.h for:
13 * VMA_VM_MM
14 * VMA_VM_FLAGS
15 * VM_EXEC
16 */
17#include <generated/asm-offsets.h>
18#include <asm/thread_info.h>
19#include <asm/memory.h>
20
21/*
22 * the cache line sizes of the I and D cache are the same
23 */
24#define CACHE_LINESIZE 32
25
26/*
27 * This is the maximum size of an area which will be invalidated
28 * using the single invalidate entry instructions. Anything larger
29 * than this, and we go for the whole cache.
30 *
31 * This value should be chosen such that we choose the cheapest
32 * alternative.
33 */
34#ifdef CONFIG_CPU_UCV2
35#define MAX_AREA_SIZE 0x800 /* 64 cache line */
36#endif
37
38/*
39 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
40 */
41 .macro vma_vm_mm, rd, rn
42 ldw \rd, [\rn+], #VMA_VM_MM
43 .endm
44
45/*
46 * vma_vm_flags - get vma->vm_flags
47 */
48 .macro vma_vm_flags, rd, rn
49 ldw \rd, [\rn+], #VMA_VM_FLAGS
50 .endm
51
52 .macro tsk_mm, rd, rn
53 ldw \rd, [\rn+], #TI_TASK
54 ldw \rd, [\rd+], #TSK_ACTIVE_MM
55 .endm
56
57/*
58 * act_mm - get current->active_mm
59 */
60 .macro act_mm, rd
61 andn \rd, sp, #8128
62 andn \rd, \rd, #63
63 ldw \rd, [\rd+], #TI_TASK
64 ldw \rd, [\rd+], #TSK_ACTIVE_MM
65 .endm
66
67/*
68 * mmid - get context id from mm pointer (mm->context.id)
69 */
70 .macro mmid, rd, rn
71 ldw \rd, [\rn+], #MM_CONTEXT_ID
72 .endm
73
74/*
75 * mask_asid - mask the ASID from the context ID
76 */
77 .macro asid, rd, rn
78 and \rd, \rn, #255
79 .endm
80
81 .macro crval, clear, mmuset, ucset
82 .word \clear
83 .word \mmuset
84 .endm
85
86#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
87/*
88 * va2pa va, pa, tbl, msk, off, err
89 * This macro is used to translate virtual address to its physical address.
90 *
91 * va: virtual address
92 * pa: physical address, result is stored in this register
93 * tbl, msk, off: temp registers, will be destroyed
94 * err: jump to error label if the physical address not exist
95 * NOTE: all regs must be different
96 */
97 .macro va2pa, va, pa, tbl, msk, off, err=990f
98 movc \pa, p0.c2, #0
99 mov \off, \va >> #22 @ off <- index of 1st page table
100 adr \tbl, 910f @ tbl <- table of 1st page table
101900: @ ---- handle 1, 2 page table
102 add \pa, \pa, #PAGE_OFFSET @ pa <- virt addr of page table
103 ldw \pa, [\pa+], \off << #2 @ pa <- the content of pt
104 cand.a \pa, #4 @ test exist bit
105 beq \err @ if not exist
106 and \off, \pa, #3 @ off <- the last 2 bits
107 add \tbl, \tbl, \off << #3 @ cmove table pointer
108 ldw \msk, [\tbl+], #0 @ get the mask
109 ldw pc, [\tbl+], #4
110930: @ ---- handle 2nd page table
111 and \pa, \pa, \msk @ pa <- phys addr of 2nd pt
112 mov \off, \va << #10
113 cntlo \tbl, \msk @ use tbl as temp reg
114 mov \off, \off >> \tbl
115 mov \off, \off >> #2 @ off <- index of 2nd pt
116 adr \tbl, 920f @ tbl <- table of 2nd pt
117 b 900b
118910: @ 1st level page table
119 .word 0xfffff000, 930b @ second level page table
120 .word 0xfffffc00, 930b @ second level large page table
121 .word 0x00000000, \err @ invalid
122 .word 0xffc00000, 980f @ super page
123
124920: @ 2nd level page table
125 .word 0xfffff000, 980f @ page
126 .word 0xffffc000, 980f @ middle page
127 .word 0xffff0000, 980f @ large page
128 .word 0x00000000, \err @ invalid
129980:
130 andn \tbl, \va, \msk
131 and \pa, \pa, \msk
132 or \pa, \pa, \tbl
133990:
134 .endm
135#endif
136
137 .macro dcacheline_flush, addr, t1, t2
138 mov \t1, \addr << #20
139 ldw \t2, =_stext @ _stext must ALIGN(4096)
140 add \t2, \t2, \t1 >> #20
141 ldw \t1, [\t2+], #0x0000
142 ldw \t1, [\t2+], #0x1000
143 ldw \t1, [\t2+], #0x2000
144 ldw \t1, [\t2+], #0x3000
145 .endm
diff --git a/arch/unicore32/mm/proc-ucv2.S b/arch/unicore32/mm/proc-ucv2.S
new file mode 100644
index 000000000000..9d296092e362
--- /dev/null
+++ b/arch/unicore32/mm/proc-ucv2.S
@@ -0,0 +1,134 @@
1/*
2 * linux/arch/unicore32/mm/proc-ucv2.S
3 *
4 * Code specific to PKUnity SoC and UniCore ISA
5 *
6 * Copyright (C) 2001-2010 GUAN Xue-tao
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/init.h>
13#include <linux/linkage.h>
14#include <asm/assembler.h>
15#include <asm/hwcap.h>
16#include <asm/pgtable-hwdef.h>
17#include <asm/pgtable.h>
18
19#include "proc-macros.S"
20
21ENTRY(cpu_proc_fin)
22 stm.w (lr), [sp-]
23 mov ip, #PSR_R_BIT | PSR_I_BIT | PRIV_MODE
24 mov.a asr, ip
25 b.l __cpuc_flush_kern_all
26 ldm.w (pc), [sp]+
27
28/*
29 * cpu_reset(loc)
30 *
31 * Perform a soft reset of the system. Put the CPU into the
32 * same state as it would be if it had been reset, and branch
33 * to what would be the reset vector.
34 *
35 * - loc - location to jump to for soft reset
36 */
37 .align 5
38ENTRY(cpu_reset)
39 mov ip, #0
40 movc p0.c5, ip, #28 @ Cache invalidate all
41 nop8
42
43 movc p0.c6, ip, #6 @ TLB invalidate all
44 nop8
45
46 movc ip, p0.c1, #0 @ ctrl register
47 or ip, ip, #0x2000 @ vector base address
48 andn ip, ip, #0x000f @ ............idam
49 movc p0.c1, ip, #0 @ disable caches and mmu
50 nop
51 mov pc, r0 @ jump to loc
52 nop8
53
54/*
55 * cpu_do_idle()
56 *
57 * Idle the processor (eg, wait for interrupt).
58 *
59 * IRQs are already disabled.
60 */
61ENTRY(cpu_do_idle)
62 mov r0, #0 @ PCI address
63 .rept 8
64 ldw r1, [r0]
65 .endr
66 mov pc, lr
67
68ENTRY(cpu_dcache_clean_area)
69#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
70 csub.a r1, #MAX_AREA_SIZE
71 bsg 101f
72 mov r9, #PAGE_SZ
73 sub r9, r9, #1 @ PAGE_MASK
741: va2pa r0, r10, r11, r12, r13 @ r10 is PA
75 b 3f
762: cand.a r0, r9
77 beq 1b
783: movc p0.c5, r10, #11 @ clean D entry
79 nop8
80 add r0, r0, #CACHE_LINESIZE
81 add r10, r10, #CACHE_LINESIZE
82 sub.a r1, r1, #CACHE_LINESIZE
83 bua 2b
84 mov pc, lr
85#endif
86101: mov ip, #0
87 movc p0.c5, ip, #10 @ Dcache clean all
88 nop8
89
90 mov pc, lr
91
92/*
93 * cpu_do_switch_mm(pgd_phys)
94 *
95 * Set the translation table base pointer to be pgd_phys
96 *
97 * - pgd_phys - physical address of new pgd
98 *
99 * It is assumed that:
100 * - we are not using split page tables
101 */
102 .align 5
103ENTRY(cpu_do_switch_mm)
104 movc p0.c2, r0, #0 @ update page table ptr
105 nop8
106
107 movc p0.c6, ip, #6 @ TLB invalidate all
108 nop8
109
110 mov pc, lr
111
112/*
113 * cpu_set_pte(ptep, pte)
114 *
115 * Set a level 2 translation table entry.
116 *
117 * - ptep - pointer to level 2 translation table entry
118 * - pte - PTE value to store
119 */
120 .align 5
121ENTRY(cpu_set_pte)
122 stw r1, [r0]
123#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
124 sub r2, r0, #PAGE_OFFSET
125 movc p0.c5, r2, #11 @ Dcache clean line
126 nop8
127#else
128 mov ip, #0
129 movc p0.c5, ip, #10 @ Dcache clean all
130 nop8
131 @dcacheline_flush r0, r2, ip
132#endif
133 mov pc, lr
134
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 01:37:45 -0500