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authorChris Metcalf <cmetcalf@tilera.com>2012-03-30 15:47:38 -0400
committerChris Metcalf <cmetcalf@tilera.com>2012-04-02 12:13:53 -0400
commit54229ff359250ce7292dbeb59f157a2d3b67e30c (patch)
treedff9b36a7097c4606e2133610fa97426cf3dbcff /arch/tile
parentab306cae660e524edbeb8889e4e23d3c97717b9c (diff)
arch/tile: fix finv_buffer_remote() for tilegx
There were some correctness issues with this code that are now fixed with this change. The change is likely less performant than it could be, but it should no longer be vulnerable to any races with memory operations on the memory network while invalidating a range of memory. This code is run infrequently so performance isn't critical, but correctness definitely is. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile')
-rw-r--r--arch/tile/lib/cacheflush.c28
1 files changed, 26 insertions, 2 deletions
diff --git a/arch/tile/lib/cacheflush.c b/arch/tile/lib/cacheflush.c
index 6af2b97a6886..db4fb89e12d8 100644
--- a/arch/tile/lib/cacheflush.c
+++ b/arch/tile/lib/cacheflush.c
@@ -39,7 +39,21 @@ void finv_buffer_remote(void *buffer, size_t size, int hfh)
39{ 39{
40 char *p, *base; 40 char *p, *base;
41 size_t step_size, load_count; 41 size_t step_size, load_count;
42
43 /*
44 * On TILEPro the striping granularity is a fixed 8KB; on
45 * TILE-Gx it is configurable, and we rely on the fact that
46 * the hypervisor always configures maximum striping, so that
47 * bits 9 and 10 of the PA are part of the stripe function, so
48 * every 512 bytes we hit a striping boundary.
49 *
50 */
51#ifdef __tilegx__
52 const unsigned long STRIPE_WIDTH = 512;
53#else
42 const unsigned long STRIPE_WIDTH = 8192; 54 const unsigned long STRIPE_WIDTH = 8192;
55#endif
56
43#ifdef __tilegx__ 57#ifdef __tilegx__
44 /* 58 /*
45 * On TILE-Gx, we must disable the dstream prefetcher before doing 59 * On TILE-Gx, we must disable the dstream prefetcher before doing
@@ -74,7 +88,7 @@ void finv_buffer_remote(void *buffer, size_t size, int hfh)
74 * memory, that one load would be sufficient, but since we may 88 * memory, that one load would be sufficient, but since we may
75 * be, we also need to back up to the last load issued to 89 * be, we also need to back up to the last load issued to
76 * another memory controller, which would be the point where 90 * another memory controller, which would be the point where
77 * we crossed an 8KB boundary (the granularity of striping 91 * we crossed a "striping" boundary (the granularity of striping
78 * across memory controllers). Keep backing up and doing this 92 * across memory controllers). Keep backing up and doing this
79 * until we are before the beginning of the buffer, or have 93 * until we are before the beginning of the buffer, or have
80 * hit all the controllers. 94 * hit all the controllers.
@@ -88,12 +102,22 @@ void finv_buffer_remote(void *buffer, size_t size, int hfh)
88 * every cache line on a full memory stripe on each 102 * every cache line on a full memory stripe on each
89 * controller" that we simply do that, to simplify the logic. 103 * controller" that we simply do that, to simplify the logic.
90 * 104 *
91 * FIXME: See bug 9535 for some issues with this code. 105 * On TILE-Gx the hash-for-home function is much more complex,
106 * with the upshot being we can't readily guarantee we have
107 * hit both entries in the 128-entry AMT that were hit by any
108 * load in the entire range, so we just re-load them all.
109 * With larger buffers, we may want to consider using a hypervisor
110 * trap to issue loads directly to each hash-for-home tile for
111 * each controller (doing it from Linux would trash the TLB).
92 */ 112 */
93 if (hfh) { 113 if (hfh) {
94 step_size = L2_CACHE_BYTES; 114 step_size = L2_CACHE_BYTES;
115#ifdef __tilegx__
116 load_count = (size + L2_CACHE_BYTES - 1) / L2_CACHE_BYTES;
117#else
95 load_count = (STRIPE_WIDTH / L2_CACHE_BYTES) * 118 load_count = (STRIPE_WIDTH / L2_CACHE_BYTES) *
96 (1 << CHIP_LOG_NUM_MSHIMS()); 119 (1 << CHIP_LOG_NUM_MSHIMS());
120#endif
97 } else { 121 } else {
98 step_size = STRIPE_WIDTH; 122 step_size = STRIPE_WIDTH;
99 load_count = (1 << CHIP_LOG_NUM_MSHIMS()); 123 load_count = (1 << CHIP_LOG_NUM_MSHIMS());