Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile

* git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile: (26 commits)
  arch/tile: prefer "tilepro" as the name of the 32-bit architecture
  compat: include aio_abi.h for aio_context_t
  arch/tile: cleanups for tilegx compat mode
  arch/tile: allocate PCI IRQs later in boot
  arch/tile: support signal "exception-trace" hook
  arch/tile: use better definitions of xchg() and cmpxchg()
  include/linux/compat.h: coding-style fixes
  tile: add an RTC driver for the Tilera hypervisor
  arch/tile: finish enabling support for TILE-Gx 64-bit chip
  compat: fixes to allow working with tile arch
  arch/tile: update defconfig file to something more useful
  tile: do_hardwall_trap: do not play with task->sighand
  tile: replace mm->cpu_vm_mask with mm_cpumask()
  tile,mn10300: add device parameter to dma_cache_sync()
  audit: support the "standard" <asm-generic/unistd.h>
  arch/tile: clarify flush_buffer()/finv_buffer() function names
  arch/tile: kernel-related cleanups from removing static page size
  arch/tile: various header improvements for building drivers
  arch/tile: disable GX prefetcher during cache flush
  arch/tile: tolerate disabling CONFIG_BLK_DEV_INITRD
  ...

1 files changed, 18 insertions, 0 deletions

diff --git a/arch/tile/lib/cacheflush.c b/arch/tile/lib/cacheflush.c
index 35c1d8ca5f38..8928aace7a64 100644
--- a/arch/tile/lib/cacheflush.c
+++ b/arch/tile/lib/cacheflush.c
@@ -15,6 +15,7 @@
 #include <asm/page.h>
 #include <asm/cacheflush.h>
 #include <arch/icache.h>
+#include <arch/spr_def.h>
 
 
 void __flush_icache_range(unsigned long start, unsigned long end)
@@ -39,6 +40,18 @@ void finv_buffer_remote(void *buffer, size_t size, int hfh)
         char *p, *base;
         size_t step_size, load_count;
         const unsigned long STRIPE_WIDTH = 8192;
+#ifdef __tilegx__
+        /*
+         * On TILE-Gx, we must disable the dstream prefetcher before doing
+         * a cache flush; otherwise, we could end up with data in the cache
+         * that we don't want there.  Note that normally we'd do an mf
+         * after the SPR write to disabling the prefetcher, but we do one
+         * below, before any further loads, so there's no need to do it
+         * here.
+         */
+        uint_reg_t old_dstream_pf = __insn_mfspr(SPR_DSTREAM_PF);
+        __insn_mtspr(SPR_DSTREAM_PF, 0);
+#endif
 
         /*
          * Flush and invalidate the buffer out of the local L1/L2
@@ -122,4 +135,9 @@ void finv_buffer_remote(void *buffer, size_t size, int hfh)
 
         /* Wait for the load+inv's (and thus finvs) to have completed. */
         __insn_mf();
+
+#ifdef __tilegx__
+        /* Reenable the prefetcher. */
+        __insn_mtspr(SPR_DSTREAM_PF, old_dstream_pf);
+#endif
 }