diff options
| author | Chris Metcalf <cmetcalf@tilera.com> | 2010-08-13 20:43:39 -0400 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2010-08-15 11:05:33 -0400 |
| commit | b3ae98ab8217a8621859e1d9cbf3ee6c4c19533b (patch) | |
| tree | dfab5358562d26fcdf9924346cde822252ec3192 /arch/tile/include | |
| parent | 947e7dc1aed0532478e10988328bfd7426e0c2bd (diff) | |
arch/tile: rename ARCH_KMALLOC_MINALIGN to ARCH_DMA_MINALIGN
See commit a6eb9fe105d5de0053b261148cee56c94b4720ca.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Acked-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Diffstat (limited to 'arch/tile/include')
| -rw-r--r-- | arch/tile/include/asm/cache.h | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h index f6101840c9e7..08a2815b5e4e 100644 --- a/arch/tile/include/asm/cache.h +++ b/arch/tile/include/asm/cache.h | |||
| @@ -27,11 +27,10 @@ | |||
| 27 | #define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES) | 27 | #define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES) |
| 28 | 28 | ||
| 29 | /* | 29 | /* |
| 30 | * TILE-Gx is fully coherents so we don't need to define | 30 | * TILE-Gx is fully coherent so we don't need to define ARCH_DMA_MINALIGN. |
| 31 | * ARCH_KMALLOC_MINALIGN. | ||
| 32 | */ | 31 | */ |
| 33 | #ifndef __tilegx__ | 32 | #ifndef __tilegx__ |
| 34 | #define ARCH_KMALLOC_MINALIGN L2_CACHE_BYTES | 33 | #define ARCH_DMA_MINALIGN L2_CACHE_BYTES |
| 35 | #endif | 34 | #endif |
| 36 | 35 | ||
| 37 | /* use the cache line size for the L2, which is where it counts */ | 36 | /* use the cache line size for the L2, which is where it counts */ |