diff options
| author | Chris Metcalf <cmetcalf@tilera.com> | 2011-05-02 15:22:18 -0400 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2011-05-04 14:40:16 -0400 |
| commit | 7194988fb5add6341b95f4501f6778bf27b4d3de (patch) | |
| tree | 8271874e8ffeb61927b94f5d8a48d76db7e43a0b /arch/tile/include/asm | |
| parent | df29ccb6c06dcb65867d4fd3c2fa473017f60ecc (diff) | |
arch/tile: disable SD_WAKE_AFFINE flag on CPU/NODE scheduling domain
This allows processes to spread more effectively to multiple cores
(particularly important on 64-core chips!).
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/include/asm')
| -rw-r--r-- | arch/tile/include/asm/topology.h | 75 |
1 files changed, 57 insertions, 18 deletions
diff --git a/arch/tile/include/asm/topology.h b/arch/tile/include/asm/topology.h index 343172d422a9..6fdd0c860193 100644 --- a/arch/tile/include/asm/topology.h +++ b/arch/tile/include/asm/topology.h | |||
| @@ -44,25 +44,64 @@ static inline const struct cpumask *cpumask_of_node(int node) | |||
| 44 | /* For now, use numa node -1 for global allocation. */ | 44 | /* For now, use numa node -1 for global allocation. */ |
| 45 | #define pcibus_to_node(bus) ((void)(bus), -1) | 45 | #define pcibus_to_node(bus) ((void)(bus), -1) |
| 46 | 46 | ||
| 47 | /* | ||
| 48 | * TILE architecture has many cores integrated in one processor, so we need | ||
| 49 | * setup bigger balance_interval for both CPU/NODE scheduling domains to | ||
| 50 | * reduce process scheduling costs. | ||
| 51 | */ | ||
| 52 | |||
| 53 | /* sched_domains SD_CPU_INIT for TILE architecture */ | ||
| 54 | #define SD_CPU_INIT (struct sched_domain) { \ | ||
| 55 | .min_interval = 4, \ | ||
| 56 | .max_interval = 128, \ | ||
| 57 | .busy_factor = 64, \ | ||
| 58 | .imbalance_pct = 125, \ | ||
| 59 | .cache_nice_tries = 1, \ | ||
| 60 | .busy_idx = 2, \ | ||
| 61 | .idle_idx = 1, \ | ||
| 62 | .newidle_idx = 0, \ | ||
| 63 | .wake_idx = 0, \ | ||
| 64 | .forkexec_idx = 0, \ | ||
| 65 | \ | ||
| 66 | .flags = 1*SD_LOAD_BALANCE \ | ||
| 67 | | 1*SD_BALANCE_NEWIDLE \ | ||
| 68 | | 1*SD_BALANCE_EXEC \ | ||
| 69 | | 1*SD_BALANCE_FORK \ | ||
| 70 | | 0*SD_BALANCE_WAKE \ | ||
| 71 | | 0*SD_WAKE_AFFINE \ | ||
| 72 | | 0*SD_PREFER_LOCAL \ | ||
| 73 | | 0*SD_SHARE_CPUPOWER \ | ||
| 74 | | 0*SD_SHARE_PKG_RESOURCES \ | ||
| 75 | | 0*SD_SERIALIZE \ | ||
| 76 | , \ | ||
| 77 | .last_balance = jiffies, \ | ||
| 78 | .balance_interval = 32, \ | ||
| 79 | } | ||
| 80 | |||
| 47 | /* sched_domains SD_NODE_INIT for TILE architecture */ | 81 | /* sched_domains SD_NODE_INIT for TILE architecture */ |
| 48 | #define SD_NODE_INIT (struct sched_domain) { \ | 82 | #define SD_NODE_INIT (struct sched_domain) { \ |
| 49 | .min_interval = 8, \ | 83 | .min_interval = 16, \ |
| 50 | .max_interval = 32, \ | 84 | .max_interval = 512, \ |
| 51 | .busy_factor = 32, \ | 85 | .busy_factor = 32, \ |
| 52 | .imbalance_pct = 125, \ | 86 | .imbalance_pct = 125, \ |
| 53 | .cache_nice_tries = 1, \ | 87 | .cache_nice_tries = 1, \ |
| 54 | .busy_idx = 3, \ | 88 | .busy_idx = 3, \ |
| 55 | .idle_idx = 1, \ | 89 | .idle_idx = 1, \ |
| 56 | .newidle_idx = 2, \ | 90 | .newidle_idx = 2, \ |
| 57 | .wake_idx = 1, \ | 91 | .wake_idx = 1, \ |
| 58 | .flags = SD_LOAD_BALANCE \ | 92 | .flags = 1*SD_LOAD_BALANCE \ |
| 59 | | SD_BALANCE_NEWIDLE \ | 93 | | 1*SD_BALANCE_NEWIDLE \ |
| 60 | | SD_BALANCE_EXEC \ | 94 | | 1*SD_BALANCE_EXEC \ |
| 61 | | SD_BALANCE_FORK \ | 95 | | 1*SD_BALANCE_FORK \ |
| 62 | | SD_WAKE_AFFINE \ | 96 | | 0*SD_BALANCE_WAKE \ |
| 63 | | SD_SERIALIZE, \ | 97 | | 0*SD_WAKE_AFFINE \ |
| 64 | .last_balance = jiffies, \ | 98 | | 0*SD_PREFER_LOCAL \ |
| 65 | .balance_interval = 1, \ | 99 | | 0*SD_SHARE_CPUPOWER \ |
| 100 | | 0*SD_SHARE_PKG_RESOURCES \ | ||
| 101 | | 1*SD_SERIALIZE \ | ||
| 102 | , \ | ||
| 103 | .last_balance = jiffies, \ | ||
| 104 | .balance_interval = 128, \ | ||
| 66 | } | 105 | } |
| 67 | 106 | ||
| 68 | /* By definition, we create nodes based on online memory. */ | 107 | /* By definition, we create nodes based on online memory. */ |