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authorChris Metcalf <cmetcalf@tilera.com>2010-09-15 11:16:10 -0400
committerChris Metcalf <cmetcalf@tilera.com>2010-09-15 11:16:10 -0400
commita802fc685426303ab627b7ad3fd5c97b5dea7e00 (patch)
tree29a4ae60405318129efc0897f311a6ac4b1328d2 /arch/tile/include/asm
parent74fca9da097b74117ae2cef9e5f0d9b0e28ccbb7 (diff)
arch/tile: Save and restore extra user state for tilegx
During context switch, save and restore a couple of additional bits of tilegx user state that can be persistently modified by userspace. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/include/asm')
-rw-r--r--arch/tile/include/asm/processor.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/tile/include/asm/processor.h b/arch/tile/include/asm/processor.h
index d942d09b252e..ccd5f8425688 100644
--- a/arch/tile/include/asm/processor.h
+++ b/arch/tile/include/asm/processor.h
@@ -103,6 +103,18 @@ struct thread_struct {
103 /* Any other miscellaneous processor state bits */ 103 /* Any other miscellaneous processor state bits */
104 unsigned long proc_status; 104 unsigned long proc_status;
105#endif 105#endif
106#if !CHIP_HAS_FIXED_INTVEC_BASE()
107 /* Interrupt base for PL0 interrupts */
108 unsigned long interrupt_vector_base;
109#endif
110#if CHIP_HAS_TILE_RTF_HWM()
111 /* Tile cache retry fifo high-water mark */
112 unsigned long tile_rtf_hwm;
113#endif
114#if CHIP_HAS_DSTREAM_PF()
115 /* Data stream prefetch control */
116 unsigned long dstream_pf;
117#endif
106#ifdef CONFIG_HARDWALL 118#ifdef CONFIG_HARDWALL
107 /* Is this task tied to an activated hardwall? */ 119 /* Is this task tied to an activated hardwall? */
108 struct hardwall_info *hardwall; 120 struct hardwall_info *hardwall;