arch/tile: support <asm/cachectl.h> header for cacheflush() syscall

We already had a syscall that did some dcache flushing, but it was
not used in practice.  Make it MIPS compatible instead so it can
do both the DCACHE and ICACHE actions.  We have code that wants to
be able to use the ICACHE flush mode from userspace so this change
enables that.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/tile/include/asm/unistd.h b/arch/tile/include/asm/unistd.h
index f70bf1c541f1..a017246ca0ce 100644
--- a/arch/tile/include/asm/unistd.h
+++ b/arch/tile/include/asm/unistd.h
@@ -24,8 +24,8 @@
 #include <asm-generic/unistd.h>
 
 /* Additional Tilera-specific syscalls. */
-#define __NR_flush_cache        (__NR_arch_specific_syscall + 1)
-__SYSCALL(__NR_flush_cache, sys_flush_cache)
+#define __NR_cacheflush (__NR_arch_specific_syscall + 1)
+__SYSCALL(__NR_cacheflush, sys_cacheflush)
 
 #ifndef __tilegx__
 /* "Fast" syscalls provide atomic support for 32-bit chips. */