diff options
author | Chris Metcalf <cmetcalf@tilera.com> | 2012-07-18 12:06:19 -0400 |
---|---|---|
committer | Chris Metcalf <cmetcalf@tilera.com> | 2012-07-18 16:54:16 -0400 |
commit | f6d2ce00da145ae31ec22d21daca6ca5e22b3c84 (patch) | |
tree | bb030290bc253b37bfad91de618c6f080f0b0af9 /arch/tile/include/asm/pci.h | |
parent | f1006257893917dfb1e0d74cb47b18c0e2908693 (diff) |
tile: updates to pci root complex from community feedback
Reviewed-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/include/asm/pci.h')
-rw-r--r-- | arch/tile/include/asm/pci.h | 27 |
1 files changed, 8 insertions, 19 deletions
diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h index 553b7ff018c4..302cdf71ceed 100644 --- a/arch/tile/include/asm/pci.h +++ b/arch/tile/include/asm/pci.h | |||
@@ -128,15 +128,10 @@ static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {} | |||
128 | #define TILE_PCI_MEM_MAP_BASE_OFFSET (1ULL << CHIP_PA_WIDTH()) | 128 | #define TILE_PCI_MEM_MAP_BASE_OFFSET (1ULL << CHIP_PA_WIDTH()) |
129 | 129 | ||
130 | /* | 130 | /* |
131 | * End of the PCI memory resource. | 131 | * Start of the PCI memory resource, which starts at the end of the |
132 | * maximum system physical RAM address. | ||
132 | */ | 133 | */ |
133 | #define TILE_PCI_MEM_END \ | 134 | #define TILE_PCI_MEM_START (1ULL << CHIP_PA_WIDTH()) |
134 | ((1ULL << CHIP_PA_WIDTH()) + TILE_PCI_BAR_WINDOW_TOP) | ||
135 | |||
136 | /* | ||
137 | * Start of the PCI memory resource. | ||
138 | */ | ||
139 | #define TILE_PCI_MEM_START (TILE_PCI_MEM_END - TILE_PCI_BAR_WINDOW_SIZE) | ||
140 | 135 | ||
141 | /* | 136 | /* |
142 | * Structure of a PCI controller (host bridge) on Gx. | 137 | * Structure of a PCI controller (host bridge) on Gx. |
@@ -159,17 +154,19 @@ struct pci_controller { | |||
159 | int index; /* PCI domain number */ | 154 | int index; /* PCI domain number */ |
160 | struct pci_bus *root_bus; | 155 | struct pci_bus *root_bus; |
161 | 156 | ||
157 | /* PCI memory space resource for this controller. */ | ||
158 | struct resource mem_space; | ||
159 | char mem_space_name[32]; | ||
160 | |||
162 | uint64_t mem_offset; /* cpu->bus memory mapping offset. */ | 161 | uint64_t mem_offset; /* cpu->bus memory mapping offset. */ |
163 | 162 | ||
164 | int last_busno; | 163 | int first_busno; |
165 | 164 | ||
166 | struct pci_ops *ops; | 165 | struct pci_ops *ops; |
167 | 166 | ||
168 | /* Table that maps the INTx numbers to Linux irq numbers. */ | 167 | /* Table that maps the INTx numbers to Linux irq numbers. */ |
169 | int irq_intx_table[4]; | 168 | int irq_intx_table[4]; |
170 | 169 | ||
171 | struct resource mem_space; | ||
172 | |||
173 | /* Address ranges that are routed to this controller/bridge. */ | 170 | /* Address ranges that are routed to this controller/bridge. */ |
174 | struct resource mem_resources[3]; | 171 | struct resource mem_resources[3]; |
175 | }; | 172 | }; |
@@ -179,14 +176,6 @@ extern gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO]; | |||
179 | 176 | ||
180 | extern void pci_iounmap(struct pci_dev *dev, void __iomem *); | 177 | extern void pci_iounmap(struct pci_dev *dev, void __iomem *); |
181 | 178 | ||
182 | extern void | ||
183 | pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | ||
184 | struct resource *res); | ||
185 | |||
186 | extern void | ||
187 | pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | ||
188 | struct pci_bus_region *region); | ||
189 | |||
190 | /* | 179 | /* |
191 | * The PCI address space does not equal the physical memory address | 180 | * The PCI address space does not equal the physical memory address |
192 | * space (we have an IOMMU). The IDE and SCSI device layers use this | 181 | * space (we have an IOMMU). The IDE and SCSI device layers use this |