tilegx pci: support I/O to arbitrarily-cached pages

The tilegx PCI root complex support (currently only in linux-next)
is limited to pages that are homed on cached in the default manner,
i.e. "hash-for-home".  This change supports delivery of I/O data to
pages that are cached in other ways (locally on a particular core,
uncached, user-managed incoherent, etc.).

A large part of the change is supporting flushing pages from cache
on particular homes so that we can transition the data that we are
delivering to or from the device appropriately.  The new homecache_finv*
routines handle this.

Some changes to page_table_range_init() were also required to make
the fixmap code work correctly on tilegx; it hadn't been used there
before.

We also remove some stub mark_caches_evicted_*() routines that
were just no-ops anyway.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>

1 files changed, 3 insertions, 4 deletions

diff --git a/arch/tile/include/asm/page.h b/arch/tile/include/asm/page.h
index 9d9131e5c552..dd033a4fd627 100644
--- a/arch/tile/include/asm/page.h
+++ b/arch/tile/include/asm/page.h
@@ -174,7 +174,9 @@ static inline __attribute_const__ int get_order(unsigned long size)
 #define MEM_LOW_END             (HALF_VA_SPACE - 1)         /* low half */
 #define MEM_HIGH_START          (-HALF_VA_SPACE)            /* high half */
 #define PAGE_OFFSET             MEM_HIGH_START
-#define _VMALLOC_START          _AC(0xfffffff500000000, UL) /* 4 GB */
+#define FIXADDR_BASE            _AC(0xfffffff400000000, UL) /* 4 GB */
+#define FIXADDR_TOP             _AC(0xfffffff500000000, UL) /* 4 GB */
+#define _VMALLOC_START          FIXADDR_TOP
 #define HUGE_VMAP_BASE          _AC(0xfffffff600000000, UL) /* 4 GB */
 #define MEM_SV_START            _AC(0xfffffff700000000, UL) /* 256 MB */
 #define MEM_SV_INTRPT           MEM_SV_START
@@ -185,9 +187,6 @@ static inline __attribute_const__ int get_order(unsigned long size)
 /* Highest DTLB address we will use */
 #define KERNEL_HIGH_VADDR       MEM_SV_START
 
-/* Since we don't currently provide any fixmaps, we use an impossible VA. */
-#define FIXADDR_TOP             MEM_HV_START
-
 #else /* !__tilegx__ */
 
 /*