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authorChris Metcalf <cmetcalf@tilera.com>2013-02-01 13:01:36 -0500
committerChris Metcalf <cmetcalf@tilera.com>2013-02-04 12:53:15 -0500
commit7f04f0816848a51b761db6e7958e42f127e8264c (patch)
tree26775c66a74e2083b3d7f459547f24c83c6ae7b3 /arch/tile/include/asm/irqflags.h
parenta05d3f9fa3b496b2894c73bb8cbb49deb09b41db (diff)
tile: avoid defining INT_MASK macro in <arch/interrupts.h>
Unfortunately, this name conflicts with a different use of the name in various places through the tree, so don't provide it for the kernel. We preserve it for userspace to avoid breaking any userspace code that relies on this definition. This fixes a number of compile errors for various drivers that are enabled by "allyesconfig". Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/include/asm/irqflags.h')
-rw-r--r--arch/tile/include/asm/irqflags.h32
1 files changed, 10 insertions, 22 deletions
diff --git a/arch/tile/include/asm/irqflags.h b/arch/tile/include/asm/irqflags.h
index b4e96fef2cf8..241c0bb60b12 100644
--- a/arch/tile/include/asm/irqflags.h
+++ b/arch/tile/include/asm/irqflags.h
@@ -18,32 +18,20 @@
18#include <arch/interrupts.h> 18#include <arch/interrupts.h>
19#include <arch/chip.h> 19#include <arch/chip.h>
20 20
21#if !defined(__tilegx__) && defined(__ASSEMBLY__)
22
23/* 21/*
24 * The set of interrupts we want to allow when interrupts are nominally 22 * The set of interrupts we want to allow when interrupts are nominally
25 * disabled. The remainder are effectively "NMI" interrupts from 23 * disabled. The remainder are effectively "NMI" interrupts from
26 * the point of view of the generic Linux code. Note that synchronous 24 * the point of view of the generic Linux code. Note that synchronous
27 * interrupts (aka "non-queued") are not blocked by the mask in any case. 25 * interrupts (aka "non-queued") are not blocked by the mask in any case.
28 */ 26 */
29#if CHIP_HAS_AUX_PERF_COUNTERS()
30#define LINUX_MASKABLE_INTERRUPTS_HI \
31 (~(INT_MASK_HI(INT_PERF_COUNT) | INT_MASK_HI(INT_AUX_PERF_COUNT)))
32#else
33#define LINUX_MASKABLE_INTERRUPTS_HI \
34 (~(INT_MASK_HI(INT_PERF_COUNT)))
35#endif
36
37#else
38
39#if CHIP_HAS_AUX_PERF_COUNTERS()
40#define LINUX_MASKABLE_INTERRUPTS \
41 (~(INT_MASK(INT_PERF_COUNT) | INT_MASK(INT_AUX_PERF_COUNT)))
42#else
43#define LINUX_MASKABLE_INTERRUPTS \ 27#define LINUX_MASKABLE_INTERRUPTS \
44 (~(INT_MASK(INT_PERF_COUNT))) 28 (~((_AC(1,ULL) << INT_PERF_COUNT) | (_AC(1,ULL) << INT_AUX_PERF_COUNT)))
45#endif
46 29
30#if CHIP_HAS_SPLIT_INTR_MASK()
31/* The same macro, but for the two 32-bit SPRs separately. */
32#define LINUX_MASKABLE_INTERRUPTS_LO (-1)
33#define LINUX_MASKABLE_INTERRUPTS_HI \
34 (~((1 << (INT_PERF_COUNT - 32)) | (1 << (INT_AUX_PERF_COUNT - 32))))
47#endif 35#endif
48 36
49#ifndef __ASSEMBLY__ 37#ifndef __ASSEMBLY__
@@ -126,7 +114,7 @@
126 * to know our current state. 114 * to know our current state.
127 */ 115 */
128DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask); 116DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
129#define INITIAL_INTERRUPTS_ENABLED INT_MASK(INT_MEM_ERROR) 117#define INITIAL_INTERRUPTS_ENABLED (1ULL << INT_MEM_ERROR)
130 118
131/* Disable interrupts. */ 119/* Disable interrupts. */
132#define arch_local_irq_disable() \ 120#define arch_local_irq_disable() \
@@ -165,7 +153,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
165 153
166/* Prevent the given interrupt from being enabled next time we enable irqs. */ 154/* Prevent the given interrupt from being enabled next time we enable irqs. */
167#define arch_local_irq_mask(interrupt) \ 155#define arch_local_irq_mask(interrupt) \
168 (__get_cpu_var(interrupts_enabled_mask) &= ~INT_MASK(interrupt)) 156 (__get_cpu_var(interrupts_enabled_mask) &= ~(1ULL << (interrupt)))
169 157
170/* Prevent the given interrupt from being enabled immediately. */ 158/* Prevent the given interrupt from being enabled immediately. */
171#define arch_local_irq_mask_now(interrupt) do { \ 159#define arch_local_irq_mask_now(interrupt) do { \
@@ -175,7 +163,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
175 163
176/* Allow the given interrupt to be enabled next time we enable irqs. */ 164/* Allow the given interrupt to be enabled next time we enable irqs. */
177#define arch_local_irq_unmask(interrupt) \ 165#define arch_local_irq_unmask(interrupt) \
178 (__get_cpu_var(interrupts_enabled_mask) |= INT_MASK(interrupt)) 166 (__get_cpu_var(interrupts_enabled_mask) |= (1ULL << (interrupt)))
179 167
180/* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */ 168/* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */
181#define arch_local_irq_unmask_now(interrupt) do { \ 169#define arch_local_irq_unmask_now(interrupt) do { \
@@ -250,7 +238,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
250/* Disable interrupts. */ 238/* Disable interrupts. */
251#define IRQ_DISABLE(tmp0, tmp1) \ 239#define IRQ_DISABLE(tmp0, tmp1) \
252 { \ 240 { \
253 movei tmp0, -1; \ 241 movei tmp0, LINUX_MASKABLE_INTERRUPTS_LO; \
254 moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI) \ 242 moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI) \
255 }; \ 243 }; \
256 { \ 244 { \