arch/tile: enhance existing finv_buffer_remote() routine

It now takes an additional argument so it can be used to
flush-and-invalidate pages that are cached using hash-for-home
as well those that are cached with coherence point on a single cpu.

This allows it to be used more widely for changing the coherence
point of arbitrary pages when necessary.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>

1 files changed, 6 insertions, 49 deletions

diff --git a/arch/tile/include/asm/cacheflush.h b/arch/tile/include/asm/cacheflush.h
index 14a3f8556ace..12fb0fb330ee 100644
--- a/arch/tile/include/asm/cacheflush.h
+++ b/arch/tile/include/asm/cacheflush.h
@@ -138,55 +138,12 @@ static inline void finv_buffer(void *buffer, size_t size)
 }
 
 /*
- * Flush & invalidate a VA range that is homed remotely on a single core,
- * waiting until the memory controller holds the flushed values.
+ * Flush and invalidate a VA range that is homed remotely, waiting
+ * until the memory controller holds the flushed values.  If "hfh" is
+ * true, we will do a more expensive flush involving additional loads
+ * to make sure we have touched all the possible home cpus of a buffer
+ * that is homed with "hash for home".
  */
-static inline void finv_buffer_remote(void *buffer, size_t size)
-{
-        char *p;
-        int i;
-
-        /*
-         * Flush and invalidate the buffer out of the local L1/L2
-         * and request the home cache to flush and invalidate as well.
-         */
-        __finv_buffer(buffer, size);
-
-        /*
-         * Wait for the home cache to acknowledge that it has processed
-         * all the flush-and-invalidate requests.  This does not mean
-         * that the flushed data has reached the memory controller yet,
-         * but it does mean the home cache is processing the flushes.
-         */
-        __insn_mf();
-
-        /*
-         * Issue a load to the last cache line, which can't complete
-         * until all the previously-issued flushes to the same memory
-         * controller have also completed.  If we weren't striping
-         * memory, that one load would be sufficient, but since we may
-         * be, we also need to back up to the last load issued to
-         * another memory controller, which would be the point where
-         * we crossed an 8KB boundary (the granularity of striping
-         * across memory controllers).  Keep backing up and doing this
-         * until we are before the beginning of the buffer, or have
-         * hit all the controllers.
-         */
-        for (i = 0, p = (char *)buffer + size - 1;
-             i < (1 << CHIP_LOG_NUM_MSHIMS()) && p >= (char *)buffer;
-             ++i) {
-                const unsigned long STRIPE_WIDTH = 8192;
-
-                /* Force a load instruction to issue. */
-                *(volatile char *)p;
-
-                /* Jump to end of previous stripe. */
-                p -= STRIPE_WIDTH;
-                p = (char *)((unsigned long)p | (STRIPE_WIDTH - 1));
-        }
-
-        /* Wait for the loads (and thus flushes) to have completed. */
-        __insn_mf();
-}
+void finv_buffer_remote(void *buffer, size_t size, int hfh);
 
 #endif /* _ASM_TILE_CACHEFLUSH_H */