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authorChris Metcalf <cmetcalf@tilera.com>2013-08-01 11:36:42 -0400
committerDavid S. Miller <davem@davemloft.net>2013-08-01 17:35:50 -0400
commit2628e8af31a0ee4d28304d96a72fdf4d7822508c (patch)
tree384c3f522e5510d2706472545a6cbae387bbb803 /arch/tile/gxio
parent48f2a4e1e83992af6c721c6c93a6b012910e255f (diff)
tile: support jumbo frames in the tilegx network driver
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/tile/gxio')
-rw-r--r--arch/tile/gxio/iorpc_mpipe.c47
-rw-r--r--arch/tile/gxio/mpipe.c18
2 files changed, 62 insertions, 3 deletions
diff --git a/arch/tile/gxio/iorpc_mpipe.c b/arch/tile/gxio/iorpc_mpipe.c
index 31b87bf8c027..c2fb15167aee 100644
--- a/arch/tile/gxio/iorpc_mpipe.c
+++ b/arch/tile/gxio/iorpc_mpipe.c
@@ -387,6 +387,27 @@ int gxio_mpipe_link_close_aux(gxio_mpipe_context_t * context, int mac)
387 387
388EXPORT_SYMBOL(gxio_mpipe_link_close_aux); 388EXPORT_SYMBOL(gxio_mpipe_link_close_aux);
389 389
390struct link_set_attr_aux_param {
391 int mac;
392 uint32_t attr;
393 int64_t val;
394};
395
396int gxio_mpipe_link_set_attr_aux(gxio_mpipe_context_t * context, int mac,
397 uint32_t attr, int64_t val)
398{
399 struct link_set_attr_aux_param temp;
400 struct link_set_attr_aux_param *params = &temp;
401
402 params->mac = mac;
403 params->attr = attr;
404 params->val = val;
405
406 return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
407 sizeof(*params), GXIO_MPIPE_OP_LINK_SET_ATTR_AUX);
408}
409
410EXPORT_SYMBOL(gxio_mpipe_link_set_attr_aux);
390 411
391struct get_timestamp_aux_param { 412struct get_timestamp_aux_param {
392 uint64_t sec; 413 uint64_t sec;
@@ -454,6 +475,32 @@ int gxio_mpipe_adjust_timestamp_aux(gxio_mpipe_context_t * context,
454 475
455EXPORT_SYMBOL(gxio_mpipe_adjust_timestamp_aux); 476EXPORT_SYMBOL(gxio_mpipe_adjust_timestamp_aux);
456 477
478struct config_edma_ring_blks_param {
479 unsigned int ering;
480 unsigned int max_blks;
481 unsigned int min_snf_blks;
482 unsigned int db;
483};
484
485int gxio_mpipe_config_edma_ring_blks(gxio_mpipe_context_t * context,
486 unsigned int ering, unsigned int max_blks,
487 unsigned int min_snf_blks, unsigned int db)
488{
489 struct config_edma_ring_blks_param temp;
490 struct config_edma_ring_blks_param *params = &temp;
491
492 params->ering = ering;
493 params->max_blks = max_blks;
494 params->min_snf_blks = min_snf_blks;
495 params->db = db;
496
497 return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
498 sizeof(*params),
499 GXIO_MPIPE_OP_CONFIG_EDMA_RING_BLKS);
500}
501
502EXPORT_SYMBOL(gxio_mpipe_config_edma_ring_blks);
503
457struct arm_pollfd_param { 504struct arm_pollfd_param {
458 union iorpc_pollfd pollfd; 505 union iorpc_pollfd pollfd;
459}; 506};
diff --git a/arch/tile/gxio/mpipe.c b/arch/tile/gxio/mpipe.c
index e71c63390acc..0567cf0cd29e 100644
--- a/arch/tile/gxio/mpipe.c
+++ b/arch/tile/gxio/mpipe.c
@@ -383,7 +383,7 @@ EXPORT_SYMBOL_GPL(gxio_mpipe_iqueue_init);
383 383
384int gxio_mpipe_equeue_init(gxio_mpipe_equeue_t *equeue, 384int gxio_mpipe_equeue_init(gxio_mpipe_equeue_t *equeue,
385 gxio_mpipe_context_t *context, 385 gxio_mpipe_context_t *context,
386 unsigned int edma_ring_id, 386 unsigned int ering,
387 unsigned int channel, 387 unsigned int channel,
388 void *mem, unsigned int mem_size, 388 void *mem, unsigned int mem_size,
389 unsigned int mem_flags) 389 unsigned int mem_flags)
@@ -394,7 +394,7 @@ int gxio_mpipe_equeue_init(gxio_mpipe_equeue_t *equeue,
394 /* Offset used to read number of completed commands. */ 394 /* Offset used to read number of completed commands. */
395 MPIPE_EDMA_POST_REGION_ADDR_t offset; 395 MPIPE_EDMA_POST_REGION_ADDR_t offset;
396 396
397 int result = gxio_mpipe_init_edma_ring(context, edma_ring_id, channel, 397 int result = gxio_mpipe_init_edma_ring(context, ering, channel,
398 mem, mem_size, mem_flags); 398 mem, mem_size, mem_flags);
399 if (result < 0) 399 if (result < 0)
400 return result; 400 return result;
@@ -405,7 +405,7 @@ int gxio_mpipe_equeue_init(gxio_mpipe_equeue_t *equeue,
405 offset.region = 405 offset.region =
406 MPIPE_MMIO_ADDR__REGION_VAL_EDMA - 406 MPIPE_MMIO_ADDR__REGION_VAL_EDMA -
407 MPIPE_MMIO_ADDR__REGION_VAL_IDMA; 407 MPIPE_MMIO_ADDR__REGION_VAL_IDMA;
408 offset.ring = edma_ring_id; 408 offset.ring = ering;
409 409
410 __gxio_dma_queue_init(&equeue->dma_queue, 410 __gxio_dma_queue_init(&equeue->dma_queue,
411 context->mmio_fast_base + offset.word, 411 context->mmio_fast_base + offset.word,
@@ -413,6 +413,9 @@ int gxio_mpipe_equeue_init(gxio_mpipe_equeue_t *equeue,
413 equeue->edescs = mem; 413 equeue->edescs = mem;
414 equeue->mask_num_entries = num_entries - 1; 414 equeue->mask_num_entries = num_entries - 1;
415 equeue->log2_num_entries = __builtin_ctz(num_entries); 415 equeue->log2_num_entries = __builtin_ctz(num_entries);
416 equeue->context = context;
417 equeue->ering = ering;
418 equeue->channel = channel;
416 419
417 return 0; 420 return 0;
418} 421}
@@ -543,3 +546,12 @@ int gxio_mpipe_link_close(gxio_mpipe_link_t *link)
543} 546}
544 547
545EXPORT_SYMBOL_GPL(gxio_mpipe_link_close); 548EXPORT_SYMBOL_GPL(gxio_mpipe_link_close);
549
550int gxio_mpipe_link_set_attr(gxio_mpipe_link_t *link, uint32_t attr,
551 int64_t val)
552{
553 return gxio_mpipe_link_set_attr_aux(link->context, link->mac, attr,
554 val);
555}
556
557EXPORT_SYMBOL_GPL(gxio_mpipe_link_set_attr);