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authorDavid S. Miller <davem@davemloft.net>2006-06-29 18:07:37 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2006-06-29 19:37:38 -0400
commit2b1e59787198e75fb2ffb3bb4fb247da1c55ac12 (patch)
tree96d74048849b310135e0c79f663b16c52186caa5 /arch/sparc64
parentc3a8b85f5ac2c21f4ef75e87bfe55ee7a753ffcf (diff)
[SPARC64]: of_device layer IRQ resolution
Do IRQ determination generically by parsing the PROM properties, and using IRQ controller drivers for final resolution. One immediate positive effect is that all of the IRQ frobbing in the EBUS, ISA, and PCI controller layers has been eliminated. We just look up the of_device and use the properly computed value. The PCI controller irq_build() routines are gone and no longer used. Unfortunately sbus_build_irq() has to remain as there is a direct reference to this in the sunzilog driver. That can be killed off once the sparc32 side of this is written and the sunzilog driver is transformed into an "of" bus driver. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64')
-rw-r--r--arch/sparc64/kernel/ebus.c150
-rw-r--r--arch/sparc64/kernel/isa.c101
-rw-r--r--arch/sparc64/kernel/of_device.c194
-rw-r--r--arch/sparc64/kernel/pci.c6
-rw-r--r--arch/sparc64/kernel/pci_common.c291
-rw-r--r--arch/sparc64/kernel/pci_psycho.c161
-rw-r--r--arch/sparc64/kernel/pci_sabre.c158
-rw-r--r--arch/sparc64/kernel/pci_schizo.c311
-rw-r--r--arch/sparc64/kernel/pci_sun4v.c10
-rw-r--r--arch/sparc64/kernel/prom.c757
10 files changed, 1091 insertions, 1048 deletions
diff --git a/arch/sparc64/kernel/ebus.c b/arch/sparc64/kernel/ebus.c
index 98e0a8cbeecd..aac014d15ad3 100644
--- a/arch/sparc64/kernel/ebus.c
+++ b/arch/sparc64/kernel/ebus.c
@@ -20,6 +20,8 @@
20#include <asm/pbm.h> 20#include <asm/pbm.h>
21#include <asm/ebus.h> 21#include <asm/ebus.h>
22#include <asm/oplib.h> 22#include <asm/oplib.h>
23#include <asm/prom.h>
24#include <asm/of_device.h>
23#include <asm/bpp.h> 25#include <asm/bpp.h>
24#include <asm/irq.h> 26#include <asm/irq.h>
25 27
@@ -279,45 +281,12 @@ static inline void *ebus_alloc(size_t size)
279 return mem; 281 return mem;
280} 282}
281 283
282int __init ebus_intmap_match(struct linux_ebus *ebus, 284static void __init fill_ebus_child(struct device_node *dp,
283 struct linux_prom_registers *reg, 285 struct linux_ebus_child *dev,
284 int *interrupt) 286 int non_standard_regs)
285{
286 struct linux_prom_ebus_intmap *imap;
287 struct linux_prom_ebus_intmask *imask;
288 unsigned int hi, lo, irq;
289 int i, len, n_imap;
290
291 imap = of_get_property(ebus->prom_node, "interrupt-map", &len);
292 if (!imap)
293 return 0;
294 n_imap = len / sizeof(imap[0]);
295
296 imask = of_get_property(ebus->prom_node, "interrupt-map-mask", NULL);
297 if (!imask)
298 return 0;
299
300 hi = reg->which_io & imask->phys_hi;
301 lo = reg->phys_addr & imask->phys_lo;
302 irq = *interrupt & imask->interrupt;
303 for (i = 0; i < n_imap; i++) {
304 if ((imap[i].phys_hi == hi) &&
305 (imap[i].phys_lo == lo) &&
306 (imap[i].interrupt == irq)) {
307 *interrupt = imap[i].cinterrupt;
308 return 0;
309 }
310 }
311 return -1;
312}
313
314void __init fill_ebus_child(struct device_node *dp,
315 struct linux_prom_registers *preg,
316 struct linux_ebus_child *dev,
317 int non_standard_regs)
318{ 287{
288 struct of_device *op;
319 int *regs; 289 int *regs;
320 int *irqs;
321 int i, len; 290 int i, len;
322 291
323 dev->prom_node = dp; 292 dev->prom_node = dp;
@@ -354,12 +323,16 @@ void __init fill_ebus_child(struct device_node *dp,
354 } 323 }
355 } 324 }
356 325
357 for (i = 0; i < PROMINTR_MAX; i++) 326 op = of_find_device_by_node(dp);
358 dev->irqs[i] = PCI_IRQ_NONE; 327 if (!op) {
359
360 irqs = of_get_property(dp, "interrupts", &len);
361 if (!irqs) {
362 dev->num_irqs = 0; 328 dev->num_irqs = 0;
329 } else {
330 dev->num_irqs = op->num_irqs;
331 for (i = 0; i < dev->num_irqs; i++)
332 dev->irqs[i] = op->irqs[i];
333 }
334
335 if (!dev->num_irqs) {
363 /* 336 /*
364 * Oh, well, some PROMs don't export interrupts 337 * Oh, well, some PROMs don't export interrupts
365 * property to children of EBus devices... 338 * property to children of EBus devices...
@@ -375,23 +348,6 @@ void __init fill_ebus_child(struct device_node *dp,
375 dev->irqs[0] = dev->parent->irqs[1]; 348 dev->irqs[0] = dev->parent->irqs[1];
376 } 349 }
377 } 350 }
378 } else {
379 dev->num_irqs = len / sizeof(irqs[0]);
380 for (i = 0; i < dev->num_irqs; i++) {
381 struct pci_pbm_info *pbm = dev->bus->parent;
382 struct pci_controller_info *p = pbm->parent;
383
384 if (ebus_intmap_match(dev->bus, preg, &irqs[i]) != -1) {
385 dev->irqs[i] = p->irq_build(pbm,
386 dev->bus->self,
387 irqs[i]);
388 } else {
389 /* If we get a bogus interrupt property, just
390 * record the raw value instead of punting.
391 */
392 dev->irqs[i] = irqs[i];
393 }
394 }
395 } 351 }
396} 352}
397 353
@@ -403,72 +359,32 @@ static int __init child_regs_nonstandard(struct linux_ebus_device *dev)
403 return 0; 359 return 0;
404} 360}
405 361
406void __init fill_ebus_device(struct device_node *dp, struct linux_ebus_device *dev) 362static void __init fill_ebus_device(struct device_node *dp, struct linux_ebus_device *dev)
407{ 363{
408 struct linux_prom_registers *regs;
409 struct linux_ebus_child *child; 364 struct linux_ebus_child *child;
410 int *irqs; 365 struct of_device *op;
411 int i, n, len; 366 int i, len;
412 367
413 dev->prom_node = dp; 368 dev->prom_node = dp;
414 369
415 printk(" [%s", dp->name); 370 printk(" [%s", dp->name);
416 371
417 regs = of_get_property(dp, "reg", &len); 372 op = of_find_device_by_node(dp);
418 if (!regs) { 373 if (!op) {
419 dev->num_addrs = 0; 374 dev->num_addrs = 0;
420 goto probe_interrupts;
421 }
422
423 if (len % sizeof(struct linux_prom_registers)) {
424 prom_printf("UGH: proplen for %s was %d, need multiple of %d\n",
425 dev->prom_node->name, len,
426 (int)sizeof(struct linux_prom_registers));
427 prom_halt();
428 }
429 dev->num_addrs = len / sizeof(struct linux_prom_registers);
430
431 for (i = 0; i < dev->num_addrs; i++) {
432 /* XXX Learn how to interpret ebus ranges... -DaveM */
433 if (regs[i].which_io >= 0x10)
434 n = (regs[i].which_io - 0x10) >> 2;
435 else
436 n = regs[i].which_io;
437
438 dev->resource[i].start = dev->bus->self->resource[n].start;
439 dev->resource[i].start += (unsigned long)regs[i].phys_addr;
440 dev->resource[i].end =
441 (dev->resource[i].start + (unsigned long)regs[i].reg_size - 1UL);
442 dev->resource[i].flags = IORESOURCE_MEM;
443 dev->resource[i].name = dev->prom_node->name;
444 request_resource(&dev->bus->self->resource[n],
445 &dev->resource[i]);
446 }
447
448probe_interrupts:
449 for (i = 0; i < PROMINTR_MAX; i++)
450 dev->irqs[i] = PCI_IRQ_NONE;
451
452 irqs = of_get_property(dp, "interrupts", &len);
453 if (!irqs) {
454 dev->num_irqs = 0; 375 dev->num_irqs = 0;
455 } else { 376 } else {
456 dev->num_irqs = len / sizeof(irqs[0]); 377 (void) of_get_property(dp, "reg", &len);
457 for (i = 0; i < dev->num_irqs; i++) { 378 dev->num_addrs = len / sizeof(struct linux_prom_registers);
458 struct pci_pbm_info *pbm = dev->bus->parent; 379
459 struct pci_controller_info *p = pbm->parent; 380 for (i = 0; i < dev->num_addrs; i++)
460 381 memcpy(&dev->resource[i],
461 if (ebus_intmap_match(dev->bus, &regs[0], &irqs[i]) != -1) { 382 &op->resource[i],
462 dev->irqs[i] = p->irq_build(pbm, 383 sizeof(struct resource));
463 dev->bus->self, 384
464 irqs[i]); 385 dev->num_irqs = op->num_irqs;
465 } else { 386 for (i = 0; i < dev->num_irqs; i++)
466 /* If we get a bogus interrupt property, just 387 dev->irqs[i] = op->irqs[i];
467 * record the raw value instead of punting.
468 */
469 dev->irqs[i] = irqs[i];
470 }
471 }
472 } 388 }
473 389
474 dev->ofdev.node = dp; 390 dev->ofdev.node = dp;
@@ -490,7 +406,7 @@ probe_interrupts:
490 child->next = NULL; 406 child->next = NULL;
491 child->parent = dev; 407 child->parent = dev;
492 child->bus = dev->bus; 408 child->bus = dev->bus;
493 fill_ebus_child(dp, regs, child, 409 fill_ebus_child(dp, child,
494 child_regs_nonstandard(dev)); 410 child_regs_nonstandard(dev));
495 411
496 while ((dp = dp->sibling) != NULL) { 412 while ((dp = dp->sibling) != NULL) {
@@ -500,7 +416,7 @@ probe_interrupts:
500 child->next = NULL; 416 child->next = NULL;
501 child->parent = dev; 417 child->parent = dev;
502 child->bus = dev->bus; 418 child->bus = dev->bus;
503 fill_ebus_child(dp, regs, child, 419 fill_ebus_child(dp, child,
504 child_regs_nonstandard(dev)); 420 child_regs_nonstandard(dev));
505 } 421 }
506 } 422 }
diff --git a/arch/sparc64/kernel/isa.c b/arch/sparc64/kernel/isa.c
index 24c0dc34be31..0f3aec72ef5f 100644
--- a/arch/sparc64/kernel/isa.c
+++ b/arch/sparc64/kernel/isa.c
@@ -3,6 +3,8 @@
3#include <linux/pci.h> 3#include <linux/pci.h>
4#include <linux/slab.h> 4#include <linux/slab.h>
5#include <asm/oplib.h> 5#include <asm/oplib.h>
6#include <asm/prom.h>
7#include <asm/of_device.h>
6#include <asm/isa.h> 8#include <asm/isa.h>
7 9
8struct sparc_isa_bridge *isa_chain; 10struct sparc_isa_bridge *isa_chain;
@@ -46,107 +48,16 @@ isa_dev_get_resource(struct sparc_isa_device *isa_dev)
46 return pregs; 48 return pregs;
47} 49}
48 50
49/* I can't believe they didn't put a real INO in the isa device
50 * interrupts property. The whole point of the OBP properties
51 * is to shield the kernel from IRQ routing details.
52 *
53 * The P1275 standard for ISA devices seems to also have been
54 * totally ignored.
55 *
56 * On later systems, an interrupt-map and interrupt-map-mask scheme
57 * akin to EBUS is used.
58 */
59static struct {
60 int obp_irq;
61 int pci_ino;
62} grover_irq_table[] = {
63 { 1, 0x00 }, /* dma, unknown ino at this point */
64 { 2, 0x27 }, /* floppy */
65 { 3, 0x22 }, /* parallel */
66 { 4, 0x2b }, /* serial */
67 { 5, 0x25 }, /* acpi power management */
68
69 { 0, 0x00 } /* end of table */
70};
71
72static int __init isa_dev_get_irq_using_imap(struct sparc_isa_device *isa_dev,
73 struct sparc_isa_bridge *isa_br,
74 int *interrupt,
75 struct linux_prom_registers *reg)
76{
77 struct linux_prom_ebus_intmap *imap;
78 struct linux_prom_ebus_intmask *imask;
79 unsigned int hi, lo, irq;
80 int i, len, n_imap;
81
82 imap = of_get_property(isa_br->prom_node, "interrupt-map", &len);
83 if (!imap)
84 return 0;
85 n_imap = len / sizeof(imap[0]);
86
87 imask = of_get_property(isa_br->prom_node, "interrupt-map-mask", NULL);
88 if (!imask)
89 return 0;
90
91 hi = reg->which_io & imask->phys_hi;
92 lo = reg->phys_addr & imask->phys_lo;
93 irq = *interrupt & imask->interrupt;
94 for (i = 0; i < n_imap; i++) {
95 if ((imap[i].phys_hi == hi) &&
96 (imap[i].phys_lo == lo) &&
97 (imap[i].interrupt == irq)) {
98 *interrupt = imap[i].cinterrupt;
99 return 0;
100 }
101 }
102 return -1;
103}
104
105static void __init isa_dev_get_irq(struct sparc_isa_device *isa_dev, 51static void __init isa_dev_get_irq(struct sparc_isa_device *isa_dev,
106 struct linux_prom_registers *pregs) 52 struct linux_prom_registers *pregs)
107{ 53{
108 int irq_prop; 54 struct of_device *op = of_find_device_by_node(isa_dev->prom_node);
109 55
110 irq_prop = of_getintprop_default(isa_dev->prom_node, 56 if (!op || !op->num_irqs) {
111 "interrupts", -1); 57 isa_dev->irq = PCI_IRQ_NONE;
112 if (irq_prop <= 0) {
113 goto no_irq;
114 } else { 58 } else {
115 struct pci_controller_info *pcic; 59 isa_dev->irq = op->irqs[0];
116 struct pci_pbm_info *pbm;
117 int i;
118
119 if (of_find_property(isa_dev->bus->prom_node,
120 "interrupt-map", NULL)) {
121 if (!isa_dev_get_irq_using_imap(isa_dev,
122 isa_dev->bus,
123 &irq_prop,
124 pregs))
125 goto route_irq;
126 }
127
128 for (i = 0; grover_irq_table[i].obp_irq != 0; i++) {
129 if (grover_irq_table[i].obp_irq == irq_prop) {
130 int ino = grover_irq_table[i].pci_ino;
131
132 if (ino == 0)
133 goto no_irq;
134
135 irq_prop = ino;
136 goto route_irq;
137 }
138 }
139 goto no_irq;
140
141route_irq:
142 pbm = isa_dev->bus->parent;
143 pcic = pbm->parent;
144 isa_dev->irq = pcic->irq_build(pbm, NULL, irq_prop);
145 return;
146 } 60 }
147
148no_irq:
149 isa_dev->irq = PCI_IRQ_NONE;
150} 61}
151 62
152static void __init isa_fill_children(struct sparc_isa_device *parent_isa_dev) 63static void __init isa_fill_children(struct sparc_isa_device *parent_isa_dev)
diff --git a/arch/sparc64/kernel/of_device.c b/arch/sparc64/kernel/of_device.c
index 9812cfa6dd36..3670dc8a7d5f 100644
--- a/arch/sparc64/kernel/of_device.c
+++ b/arch/sparc64/kernel/of_device.c
@@ -146,6 +146,26 @@ void of_iounmap(void __iomem *base, unsigned long size)
146} 146}
147EXPORT_SYMBOL(of_iounmap); 147EXPORT_SYMBOL(of_iounmap);
148 148
149static int node_match(struct device *dev, void *data)
150{
151 struct of_device *op = to_of_device(dev);
152 struct device_node *dp = data;
153
154 return (op->node == dp);
155}
156
157struct of_device *of_find_device_by_node(struct device_node *dp)
158{
159 struct device *dev = bus_find_device(&of_bus_type, NULL,
160 dp, node_match);
161
162 if (dev)
163 return to_of_device(dev);
164
165 return NULL;
166}
167EXPORT_SYMBOL(of_find_device_by_node);
168
149#ifdef CONFIG_PCI 169#ifdef CONFIG_PCI
150struct bus_type isa_bus_type = { 170struct bus_type isa_bus_type = {
151 .name = "isa", 171 .name = "isa",
@@ -261,7 +281,6 @@ static unsigned int of_bus_default_get_flags(u32 *addr)
261 return IORESOURCE_MEM; 281 return IORESOURCE_MEM;
262} 282}
263 283
264
265/* 284/*
266 * PCI bus specific translator 285 * PCI bus specific translator
267 */ 286 */
@@ -594,12 +613,171 @@ static void __init build_device_resources(struct of_device *op,
594 } 613 }
595} 614}
596 615
616static struct device_node * __init
617apply_interrupt_map(struct device_node *dp, struct device_node *pp,
618 u32 *imap, int imlen, u32 *imask,
619 unsigned int *irq_p)
620{
621 struct device_node *cp;
622 unsigned int irq = *irq_p;
623 struct of_bus *bus;
624 phandle handle;
625 u32 *reg;
626 int na, num_reg, i;
627
628 bus = of_match_bus(pp);
629 bus->count_cells(dp, &na, NULL);
630
631 reg = of_get_property(dp, "reg", &num_reg);
632 if (!reg || !num_reg)
633 return NULL;
634
635 imlen /= ((na + 3) * 4);
636 handle = 0;
637 for (i = 0; i < imlen; i++) {
638 int j;
639
640 for (j = 0; j < na; j++) {
641 if ((reg[j] & imask[j]) != imap[j])
642 goto next;
643 }
644 if (imap[na] == irq) {
645 handle = imap[na + 1];
646 irq = imap[na + 2];
647 break;
648 }
649
650 next:
651 imap += (na + 3);
652 }
653 if (i == imlen)
654 return NULL;
655
656 *irq_p = irq;
657 cp = of_find_node_by_phandle(handle);
658
659 return cp;
660}
661
662static unsigned int __init pci_irq_swizzle(struct device_node *dp,
663 struct device_node *pp,
664 unsigned int irq)
665{
666 struct linux_prom_pci_registers *regs;
667 unsigned int devfn, slot, ret;
668
669 if (irq < 1 || irq > 4)
670 return irq;
671
672 regs = of_get_property(dp, "reg", NULL);
673 if (!regs)
674 return irq;
675
676 devfn = (regs->phys_hi >> 8) & 0xff;
677 slot = (devfn >> 3) & 0x1f;
678
679 ret = ((irq - 1 + (slot & 3)) & 3) + 1;
680
681 return ret;
682}
683
684static unsigned int __init build_one_device_irq(struct of_device *op,
685 struct device *parent,
686 unsigned int irq)
687{
688 struct device_node *dp = op->node;
689 struct device_node *pp, *ip;
690 unsigned int orig_irq = irq;
691
692 if (irq == 0xffffffff)
693 return irq;
694
695 if (dp->irq_trans) {
696 irq = dp->irq_trans->irq_build(dp, irq,
697 dp->irq_trans->data);
698#if 1
699 printk("%s: direct translate %x --> %x\n",
700 dp->full_name, orig_irq, irq);
701#endif
702 return irq;
703 }
704
705 /* Something more complicated. Walk up to the root, applying
706 * interrupt-map or bus specific translations, until we hit
707 * an IRQ translator.
708 *
709 * If we hit a bus type or situation we cannot handle, we
710 * stop and assume that the original IRQ number was in a
711 * format which has special meaning to it's immediate parent.
712 */
713 pp = dp->parent;
714 ip = NULL;
715 while (pp) {
716 void *imap, *imsk;
717 int imlen;
718
719 imap = of_get_property(pp, "interrupt-map", &imlen);
720 imsk = of_get_property(pp, "interrupt-map-mask", NULL);
721 if (imap && imsk) {
722 struct device_node *iret;
723 int this_orig_irq = irq;
724
725 iret = apply_interrupt_map(dp, pp,
726 imap, imlen, imsk,
727 &irq);
728#if 1
729 printk("%s: Apply [%s:%x] imap --> [%s:%x]\n",
730 op->node->full_name,
731 pp->full_name, this_orig_irq,
732 (iret ? iret->full_name : "NULL"), irq);
733#endif
734 if (!iret)
735 break;
736
737 if (iret->irq_trans) {
738 ip = iret;
739 break;
740 }
741 } else {
742 if (!strcmp(pp->type, "pci") ||
743 !strcmp(pp->type, "pciex")) {
744 unsigned int this_orig_irq = irq;
745
746 irq = pci_irq_swizzle(dp, pp, irq);
747#if 1
748 printk("%s: PCI swizzle [%s] %x --> %x\n",
749 op->node->full_name,
750 pp->full_name, this_orig_irq, irq);
751#endif
752 }
753
754 if (pp->irq_trans) {
755 ip = pp;
756 break;
757 }
758 }
759 dp = pp;
760 pp = pp->parent;
761 }
762 if (!ip)
763 return orig_irq;
764
765 irq = ip->irq_trans->irq_build(op->node, irq,
766 ip->irq_trans->data);
767#if 1
768 printk("%s: Apply IRQ trans [%s] %x --> %x\n",
769 op->node->full_name, ip->full_name, orig_irq, irq);
770#endif
771
772 return irq;
773}
774
597static struct of_device * __init scan_one_device(struct device_node *dp, 775static struct of_device * __init scan_one_device(struct device_node *dp,
598 struct device *parent) 776 struct device *parent)
599{ 777{
600 struct of_device *op = kzalloc(sizeof(*op), GFP_KERNEL); 778 struct of_device *op = kzalloc(sizeof(*op), GFP_KERNEL);
601 unsigned int *irq; 779 unsigned int *irq;
602 int len; 780 int len, i;
603 781
604 if (!op) 782 if (!op)
605 return NULL; 783 return NULL;
@@ -613,12 +791,16 @@ static struct of_device * __init scan_one_device(struct device_node *dp,
613 op->portid = of_getintprop_default(dp, "portid", -1); 791 op->portid = of_getintprop_default(dp, "portid", -1);
614 792
615 irq = of_get_property(dp, "interrupts", &len); 793 irq = of_get_property(dp, "interrupts", &len);
616 if (irq) 794 if (irq) {
617 op->irq = *irq; 795 memcpy(op->irqs, irq, len);
618 else 796 op->num_irqs = len / 4;
619 op->irq = 0xffffffff; 797 } else {
798 op->num_irqs = 0;
799 }
620 800
621 build_device_resources(op, parent); 801 build_device_resources(op, parent);
802 for (i = 0; i < op->num_irqs; i++)
803 op->irqs[i] = build_one_device_irq(op, parent, op->irqs[i]);
622 804
623 op->dev.parent = parent; 805 op->dev.parent = parent;
624 op->dev.bus = &of_bus_type; 806 op->dev.bus = &of_bus_type;
diff --git a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c
index 7b9625828603..04ea6c2eb7a1 100644
--- a/arch/sparc64/kernel/pci.c
+++ b/arch/sparc64/kernel/pci.c
@@ -404,14 +404,8 @@ void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
404} 404}
405EXPORT_SYMBOL(pcibios_bus_to_resource); 405EXPORT_SYMBOL(pcibios_bus_to_resource);
406 406
407extern int pci_irq_verbose;
408
409char * __init pcibios_setup(char *str) 407char * __init pcibios_setup(char *str)
410{ 408{
411 if (!strcmp(str, "irq_verbose")) {
412 pci_irq_verbose = 1;
413 return NULL;
414 }
415 return str; 409 return str;
416} 410}
417 411
diff --git a/arch/sparc64/kernel/pci_common.c b/arch/sparc64/kernel/pci_common.c
index b06a2955bf5f..7a59cc72c844 100644
--- a/arch/sparc64/kernel/pci_common.c
+++ b/arch/sparc64/kernel/pci_common.c
@@ -10,12 +10,10 @@
10 10
11#include <asm/pbm.h> 11#include <asm/pbm.h>
12#include <asm/prom.h> 12#include <asm/prom.h>
13#include <asm/of_device.h>
13 14
14#include "pci_impl.h" 15#include "pci_impl.h"
15 16
16/* Pass "pci=irq_verbose" on the kernel command line to enable this. */
17int pci_irq_verbose;
18
19/* Fix self device of BUS and hook it into BUS->self. 17/* Fix self device of BUS and hook it into BUS->self.
20 * The pci_scan_bus does not do this for the host bridge. 18 * The pci_scan_bus does not do this for the host bridge.
21 */ 19 */
@@ -169,6 +167,7 @@ static void __init pdev_cookie_fillin(struct pci_pbm_info *pbm,
169 } 167 }
170 pcp->pbm = pbm; 168 pcp->pbm = pbm;
171 pcp->prom_node = dp; 169 pcp->prom_node = dp;
170 pcp->op = of_find_device_by_node(dp);
172 memcpy(pcp->prom_regs, pregs, 171 memcpy(pcp->prom_regs, pregs,
173 nregs * sizeof(struct linux_prom_pci_registers)); 172 nregs * sizeof(struct linux_prom_pci_registers));
174 pcp->num_prom_regs = nregs; 173 pcp->num_prom_regs = nregs;
@@ -549,296 +548,18 @@ void __init pci_assign_unassigned(struct pci_pbm_info *pbm,
549 pci_assign_unassigned(pbm, bus); 548 pci_assign_unassigned(pbm, bus);
550} 549}
551 550
552static inline unsigned int pci_slot_swivel(struct pci_pbm_info *pbm,
553 struct pci_dev *toplevel_pdev,
554 struct pci_dev *pdev,
555 unsigned int interrupt)
556{
557 unsigned int ret;
558
559 if (unlikely(interrupt < 1 || interrupt > 4)) {
560 printk("%s: Device %s interrupt value of %u is strange.\n",
561 pbm->name, pci_name(pdev), interrupt);
562 return interrupt;
563 }
564
565 ret = ((interrupt - 1 + (PCI_SLOT(pdev->devfn) & 3)) & 3) + 1;
566
567 if (pci_irq_verbose)
568 printk("%s: %s IRQ Swivel %s [%x:%x] -> [%x]\n",
569 pbm->name, pci_name(toplevel_pdev), pci_name(pdev),
570 interrupt, PCI_SLOT(pdev->devfn), ret);
571
572 return ret;
573}
574
575static inline unsigned int pci_apply_intmap(struct pci_pbm_info *pbm,
576 struct pci_dev *toplevel_pdev,
577 struct pci_dev *pbus,
578 struct pci_dev *pdev,
579 unsigned int interrupt,
580 struct device_node **cnode)
581{
582 struct linux_prom_pci_intmap *imap;
583 struct linux_prom_pci_intmask *imask;
584 struct pcidev_cookie *pbus_pcp = pbus->sysdata;
585 struct pcidev_cookie *pdev_pcp = pdev->sysdata;
586 struct linux_prom_pci_registers *pregs = pdev_pcp->prom_regs;
587 struct property *prop;
588 int plen, num_imap, i;
589 unsigned int hi, mid, lo, irq, orig_interrupt;
590
591 *cnode = pbus_pcp->prom_node;
592
593 prop = of_find_property(pbus_pcp->prom_node, "interrupt-map", &plen);
594 if (!prop ||
595 (plen % sizeof(struct linux_prom_pci_intmap)) != 0) {
596 printk("%s: Device %s interrupt-map has bad len %d\n",
597 pbm->name, pci_name(pbus), plen);
598 goto no_intmap;
599 }
600 imap = prop->value;
601 num_imap = plen / sizeof(struct linux_prom_pci_intmap);
602
603 prop = of_find_property(pbus_pcp->prom_node, "interrupt-map-mask", &plen);
604 if (!prop ||
605 (plen % sizeof(struct linux_prom_pci_intmask)) != 0) {
606 printk("%s: Device %s interrupt-map-mask has bad len %d\n",
607 pbm->name, pci_name(pbus), plen);
608 goto no_intmap;
609 }
610 imask = prop->value;
611
612 orig_interrupt = interrupt;
613
614 hi = pregs->phys_hi & imask->phys_hi;
615 mid = pregs->phys_mid & imask->phys_mid;
616 lo = pregs->phys_lo & imask->phys_lo;
617 irq = interrupt & imask->interrupt;
618
619 for (i = 0; i < num_imap; i++) {
620 if (imap[i].phys_hi == hi &&
621 imap[i].phys_mid == mid &&
622 imap[i].phys_lo == lo &&
623 imap[i].interrupt == irq) {
624 *cnode = of_find_node_by_phandle(imap[i].cnode);
625 interrupt = imap[i].cinterrupt;
626 }
627 }
628
629 if (pci_irq_verbose)
630 printk("%s: %s MAP BUS %s DEV %s [%x] -> [%x]\n",
631 pbm->name, pci_name(toplevel_pdev),
632 pci_name(pbus), pci_name(pdev),
633 orig_interrupt, interrupt);
634
635no_intmap:
636 return interrupt;
637}
638
639/* For each PCI bus on the way to the root:
640 * 1) If it has an interrupt-map property, apply it.
641 * 2) Else, swivel the interrupt number based upon the PCI device number.
642 *
643 * Return the "IRQ controller" node. If this is the PBM's device node,
644 * all interrupt translations are complete, else we should use that node's
645 * "reg" property to apply the PBM's "interrupt-{map,mask}" to the interrupt.
646 */
647static struct device_node * __init
648pci_intmap_match_to_root(struct pci_pbm_info *pbm,
649 struct pci_dev *pdev,
650 unsigned int *interrupt)
651{
652 struct pci_dev *toplevel_pdev = pdev;
653 struct pcidev_cookie *toplevel_pcp = toplevel_pdev->sysdata;
654 struct device_node *cnode = toplevel_pcp->prom_node;
655
656 while (pdev->bus->number != pbm->pci_first_busno) {
657 struct pci_dev *pbus = pdev->bus->self;
658 struct pcidev_cookie *pcp = pbus->sysdata;
659 struct property *prop;
660
661 prop = of_find_property(pcp->prom_node, "interrupt-map", NULL);
662 if (!prop) {
663 *interrupt = pci_slot_swivel(pbm, toplevel_pdev,
664 pdev, *interrupt);
665 cnode = pcp->prom_node;
666 } else {
667 *interrupt = pci_apply_intmap(pbm, toplevel_pdev,
668 pbus, pdev,
669 *interrupt, &cnode);
670
671 while (pcp->prom_node != cnode &&
672 pbus->bus->number != pbm->pci_first_busno) {
673 pbus = pbus->bus->self;
674 pcp = pbus->sysdata;
675 }
676 }
677 pdev = pbus;
678
679 if (cnode == pbm->prom_node)
680 break;
681 }
682
683 return cnode;
684}
685
686static int __init pci_intmap_match(struct pci_dev *pdev, unsigned int *interrupt)
687{
688 struct pcidev_cookie *dev_pcp = pdev->sysdata;
689 struct pci_pbm_info *pbm = dev_pcp->pbm;
690 struct linux_prom_pci_registers *reg;
691 struct device_node *cnode;
692 struct property *prop;
693 unsigned int hi, mid, lo, irq;
694 int i, plen;
695
696 cnode = pci_intmap_match_to_root(pbm, pdev, interrupt);
697 if (cnode == pbm->prom_node)
698 goto success;
699
700 prop = of_find_property(cnode, "reg", &plen);
701 if (!prop ||
702 (plen % sizeof(struct linux_prom_pci_registers)) != 0) {
703 printk("%s: OBP node %s reg property has bad len %d\n",
704 pbm->name, cnode->full_name, plen);
705 goto fail;
706 }
707 reg = prop->value;
708
709 hi = reg[0].phys_hi & pbm->pbm_intmask->phys_hi;
710 mid = reg[0].phys_mid & pbm->pbm_intmask->phys_mid;
711 lo = reg[0].phys_lo & pbm->pbm_intmask->phys_lo;
712 irq = *interrupt & pbm->pbm_intmask->interrupt;
713
714 for (i = 0; i < pbm->num_pbm_intmap; i++) {
715 struct linux_prom_pci_intmap *intmap;
716
717 intmap = &pbm->pbm_intmap[i];
718
719 if (intmap->phys_hi == hi &&
720 intmap->phys_mid == mid &&
721 intmap->phys_lo == lo &&
722 intmap->interrupt == irq) {
723 *interrupt = intmap->cinterrupt;
724 goto success;
725 }
726 }
727
728fail:
729 return 0;
730
731success:
732 if (pci_irq_verbose)
733 printk("%s: Routing bus[%2x] slot[%2x] to INO[%02x]\n",
734 pbm->name,
735 pdev->bus->number, PCI_SLOT(pdev->devfn),
736 *interrupt);
737 return 1;
738}
739
740static void __init pdev_fixup_irq(struct pci_dev *pdev) 551static void __init pdev_fixup_irq(struct pci_dev *pdev)
741{ 552{
742 struct pcidev_cookie *pcp = pdev->sysdata; 553 struct pcidev_cookie *pcp = pdev->sysdata;
743 struct pci_pbm_info *pbm = pcp->pbm; 554 struct of_device *op = pcp->op;
744 struct pci_controller_info *p = pbm->parent;
745 unsigned int portid = pbm->portid;
746 unsigned int prom_irq;
747 struct device_node *dp = pcp->prom_node;
748 struct property *prop;
749
750 /* If this is an empty EBUS device, sometimes OBP fails to
751 * give it a valid fully specified interrupts property.
752 * The EBUS hooked up to SunHME on PCI I/O boards of
753 * Ex000 systems is one such case.
754 *
755 * The interrupt is not important so just ignore it.
756 */
757 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
758 pdev->device == PCI_DEVICE_ID_SUN_EBUS &&
759 !dp->child) {
760 pdev->irq = 0;
761 return;
762 }
763 555
764 prop = of_find_property(dp, "interrupts", NULL); 556 if (op->irqs[0] == 0xffffffff) {
765 if (!prop) { 557 pdev->irq = PCI_IRQ_NONE;
766 pdev->irq = 0;
767 return; 558 return;
768 } 559 }
769 prom_irq = *(unsigned int *) prop->value;
770
771 if (tlb_type != hypervisor) {
772 /* Fully specified already? */
773 if (((prom_irq & PCI_IRQ_IGN) >> 6) == portid) {
774 pdev->irq = p->irq_build(pbm, pdev, prom_irq);
775 goto have_irq;
776 }
777
778 /* An onboard device? (bit 5 set) */
779 if ((prom_irq & PCI_IRQ_INO) & 0x20) {
780 pdev->irq = p->irq_build(pbm, pdev, (portid << 6 | prom_irq));
781 goto have_irq;
782 }
783 }
784
785 /* Can we find a matching entry in the interrupt-map? */
786 if (pci_intmap_match(pdev, &prom_irq)) {
787 pdev->irq = p->irq_build(pbm, pdev, (portid << 6) | prom_irq);
788 goto have_irq;
789 }
790
791 /* Ok, we have to do it the hard way. */
792 {
793 unsigned int bus, slot, line;
794
795 bus = (pbm == &pbm->parent->pbm_B) ? (1 << 4) : 0;
796
797 /* If we have a legal interrupt property, use it as
798 * the IRQ line.
799 */
800 if (prom_irq > 0 && prom_irq < 5) {
801 line = ((prom_irq - 1) & 3);
802 } else {
803 u8 pci_irq_line;
804 560
805 /* Else just directly consult PCI config space. */ 561 pdev->irq = op->irqs[0];
806 pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pci_irq_line);
807 line = ((pci_irq_line - 1) & 3);
808 }
809
810 /* Now figure out the slot.
811 *
812 * Basically, device number zero on the top-level bus is
813 * always the PCI host controller. Slot 0 is then device 1.
814 * PBM A supports two external slots (0 and 1), and PBM B
815 * supports 4 external slots (0, 1, 2, and 3). On-board PCI
816 * devices are wired to device numbers outside of these
817 * ranges. -DaveM
818 */
819 if (pdev->bus->number == pbm->pci_first_busno) {
820 slot = PCI_SLOT(pdev->devfn) - pbm->pci_first_slot;
821 } else {
822 struct pci_dev *bus_dev;
823
824 /* Underneath a bridge, use slot number of parent
825 * bridge which is closest to the PBM.
826 */
827 bus_dev = pdev->bus->self;
828 while (bus_dev->bus &&
829 bus_dev->bus->number != pbm->pci_first_busno)
830 bus_dev = bus_dev->bus->self;
831
832 slot = PCI_SLOT(bus_dev->devfn) - pbm->pci_first_slot;
833 }
834 slot = slot << 2;
835
836 pdev->irq = p->irq_build(pbm, pdev,
837 ((portid << 6) & PCI_IRQ_IGN) |
838 (bus | slot | line));
839 }
840 562
841have_irq:
842 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 563 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE,
843 pdev->irq & PCI_IRQ_INO); 564 pdev->irq & PCI_IRQ_INO);
844} 565}
diff --git a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c
index 1cb63346f093..bf7b32b36705 100644
--- a/arch/sparc64/kernel/pci_psycho.c
+++ b/arch/sparc64/kernel/pci_psycho.c
@@ -18,6 +18,7 @@
18#include <asm/irq.h> 18#include <asm/irq.h>
19#include <asm/starfire.h> 19#include <asm/starfire.h>
20#include <asm/prom.h> 20#include <asm/prom.h>
21#include <asm/of_device.h>
21 22
22#include "pci_impl.h" 23#include "pci_impl.h"
23#include "iommu_common.h" 24#include "iommu_common.h"
@@ -208,110 +209,6 @@ static struct pci_ops psycho_ops = {
208 .write = psycho_write_pci_cfg, 209 .write = psycho_write_pci_cfg,
209}; 210};
210 211
211/* PSYCHO interrupt mapping support. */
212#define PSYCHO_IMAP_A_SLOT0 0x0c00UL
213#define PSYCHO_IMAP_B_SLOT0 0x0c20UL
214static unsigned long psycho_pcislot_imap_offset(unsigned long ino)
215{
216 unsigned int bus = (ino & 0x10) >> 4;
217 unsigned int slot = (ino & 0x0c) >> 2;
218
219 if (bus == 0)
220 return PSYCHO_IMAP_A_SLOT0 + (slot * 8);
221 else
222 return PSYCHO_IMAP_B_SLOT0 + (slot * 8);
223}
224
225#define PSYCHO_IMAP_SCSI 0x1000UL
226#define PSYCHO_IMAP_ETH 0x1008UL
227#define PSYCHO_IMAP_BPP 0x1010UL
228#define PSYCHO_IMAP_AU_REC 0x1018UL
229#define PSYCHO_IMAP_AU_PLAY 0x1020UL
230#define PSYCHO_IMAP_PFAIL 0x1028UL
231#define PSYCHO_IMAP_KMS 0x1030UL
232#define PSYCHO_IMAP_FLPY 0x1038UL
233#define PSYCHO_IMAP_SHW 0x1040UL
234#define PSYCHO_IMAP_KBD 0x1048UL
235#define PSYCHO_IMAP_MS 0x1050UL
236#define PSYCHO_IMAP_SER 0x1058UL
237#define PSYCHO_IMAP_TIM0 0x1060UL
238#define PSYCHO_IMAP_TIM1 0x1068UL
239#define PSYCHO_IMAP_UE 0x1070UL
240#define PSYCHO_IMAP_CE 0x1078UL
241#define PSYCHO_IMAP_A_ERR 0x1080UL
242#define PSYCHO_IMAP_B_ERR 0x1088UL
243#define PSYCHO_IMAP_PMGMT 0x1090UL
244#define PSYCHO_IMAP_GFX 0x1098UL
245#define PSYCHO_IMAP_EUPA 0x10a0UL
246
247static unsigned long __onboard_imap_off[] = {
248/*0x20*/ PSYCHO_IMAP_SCSI,
249/*0x21*/ PSYCHO_IMAP_ETH,
250/*0x22*/ PSYCHO_IMAP_BPP,
251/*0x23*/ PSYCHO_IMAP_AU_REC,
252/*0x24*/ PSYCHO_IMAP_AU_PLAY,
253/*0x25*/ PSYCHO_IMAP_PFAIL,
254/*0x26*/ PSYCHO_IMAP_KMS,
255/*0x27*/ PSYCHO_IMAP_FLPY,
256/*0x28*/ PSYCHO_IMAP_SHW,
257/*0x29*/ PSYCHO_IMAP_KBD,
258/*0x2a*/ PSYCHO_IMAP_MS,
259/*0x2b*/ PSYCHO_IMAP_SER,
260/*0x2c*/ PSYCHO_IMAP_TIM0,
261/*0x2d*/ PSYCHO_IMAP_TIM1,
262/*0x2e*/ PSYCHO_IMAP_UE,
263/*0x2f*/ PSYCHO_IMAP_CE,
264/*0x30*/ PSYCHO_IMAP_A_ERR,
265/*0x31*/ PSYCHO_IMAP_B_ERR,
266/*0x32*/ PSYCHO_IMAP_PMGMT
267};
268#define PSYCHO_ONBOARD_IRQ_BASE 0x20
269#define PSYCHO_ONBOARD_IRQ_LAST 0x32
270#define psycho_onboard_imap_offset(__ino) \
271 __onboard_imap_off[(__ino) - PSYCHO_ONBOARD_IRQ_BASE]
272
273#define PSYCHO_ICLR_A_SLOT0 0x1400UL
274#define PSYCHO_ICLR_SCSI 0x1800UL
275
276#define psycho_iclr_offset(ino) \
277 ((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
278 (PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
279
280static unsigned int psycho_irq_build(struct pci_pbm_info *pbm,
281 struct pci_dev *pdev,
282 unsigned int ino)
283{
284 unsigned long imap, iclr;
285 unsigned long imap_off, iclr_off;
286 int inofixup = 0;
287
288 ino &= PCI_IRQ_INO;
289 if (ino < PSYCHO_ONBOARD_IRQ_BASE) {
290 /* PCI slot */
291 imap_off = psycho_pcislot_imap_offset(ino);
292 } else {
293 /* Onboard device */
294 if (ino > PSYCHO_ONBOARD_IRQ_LAST) {
295 prom_printf("psycho_irq_build: Wacky INO [%x]\n", ino);
296 prom_halt();
297 }
298 imap_off = psycho_onboard_imap_offset(ino);
299 }
300
301 /* Now build the IRQ bucket. */
302 imap = pbm->controller_regs + imap_off;
303 imap += 4;
304
305 iclr_off = psycho_iclr_offset(ino);
306 iclr = pbm->controller_regs + iclr_off;
307 iclr += 4;
308
309 if ((ino & 0x20) == 0)
310 inofixup = ino & 0x03;
311
312 return build_irq(inofixup, iclr, imap);
313}
314
315/* PSYCHO error handling support. */ 212/* PSYCHO error handling support. */
316enum psycho_error_type { 213enum psycho_error_type {
317 UE_ERR, CE_ERR, PCI_ERR 214 UE_ERR, CE_ERR, PCI_ERR
@@ -944,51 +841,34 @@ static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id, struct pt_regs *reg
944#define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ 841#define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
945#define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */ 842#define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
946#define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ 843#define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
947#define PSYCHO_UE_INO 0x2e
948#define PSYCHO_CE_INO 0x2f
949#define PSYCHO_PCIERR_A_INO 0x30
950#define PSYCHO_PCIERR_B_INO 0x31
951static void psycho_register_error_handlers(struct pci_controller_info *p) 844static void psycho_register_error_handlers(struct pci_controller_info *p)
952{ 845{
953 struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */ 846 struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
847 struct of_device *op = of_find_device_by_node(pbm->prom_node);
954 unsigned long base = p->pbm_A.controller_regs; 848 unsigned long base = p->pbm_A.controller_regs;
955 unsigned int irq, portid = pbm->portid;
956 u64 tmp; 849 u64 tmp;
957 850
958 /* Build IRQs and register handlers. */ 851 if (!op)
959 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_UE_INO); 852 return;
960 if (request_irq(irq, psycho_ue_intr,
961 SA_SHIRQ, "PSYCHO UE", p) < 0) {
962 prom_printf("PSYCHO%d: Cannot register UE interrupt.\n",
963 p->index);
964 prom_halt();
965 }
966 853
967 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_CE_INO); 854 /* Psycho interrupt property order is:
968 if (request_irq(irq, psycho_ce_intr, 855 * 0: PCIERR PBM B INO
969 SA_SHIRQ, "PSYCHO CE", p) < 0) { 856 * 1: UE ERR
970 prom_printf("PSYCHO%d: Cannot register CE interrupt.\n", 857 * 2: CE ERR
971 p->index); 858 * 3: POWER FAIL
972 prom_halt(); 859 * 4: SPARE HARDWARE
973 } 860 * 5: PCIERR PBM A INO
861 */
974 862
975 pbm = &p->pbm_A; 863 if (op->num_irqs < 6)
976 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_PCIERR_A_INO); 864 return;
977 if (request_irq(irq, psycho_pcierr_intr,
978 SA_SHIRQ, "PSYCHO PCIERR", &p->pbm_A) < 0) {
979 prom_printf("PSYCHO%d(PBMA): Cannot register PciERR interrupt.\n",
980 p->index);
981 prom_halt();
982 }
983 865
984 pbm = &p->pbm_B; 866 request_irq(op->irqs[1], psycho_ue_intr, SA_SHIRQ, "PSYCHO UE", p);
985 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_PCIERR_B_INO); 867 request_irq(op->irqs[2], psycho_ce_intr, SA_SHIRQ, "PSYCHO CE", p);
986 if (request_irq(irq, psycho_pcierr_intr, 868 request_irq(op->irqs[5], psycho_pcierr_intr, SA_SHIRQ,
987 SA_SHIRQ, "PSYCHO PCIERR", &p->pbm_B) < 0) { 869 "PSYCHO PCIERR-A", &p->pbm_A);
988 prom_printf("PSYCHO%d(PBMB): Cannot register PciERR interrupt.\n", 870 request_irq(op->irqs[0], psycho_pcierr_intr, SA_SHIRQ,
989 p->index); 871 "PSYCHO PCIERR-B", &p->pbm_B);
990 prom_halt();
991 }
992 872
993 /* Enable UE and CE interrupts for controller. */ 873 /* Enable UE and CE interrupts for controller. */
994 psycho_write(base + PSYCHO_ECC_CTRL, 874 psycho_write(base + PSYCHO_ECC_CTRL,
@@ -1406,7 +1286,6 @@ void psycho_init(struct device_node *dp, char *model_name)
1406 p->index = pci_num_controllers++; 1286 p->index = pci_num_controllers++;
1407 p->pbms_same_domain = 0; 1287 p->pbms_same_domain = 0;
1408 p->scan_bus = psycho_scan_bus; 1288 p->scan_bus = psycho_scan_bus;
1409 p->irq_build = psycho_irq_build;
1410 p->base_address_update = psycho_base_address_update; 1289 p->base_address_update = psycho_base_address_update;
1411 p->resource_adjust = psycho_resource_adjust; 1290 p->resource_adjust = psycho_resource_adjust;
1412 p->pci_ops = &psycho_ops; 1291 p->pci_ops = &psycho_ops;
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
index 26f194ce4400..5e087b0fb4c9 100644
--- a/arch/sparc64/kernel/pci_sabre.c
+++ b/arch/sparc64/kernel/pci_sabre.c
@@ -485,114 +485,6 @@ static struct pci_ops sabre_ops = {
485 .write = sabre_write_pci_cfg, 485 .write = sabre_write_pci_cfg,
486}; 486};
487 487
488static unsigned long sabre_pcislot_imap_offset(unsigned long ino)
489{
490 unsigned int bus = (ino & 0x10) >> 4;
491 unsigned int slot = (ino & 0x0c) >> 2;
492
493 if (bus == 0)
494 return SABRE_IMAP_A_SLOT0 + (slot * 8);
495 else
496 return SABRE_IMAP_B_SLOT0 + (slot * 8);
497}
498
499static unsigned long __onboard_imap_off[] = {
500/*0x20*/ SABRE_IMAP_SCSI,
501/*0x21*/ SABRE_IMAP_ETH,
502/*0x22*/ SABRE_IMAP_BPP,
503/*0x23*/ SABRE_IMAP_AU_REC,
504/*0x24*/ SABRE_IMAP_AU_PLAY,
505/*0x25*/ SABRE_IMAP_PFAIL,
506/*0x26*/ SABRE_IMAP_KMS,
507/*0x27*/ SABRE_IMAP_FLPY,
508/*0x28*/ SABRE_IMAP_SHW,
509/*0x29*/ SABRE_IMAP_KBD,
510/*0x2a*/ SABRE_IMAP_MS,
511/*0x2b*/ SABRE_IMAP_SER,
512/*0x2c*/ 0 /* reserved */,
513/*0x2d*/ 0 /* reserved */,
514/*0x2e*/ SABRE_IMAP_UE,
515/*0x2f*/ SABRE_IMAP_CE,
516/*0x30*/ SABRE_IMAP_PCIERR,
517};
518#define SABRE_ONBOARD_IRQ_BASE 0x20
519#define SABRE_ONBOARD_IRQ_LAST 0x30
520#define sabre_onboard_imap_offset(__ino) \
521 __onboard_imap_off[(__ino) - SABRE_ONBOARD_IRQ_BASE]
522
523#define sabre_iclr_offset(ino) \
524 ((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
525 (SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
526
527/* When a device lives behind a bridge deeper in the PCI bus topology
528 * than APB, a special sequence must run to make sure all pending DMA
529 * transfers at the time of IRQ delivery are visible in the coherency
530 * domain by the cpu. This sequence is to perform a read on the far
531 * side of the non-APB bridge, then perform a read of Sabre's DMA
532 * write-sync register.
533 */
534static void sabre_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
535{
536 struct pci_dev *pdev = _arg1;
537 unsigned long sync_reg = (unsigned long) _arg2;
538 u16 _unused;
539
540 pci_read_config_word(pdev, PCI_VENDOR_ID, &_unused);
541 sabre_read(sync_reg);
542}
543
544static unsigned int sabre_irq_build(struct pci_pbm_info *pbm,
545 struct pci_dev *pdev,
546 unsigned int ino)
547{
548 unsigned long imap, iclr;
549 unsigned long imap_off, iclr_off;
550 int inofixup = 0;
551 int virt_irq;
552
553 ino &= PCI_IRQ_INO;
554 if (ino < SABRE_ONBOARD_IRQ_BASE) {
555 /* PCI slot */
556 imap_off = sabre_pcislot_imap_offset(ino);
557 } else {
558 /* onboard device */
559 if (ino > SABRE_ONBOARD_IRQ_LAST) {
560 prom_printf("sabre_irq_build: Wacky INO [%x]\n", ino);
561 prom_halt();
562 }
563 imap_off = sabre_onboard_imap_offset(ino);
564 }
565
566 /* Now build the IRQ bucket. */
567 imap = pbm->controller_regs + imap_off;
568 imap += 4;
569
570 iclr_off = sabre_iclr_offset(ino);
571 iclr = pbm->controller_regs + iclr_off;
572 iclr += 4;
573
574 if ((ino & 0x20) == 0)
575 inofixup = ino & 0x03;
576
577 virt_irq = build_irq(inofixup, iclr, imap);
578
579 if (pdev) {
580 struct pcidev_cookie *pcp = pdev->sysdata;
581
582 if (pdev->bus->number != pcp->pbm->pci_first_busno) {
583 struct pci_controller_info *p = pcp->pbm->parent;
584
585 irq_install_pre_handler(virt_irq,
586 sabre_wsync_handler,
587 pdev,
588 (void *)
589 p->pbm_A.controller_regs +
590 SABRE_WRSYNC);
591 }
592 }
593 return virt_irq;
594}
595
596/* SABRE error handling support. */ 488/* SABRE error handling support. */
597static void sabre_check_iommu_error(struct pci_controller_info *p, 489static void sabre_check_iommu_error(struct pci_controller_info *p,
598 unsigned long afsr, 490 unsigned long afsr,
@@ -929,17 +821,30 @@ static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs
929 return IRQ_HANDLED; 821 return IRQ_HANDLED;
930} 822}
931 823
932/* XXX What about PowerFail/PowerManagement??? -DaveM */
933#define SABRE_UE_INO 0x2e
934#define SABRE_CE_INO 0x2f
935#define SABRE_PCIERR_INO 0x30
936static void sabre_register_error_handlers(struct pci_controller_info *p) 824static void sabre_register_error_handlers(struct pci_controller_info *p)
937{ 825{
938 struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */ 826 struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
827 struct device_node *dp = pbm->prom_node;
828 struct of_device *op;
939 unsigned long base = pbm->controller_regs; 829 unsigned long base = pbm->controller_regs;
940 unsigned long irq, portid = pbm->portid;
941 u64 tmp; 830 u64 tmp;
942 831
832 if (pbm->chip_type == PBM_CHIP_TYPE_SABRE)
833 dp = dp->parent;
834
835 op = of_find_device_by_node(dp);
836 if (!op)
837 return;
838
839 /* Sabre/Hummingbird IRQ property layout is:
840 * 0: PCI ERR
841 * 1: UE ERR
842 * 2: CE ERR
843 * 3: POWER FAIL
844 */
845 if (op->num_irqs < 4)
846 return;
847
943 /* We clear the error bits in the appropriate AFSR before 848 /* We clear the error bits in the appropriate AFSR before
944 * registering the handler so that we don't get spurious 849 * registering the handler so that we don't get spurious
945 * interrupts. 850 * interrupts.
@@ -948,32 +853,16 @@ static void sabre_register_error_handlers(struct pci_controller_info *p)
948 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR | 853 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
949 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR | 854 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
950 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE)); 855 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE));
951 irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_UE_INO); 856
952 if (request_irq(irq, sabre_ue_intr, 857 request_irq(op->irqs[1], sabre_ue_intr, SA_SHIRQ, "SABRE UE", p);
953 SA_SHIRQ, "SABRE UE", p) < 0) {
954 prom_printf("SABRE%d: Cannot register UE interrupt.\n",
955 p->index);
956 prom_halt();
957 }
958 858
959 sabre_write(base + SABRE_CE_AFSR, 859 sabre_write(base + SABRE_CE_AFSR,
960 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR | 860 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
961 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR)); 861 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR));
962 irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_CE_INO);
963 if (request_irq(irq, sabre_ce_intr,
964 SA_SHIRQ, "SABRE CE", p) < 0) {
965 prom_printf("SABRE%d: Cannot register CE interrupt.\n",
966 p->index);
967 prom_halt();
968 }
969 862
970 irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_PCIERR_INO); 863 request_irq(op->irqs[2], sabre_ce_intr, SA_SHIRQ, "SABRE CE", p);
971 if (request_irq(irq, sabre_pcierr_intr, 864 request_irq(op->irqs[0], sabre_pcierr_intr, SA_SHIRQ,
972 SA_SHIRQ, "SABRE PCIERR", p) < 0) { 865 "SABRE PCIERR", p);
973 prom_printf("SABRE%d: Cannot register PciERR interrupt.\n",
974 p->index);
975 prom_halt();
976 }
977 866
978 tmp = sabre_read(base + SABRE_PCICTRL); 867 tmp = sabre_read(base + SABRE_PCICTRL);
979 tmp |= SABRE_PCICTRL_ERREN; 868 tmp |= SABRE_PCICTRL_ERREN;
@@ -1492,7 +1381,6 @@ void sabre_init(struct device_node *dp, char *model_name)
1492 p->index = pci_num_controllers++; 1381 p->index = pci_num_controllers++;
1493 p->pbms_same_domain = 1; 1382 p->pbms_same_domain = 1;
1494 p->scan_bus = sabre_scan_bus; 1383 p->scan_bus = sabre_scan_bus;
1495 p->irq_build = sabre_irq_build;
1496 p->base_address_update = sabre_base_address_update; 1384 p->base_address_update = sabre_base_address_update;
1497 p->resource_adjust = sabre_resource_adjust; 1385 p->resource_adjust = sabre_resource_adjust;
1498 p->pci_ops = &sabre_ops; 1386 p->pci_ops = &sabre_ops;
diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c
index f16449ccd7bc..5c6e2a9b91f8 100644
--- a/arch/sparc64/kernel/pci_schizo.c
+++ b/arch/sparc64/kernel/pci_schizo.c
@@ -217,116 +217,6 @@ static struct pci_ops schizo_ops = {
217 .write = schizo_write_pci_cfg, 217 .write = schizo_write_pci_cfg,
218}; 218};
219 219
220/* SCHIZO interrupt mapping support. Unlike Psycho, for this controller the
221 * imap/iclr registers are per-PBM.
222 */
223#define SCHIZO_IMAP_BASE 0x1000UL
224#define SCHIZO_ICLR_BASE 0x1400UL
225
226static unsigned long schizo_imap_offset(unsigned long ino)
227{
228 return SCHIZO_IMAP_BASE + (ino * 8UL);
229}
230
231static unsigned long schizo_iclr_offset(unsigned long ino)
232{
233 return SCHIZO_ICLR_BASE + (ino * 8UL);
234}
235
236static void tomatillo_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
237{
238 unsigned long sync_reg = (unsigned long) _arg2;
239 u64 mask = 1UL << (ino & IMAP_INO);
240 u64 val;
241 int limit;
242
243 schizo_write(sync_reg, mask);
244
245 limit = 100000;
246 val = 0;
247 while (--limit) {
248 val = schizo_read(sync_reg);
249 if (!(val & mask))
250 break;
251 }
252 if (limit <= 0) {
253 printk("tomatillo_wsync_handler: DMA won't sync [%lx:%lx]\n",
254 val, mask);
255 }
256
257 if (_arg1) {
258 static unsigned char cacheline[64]
259 __attribute__ ((aligned (64)));
260
261 __asm__ __volatile__("rd %%fprs, %0\n\t"
262 "or %0, %4, %1\n\t"
263 "wr %1, 0x0, %%fprs\n\t"
264 "stda %%f0, [%5] %6\n\t"
265 "wr %0, 0x0, %%fprs\n\t"
266 "membar #Sync"
267 : "=&r" (mask), "=&r" (val)
268 : "0" (mask), "1" (val),
269 "i" (FPRS_FEF), "r" (&cacheline[0]),
270 "i" (ASI_BLK_COMMIT_P));
271 }
272}
273
274static unsigned long schizo_ino_to_iclr(struct pci_pbm_info *pbm,
275 unsigned int ino)
276{
277 ino &= PCI_IRQ_INO;
278 return pbm->pbm_regs + schizo_iclr_offset(ino) + 4;
279}
280
281static unsigned long schizo_ino_to_imap(struct pci_pbm_info *pbm,
282 unsigned int ino)
283{
284 ino &= PCI_IRQ_INO;
285 return pbm->pbm_regs + schizo_imap_offset(ino) + 4;
286}
287
288static unsigned int schizo_irq_build(struct pci_pbm_info *pbm,
289 struct pci_dev *pdev,
290 unsigned int ino)
291{
292 unsigned long imap, iclr;
293 int ign_fixup;
294 int virt_irq;
295
296 ino &= PCI_IRQ_INO;
297
298 /* Now build the IRQ bucket. */
299 imap = schizo_ino_to_imap(pbm, ino);
300 iclr = schizo_ino_to_iclr(pbm, ino);
301
302 /* On Schizo, no inofixup occurs. This is because each
303 * INO has it's own IMAP register. On Psycho and Sabre
304 * there is only one IMAP register for each PCI slot even
305 * though four different INOs can be generated by each
306 * PCI slot.
307 *
308 * But, for JBUS variants (essentially, Tomatillo), we have
309 * to fixup the lowest bit of the interrupt group number.
310 */
311 ign_fixup = 0;
312 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
313 if (pbm->portid & 1)
314 ign_fixup = (1 << 6);
315 }
316
317 virt_irq = build_irq(ign_fixup, iclr, imap);
318
319 if (pdev && pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
320 irq_install_pre_handler(virt_irq,
321 tomatillo_wsync_handler,
322 ((pbm->chip_version <= 4) ?
323 (void *) 1 : (void *) 0),
324 (void *) pbm->sync_reg);
325 }
326
327 return virt_irq;
328}
329
330/* SCHIZO error handling support. */ 220/* SCHIZO error handling support. */
331enum schizo_error_type { 221enum schizo_error_type {
332 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR 222 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
@@ -362,34 +252,6 @@ struct pci_pbm_info *pbm_for_ino(struct pci_controller_info *p, u32 ino)
362 return &p->pbm_A; 252 return &p->pbm_A;
363} 253}
364 254
365static void schizo_clear_other_err_intr(struct pci_controller_info *p, int irq)
366{
367 struct pci_pbm_info *pbm;
368 unsigned long iclr;
369
370 /* Do not clear the interrupt for the other PCI bus.
371 *
372 * This "ACK both PBM IRQs" only needs to be performed
373 * for chip-wide error interrupts.
374 */
375 if ((irq & IMAP_INO) == SCHIZO_PCIERR_A_INO ||
376 (irq & IMAP_INO) == SCHIZO_PCIERR_B_INO)
377 return;
378
379 pbm = pbm_for_ino(p, irq);
380 if (pbm == &p->pbm_A)
381 pbm = &p->pbm_B;
382 else
383 pbm = &p->pbm_A;
384
385 schizo_irq_build(pbm, NULL,
386 (pbm->portid << 6) | (irq & IMAP_INO));
387
388 iclr = schizo_ino_to_iclr(pbm,
389 (pbm->portid << 6) | (irq & IMAP_INO));
390 upa_writel(ICLR_IDLE, iclr);
391}
392
393#define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */ 255#define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
394#define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */ 256#define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
395#define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */ 257#define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
@@ -720,8 +582,6 @@ static irqreturn_t schizo_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
720 /* Interrogate IOMMU for error status. */ 582 /* Interrogate IOMMU for error status. */
721 schizo_check_iommu_error(p, UE_ERR); 583 schizo_check_iommu_error(p, UE_ERR);
722 584
723 schizo_clear_other_err_intr(p, irq);
724
725 return IRQ_HANDLED; 585 return IRQ_HANDLED;
726} 586}
727 587
@@ -811,8 +671,6 @@ static irqreturn_t schizo_ce_intr(int irq, void *dev_id, struct pt_regs *regs)
811 printk("(none)"); 671 printk("(none)");
812 printk("]\n"); 672 printk("]\n");
813 673
814 schizo_clear_other_err_intr(p, irq);
815
816 return IRQ_HANDLED; 674 return IRQ_HANDLED;
817} 675}
818 676
@@ -1033,8 +891,6 @@ static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id, struct pt_regs *reg
1033 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR)) 891 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
1034 pci_scan_for_parity_error(p, pbm, pbm->pci_bus); 892 pci_scan_for_parity_error(p, pbm, pbm->pci_bus);
1035 893
1036 schizo_clear_other_err_intr(p, irq);
1037
1038 return IRQ_HANDLED; 894 return IRQ_HANDLED;
1039} 895}
1040 896
@@ -1090,7 +946,6 @@ static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id, struct pt_regs *
1090 printk("PCI%d: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n", 946 printk("PCI%d: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n",
1091 p->index, errlog); 947 p->index, errlog);
1092 948
1093 schizo_clear_other_err_intr(p, irq);
1094 return IRQ_HANDLED; 949 return IRQ_HANDLED;
1095 } 950 }
1096 951
@@ -1098,7 +953,6 @@ static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id, struct pt_regs *
1098 p->index); 953 p->index);
1099 schizo_check_iommu_error(p, SAFARI_ERR); 954 schizo_check_iommu_error(p, SAFARI_ERR);
1100 955
1101 schizo_clear_other_err_intr(p, irq);
1102 return IRQ_HANDLED; 956 return IRQ_HANDLED;
1103} 957}
1104 958
@@ -1130,74 +984,47 @@ static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id, struct pt_regs *
1130static void tomatillo_register_error_handlers(struct pci_controller_info *p) 984static void tomatillo_register_error_handlers(struct pci_controller_info *p)
1131{ 985{
1132 struct pci_pbm_info *pbm; 986 struct pci_pbm_info *pbm;
1133 unsigned int irq; 987 struct of_device *op;
1134 u64 tmp, err_mask, err_no_mask; 988 u64 tmp, err_mask, err_no_mask;
1135 989
1136 /* Build IRQs and register handlers. */ 990 /* Tomatillo IRQ property layout is:
991 * 0: PCIERR
992 * 1: UE ERR
993 * 2: CE ERR
994 * 3: SERR
995 * 4: POWER FAIL?
996 */
997
1137 pbm = pbm_for_ino(p, SCHIZO_UE_INO); 998 pbm = pbm_for_ino(p, SCHIZO_UE_INO);
1138 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_UE_INO); 999 op = of_find_device_by_node(pbm->prom_node);
1139 if (request_irq(irq, schizo_ue_intr, 1000 if (op)
1140 SA_SHIRQ, "TOMATILLO UE", p) < 0) { 1001 request_irq(op->irqs[1], schizo_ue_intr, SA_SHIRQ,
1141 prom_printf("%s: Cannot register UE interrupt.\n", 1002 "TOMATILLO_UE", p);
1142 pbm->name);
1143 prom_halt();
1144 }
1145 tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_UE_INO));
1146 upa_writel(tmp, (pbm->pbm_regs +
1147 schizo_imap_offset(SCHIZO_UE_INO) + 4));
1148 1003
1149 pbm = pbm_for_ino(p, SCHIZO_CE_INO); 1004 pbm = pbm_for_ino(p, SCHIZO_CE_INO);
1150 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_CE_INO); 1005 op = of_find_device_by_node(pbm->prom_node);
1151 if (request_irq(irq, schizo_ce_intr, 1006 if (op)
1152 SA_SHIRQ, "TOMATILLO CE", p) < 0) { 1007 request_irq(op->irqs[2], schizo_ce_intr, SA_SHIRQ,
1153 prom_printf("%s: Cannot register CE interrupt.\n", 1008 "TOMATILLO CE", p);
1154 pbm->name);
1155 prom_halt();
1156 }
1157 tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_CE_INO));
1158 upa_writel(tmp, (pbm->pbm_regs +
1159 schizo_imap_offset(SCHIZO_CE_INO) + 4));
1160 1009
1161 pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO); 1010 pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO);
1162 irq = schizo_irq_build(pbm, NULL, ((pbm->portid << 6) | 1011 op = of_find_device_by_node(pbm->prom_node);
1163 SCHIZO_PCIERR_A_INO)); 1012 if (op)
1164 if (request_irq(irq, schizo_pcierr_intr, 1013 request_irq(op->irqs[0], schizo_pcierr_intr, SA_SHIRQ,
1165 SA_SHIRQ, "TOMATILLO PCIERR", pbm) < 0) { 1014 "TOMATILLO PCIERR-A", pbm);
1166 prom_printf("%s: Cannot register PBM A PciERR interrupt.\n", 1015
1167 pbm->name);
1168 prom_halt();
1169 }
1170 tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) |
1171 SCHIZO_PCIERR_A_INO)));
1172 upa_writel(tmp, (pbm->pbm_regs +
1173 schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4));
1174 1016
1175 pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO); 1017 pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO);
1176 irq = schizo_irq_build(pbm, NULL, ((pbm->portid << 6) | 1018 op = of_find_device_by_node(pbm->prom_node);
1177 SCHIZO_PCIERR_B_INO)); 1019 if (op)
1178 if (request_irq(irq, schizo_pcierr_intr, 1020 request_irq(op->irqs[0], schizo_pcierr_intr, SA_SHIRQ,
1179 SA_SHIRQ, "TOMATILLO PCIERR", pbm) < 0) { 1021 "TOMATILLO PCIERR-B", pbm);
1180 prom_printf("%s: Cannot register PBM B PciERR interrupt.\n",
1181 pbm->name);
1182 prom_halt();
1183 }
1184 tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) |
1185 SCHIZO_PCIERR_B_INO)));
1186 upa_writel(tmp, (pbm->pbm_regs +
1187 schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4));
1188 1022
1189 pbm = pbm_for_ino(p, SCHIZO_SERR_INO); 1023 pbm = pbm_for_ino(p, SCHIZO_SERR_INO);
1190 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_SERR_INO); 1024 op = of_find_device_by_node(pbm->prom_node);
1191 if (request_irq(irq, schizo_safarierr_intr, 1025 if (op)
1192 SA_SHIRQ, "TOMATILLO SERR", p) < 0) { 1026 request_irq(op->irqs[3], schizo_safarierr_intr, SA_SHIRQ,
1193 prom_printf("%s: Cannot register SafariERR interrupt.\n", 1027 "TOMATILLO SERR", p);
1194 pbm->name);
1195 prom_halt();
1196 }
1197 tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) |
1198 SCHIZO_SERR_INO)));
1199 upa_writel(tmp, (pbm->pbm_regs +
1200 schizo_imap_offset(SCHIZO_SERR_INO) + 4));
1201 1028
1202 /* Enable UE and CE interrupts for controller. */ 1029 /* Enable UE and CE interrupts for controller. */
1203 schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL, 1030 schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL,
@@ -1265,64 +1092,47 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
1265static void schizo_register_error_handlers(struct pci_controller_info *p) 1092static void schizo_register_error_handlers(struct pci_controller_info *p)
1266{ 1093{
1267 struct pci_pbm_info *pbm; 1094 struct pci_pbm_info *pbm;
1268 unsigned int irq; 1095 struct of_device *op;
1269 u64 tmp, err_mask, err_no_mask; 1096 u64 tmp, err_mask, err_no_mask;
1270 1097
1271 /* Build IRQs and register handlers. */ 1098 /* Schizo IRQ property layout is:
1099 * 0: PCIERR
1100 * 1: UE ERR
1101 * 2: CE ERR
1102 * 3: SERR
1103 * 4: POWER FAIL?
1104 */
1105
1272 pbm = pbm_for_ino(p, SCHIZO_UE_INO); 1106 pbm = pbm_for_ino(p, SCHIZO_UE_INO);
1273 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_UE_INO); 1107 op = of_find_device_by_node(pbm->prom_node);
1274 if (request_irq(irq, schizo_ue_intr, 1108 if (op)
1275 SA_SHIRQ, "SCHIZO UE", p) < 0) { 1109 request_irq(op->irqs[1], schizo_ue_intr, SA_SHIRQ,
1276 prom_printf("%s: Cannot register UE interrupt.\n", 1110 "SCHIZO_UE", p);
1277 pbm->name);
1278 prom_halt();
1279 }
1280 tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_UE_INO));
1281 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_UE_INO) + 4));
1282 1111
1283 pbm = pbm_for_ino(p, SCHIZO_CE_INO); 1112 pbm = pbm_for_ino(p, SCHIZO_CE_INO);
1284 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_CE_INO); 1113 op = of_find_device_by_node(pbm->prom_node);
1285 if (request_irq(irq, schizo_ce_intr, 1114 if (op)
1286 SA_SHIRQ, "SCHIZO CE", p) < 0) { 1115 request_irq(op->irqs[2], schizo_ce_intr, SA_SHIRQ,
1287 prom_printf("%s: Cannot register CE interrupt.\n", 1116 "SCHIZO CE", p);
1288 pbm->name);
1289 prom_halt();
1290 }
1291 tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_CE_INO));
1292 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_CE_INO) + 4));
1293 1117
1294 pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO); 1118 pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO);
1295 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_PCIERR_A_INO); 1119 op = of_find_device_by_node(pbm->prom_node);
1296 if (request_irq(irq, schizo_pcierr_intr, 1120 if (op)
1297 SA_SHIRQ, "SCHIZO PCIERR", pbm) < 0) { 1121 request_irq(op->irqs[0], schizo_pcierr_intr, SA_SHIRQ,
1298 prom_printf("%s: Cannot register PBM A PciERR interrupt.\n", 1122 "SCHIZO PCIERR-A", pbm);
1299 pbm->name); 1123
1300 prom_halt();
1301 }
1302 tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_PCIERR_A_INO));
1303 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4));
1304 1124
1305 pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO); 1125 pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO);
1306 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_PCIERR_B_INO); 1126 op = of_find_device_by_node(pbm->prom_node);
1307 if (request_irq(irq, schizo_pcierr_intr, 1127 if (op)
1308 SA_SHIRQ, "SCHIZO PCIERR", &p->pbm_B) < 0) { 1128 request_irq(op->irqs[0], schizo_pcierr_intr, SA_SHIRQ,
1309 prom_printf("%s: Cannot register PBM B PciERR interrupt.\n", 1129 "SCHIZO PCIERR-B", pbm);
1310 pbm->name);
1311 prom_halt();
1312 }
1313 tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_PCIERR_B_INO));
1314 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4));
1315 1130
1316 pbm = pbm_for_ino(p, SCHIZO_SERR_INO); 1131 pbm = pbm_for_ino(p, SCHIZO_SERR_INO);
1317 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_SERR_INO); 1132 op = of_find_device_by_node(pbm->prom_node);
1318 if (request_irq(irq, schizo_safarierr_intr, 1133 if (op)
1319 SA_SHIRQ, "SCHIZO SERR", p) < 0) { 1134 request_irq(op->irqs[3], schizo_safarierr_intr, SA_SHIRQ,
1320 prom_printf("%s: Cannot register SafariERR interrupt.\n", 1135 "SCHIZO SERR", p);
1321 pbm->name);
1322 prom_halt();
1323 }
1324 tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_SERR_INO));
1325 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_SERR_INO) + 4));
1326 1136
1327 /* Enable UE and CE interrupts for controller. */ 1137 /* Enable UE and CE interrupts for controller. */
1328 schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL, 1138 schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL,
@@ -2022,7 +1832,6 @@ static void __schizo_init(struct device_node *dp, char *model_name, int chip_typ
2022 p->scan_bus = (chip_type == PBM_CHIP_TYPE_TOMATILLO ? 1832 p->scan_bus = (chip_type == PBM_CHIP_TYPE_TOMATILLO ?
2023 tomatillo_scan_bus : 1833 tomatillo_scan_bus :
2024 schizo_scan_bus); 1834 schizo_scan_bus);
2025 p->irq_build = schizo_irq_build;
2026 p->base_address_update = schizo_base_address_update; 1835 p->base_address_update = schizo_base_address_update;
2027 p->resource_adjust = schizo_resource_adjust; 1836 p->resource_adjust = schizo_resource_adjust;
2028 p->pci_ops = &schizo_ops; 1837 p->pci_ops = &schizo_ops;
diff --git a/arch/sparc64/kernel/pci_sun4v.c b/arch/sparc64/kernel/pci_sun4v.c
index b69e2270a721..03ad4c06758e 100644
--- a/arch/sparc64/kernel/pci_sun4v.c
+++ b/arch/sparc64/kernel/pci_sun4v.c
@@ -843,15 +843,6 @@ static void pci_sun4v_scan_bus(struct pci_controller_info *p)
843 /* XXX register error interrupt handlers XXX */ 843 /* XXX register error interrupt handlers XXX */
844} 844}
845 845
846static unsigned int pci_sun4v_irq_build(struct pci_pbm_info *pbm,
847 struct pci_dev *pdev,
848 unsigned int devino)
849{
850 u32 devhandle = pbm->devhandle;
851
852 return sun4v_build_irq(devhandle, devino);
853}
854
855static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource) 846static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
856{ 847{
857 struct pcidev_cookie *pcp = pdev->sysdata; 848 struct pcidev_cookie *pcp = pdev->sysdata;
@@ -1200,7 +1191,6 @@ void sun4v_pci_init(struct device_node *dp, char *model_name)
1200 p->pbms_same_domain = 0; 1191 p->pbms_same_domain = 0;
1201 1192
1202 p->scan_bus = pci_sun4v_scan_bus; 1193 p->scan_bus = pci_sun4v_scan_bus;
1203 p->irq_build = pci_sun4v_irq_build;
1204 p->base_address_update = pci_sun4v_base_address_update; 1194 p->base_address_update = pci_sun4v_base_address_update;
1205 p->resource_adjust = pci_sun4v_resource_adjust; 1195 p->resource_adjust = pci_sun4v_resource_adjust;
1206 p->pci_ops = &pci_sun4v_ops; 1196 p->pci_ops = &pci_sun4v_ops;
diff --git a/arch/sparc64/kernel/prom.c b/arch/sparc64/kernel/prom.c
index 6aa856a18157..8a70c52c0447 100644
--- a/arch/sparc64/kernel/prom.c
+++ b/arch/sparc64/kernel/prom.c
@@ -15,6 +15,7 @@
15 * 2 of the License, or (at your option) any later version. 15 * 2 of the License, or (at your option) any later version.
16 */ 16 */
17 17
18#include <linux/config.h>
18#include <linux/kernel.h> 19#include <linux/kernel.h>
19#include <linux/types.h> 20#include <linux/types.h>
20#include <linux/string.h> 21#include <linux/string.h>
@@ -23,7 +24,11 @@
23#include <linux/module.h> 24#include <linux/module.h>
24 25
25#include <asm/prom.h> 26#include <asm/prom.h>
27#include <asm/of_device.h>
26#include <asm/oplib.h> 28#include <asm/oplib.h>
29#include <asm/irq.h>
30#include <asm/asi.h>
31#include <asm/upa.h>
27 32
28static struct device_node *allnodes; 33static struct device_node *allnodes;
29 34
@@ -283,6 +288,754 @@ static void * __init prom_early_alloc(unsigned long size)
283 return ret; 288 return ret;
284} 289}
285 290
291#ifdef CONFIG_PCI
292/* PSYCHO interrupt mapping support. */
293#define PSYCHO_IMAP_A_SLOT0 0x0c00UL
294#define PSYCHO_IMAP_B_SLOT0 0x0c20UL
295static unsigned long psycho_pcislot_imap_offset(unsigned long ino)
296{
297 unsigned int bus = (ino & 0x10) >> 4;
298 unsigned int slot = (ino & 0x0c) >> 2;
299
300 if (bus == 0)
301 return PSYCHO_IMAP_A_SLOT0 + (slot * 8);
302 else
303 return PSYCHO_IMAP_B_SLOT0 + (slot * 8);
304}
305
306#define PSYCHO_IMAP_SCSI 0x1000UL
307#define PSYCHO_IMAP_ETH 0x1008UL
308#define PSYCHO_IMAP_BPP 0x1010UL
309#define PSYCHO_IMAP_AU_REC 0x1018UL
310#define PSYCHO_IMAP_AU_PLAY 0x1020UL
311#define PSYCHO_IMAP_PFAIL 0x1028UL
312#define PSYCHO_IMAP_KMS 0x1030UL
313#define PSYCHO_IMAP_FLPY 0x1038UL
314#define PSYCHO_IMAP_SHW 0x1040UL
315#define PSYCHO_IMAP_KBD 0x1048UL
316#define PSYCHO_IMAP_MS 0x1050UL
317#define PSYCHO_IMAP_SER 0x1058UL
318#define PSYCHO_IMAP_TIM0 0x1060UL
319#define PSYCHO_IMAP_TIM1 0x1068UL
320#define PSYCHO_IMAP_UE 0x1070UL
321#define PSYCHO_IMAP_CE 0x1078UL
322#define PSYCHO_IMAP_A_ERR 0x1080UL
323#define PSYCHO_IMAP_B_ERR 0x1088UL
324#define PSYCHO_IMAP_PMGMT 0x1090UL
325#define PSYCHO_IMAP_GFX 0x1098UL
326#define PSYCHO_IMAP_EUPA 0x10a0UL
327
328static unsigned long __psycho_onboard_imap_off[] = {
329/*0x20*/ PSYCHO_IMAP_SCSI,
330/*0x21*/ PSYCHO_IMAP_ETH,
331/*0x22*/ PSYCHO_IMAP_BPP,
332/*0x23*/ PSYCHO_IMAP_AU_REC,
333/*0x24*/ PSYCHO_IMAP_AU_PLAY,
334/*0x25*/ PSYCHO_IMAP_PFAIL,
335/*0x26*/ PSYCHO_IMAP_KMS,
336/*0x27*/ PSYCHO_IMAP_FLPY,
337/*0x28*/ PSYCHO_IMAP_SHW,
338/*0x29*/ PSYCHO_IMAP_KBD,
339/*0x2a*/ PSYCHO_IMAP_MS,
340/*0x2b*/ PSYCHO_IMAP_SER,
341/*0x2c*/ PSYCHO_IMAP_TIM0,
342/*0x2d*/ PSYCHO_IMAP_TIM1,
343/*0x2e*/ PSYCHO_IMAP_UE,
344/*0x2f*/ PSYCHO_IMAP_CE,
345/*0x30*/ PSYCHO_IMAP_A_ERR,
346/*0x31*/ PSYCHO_IMAP_B_ERR,
347/*0x32*/ PSYCHO_IMAP_PMGMT
348};
349#define PSYCHO_ONBOARD_IRQ_BASE 0x20
350#define PSYCHO_ONBOARD_IRQ_LAST 0x32
351#define psycho_onboard_imap_offset(__ino) \
352 __psycho_onboard_imap_off[(__ino) - PSYCHO_ONBOARD_IRQ_BASE]
353
354#define PSYCHO_ICLR_A_SLOT0 0x1400UL
355#define PSYCHO_ICLR_SCSI 0x1800UL
356
357#define psycho_iclr_offset(ino) \
358 ((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
359 (PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
360
361static unsigned int psycho_irq_build(struct device_node *dp,
362 unsigned int ino,
363 void *_data)
364{
365 unsigned long controller_regs = (unsigned long) _data;
366 unsigned long imap, iclr;
367 unsigned long imap_off, iclr_off;
368 int inofixup = 0;
369
370 ino &= 0x3f;
371 if (ino < PSYCHO_ONBOARD_IRQ_BASE) {
372 /* PCI slot */
373 imap_off = psycho_pcislot_imap_offset(ino);
374 } else {
375 /* Onboard device */
376 if (ino > PSYCHO_ONBOARD_IRQ_LAST) {
377 prom_printf("psycho_irq_build: Wacky INO [%x]\n", ino);
378 prom_halt();
379 }
380 imap_off = psycho_onboard_imap_offset(ino);
381 }
382
383 /* Now build the IRQ bucket. */
384 imap = controller_regs + imap_off;
385 imap += 4;
386
387 iclr_off = psycho_iclr_offset(ino);
388 iclr = controller_regs + iclr_off;
389 iclr += 4;
390
391 if ((ino & 0x20) == 0)
392 inofixup = ino & 0x03;
393
394 return build_irq(inofixup, iclr, imap);
395}
396
397static void psycho_irq_trans_init(struct device_node *dp)
398{
399 struct linux_prom64_registers *regs;
400
401 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
402 dp->irq_trans->irq_build = psycho_irq_build;
403
404 regs = of_get_property(dp, "reg", NULL);
405 dp->irq_trans->data = (void *) regs[2].phys_addr;
406}
407
408#define sabre_read(__reg) \
409({ u64 __ret; \
410 __asm__ __volatile__("ldxa [%1] %2, %0" \
411 : "=r" (__ret) \
412 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
413 : "memory"); \
414 __ret; \
415})
416
417struct sabre_irq_data {
418 unsigned long controller_regs;
419 unsigned int pci_first_busno;
420};
421#define SABRE_CONFIGSPACE 0x001000000UL
422#define SABRE_WRSYNC 0x1c20UL
423
424#define SABRE_CONFIG_BASE(CONFIG_SPACE) \
425 (CONFIG_SPACE | (1UL << 24))
426#define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
427 (((unsigned long)(BUS) << 16) | \
428 ((unsigned long)(DEVFN) << 8) | \
429 ((unsigned long)(REG)))
430
431/* When a device lives behind a bridge deeper in the PCI bus topology
432 * than APB, a special sequence must run to make sure all pending DMA
433 * transfers at the time of IRQ delivery are visible in the coherency
434 * domain by the cpu. This sequence is to perform a read on the far
435 * side of the non-APB bridge, then perform a read of Sabre's DMA
436 * write-sync register.
437 */
438static void sabre_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
439{
440 unsigned int phys_hi = (unsigned int) (unsigned long) _arg1;
441 struct sabre_irq_data *irq_data = _arg2;
442 unsigned long controller_regs = irq_data->controller_regs;
443 unsigned long sync_reg = controller_regs + SABRE_WRSYNC;
444 unsigned long config_space = controller_regs + SABRE_CONFIGSPACE;
445 unsigned int bus, devfn;
446 u16 _unused;
447
448 config_space = SABRE_CONFIG_BASE(config_space);
449
450 bus = (phys_hi >> 16) & 0xff;
451 devfn = (phys_hi >> 8) & 0xff;
452
453 config_space |= SABRE_CONFIG_ENCODE(bus, devfn, 0x00);
454
455 __asm__ __volatile__("membar #Sync\n\t"
456 "lduha [%1] %2, %0\n\t"
457 "membar #Sync"
458 : "=r" (_unused)
459 : "r" ((u16 *) config_space),
460 "i" (ASI_PHYS_BYPASS_EC_E_L)
461 : "memory");
462
463 sabre_read(sync_reg);
464}
465
466#define SABRE_IMAP_A_SLOT0 0x0c00UL
467#define SABRE_IMAP_B_SLOT0 0x0c20UL
468#define SABRE_IMAP_SCSI 0x1000UL
469#define SABRE_IMAP_ETH 0x1008UL
470#define SABRE_IMAP_BPP 0x1010UL
471#define SABRE_IMAP_AU_REC 0x1018UL
472#define SABRE_IMAP_AU_PLAY 0x1020UL
473#define SABRE_IMAP_PFAIL 0x1028UL
474#define SABRE_IMAP_KMS 0x1030UL
475#define SABRE_IMAP_FLPY 0x1038UL
476#define SABRE_IMAP_SHW 0x1040UL
477#define SABRE_IMAP_KBD 0x1048UL
478#define SABRE_IMAP_MS 0x1050UL
479#define SABRE_IMAP_SER 0x1058UL
480#define SABRE_IMAP_UE 0x1070UL
481#define SABRE_IMAP_CE 0x1078UL
482#define SABRE_IMAP_PCIERR 0x1080UL
483#define SABRE_IMAP_GFX 0x1098UL
484#define SABRE_IMAP_EUPA 0x10a0UL
485#define SABRE_ICLR_A_SLOT0 0x1400UL
486#define SABRE_ICLR_B_SLOT0 0x1480UL
487#define SABRE_ICLR_SCSI 0x1800UL
488#define SABRE_ICLR_ETH 0x1808UL
489#define SABRE_ICLR_BPP 0x1810UL
490#define SABRE_ICLR_AU_REC 0x1818UL
491#define SABRE_ICLR_AU_PLAY 0x1820UL
492#define SABRE_ICLR_PFAIL 0x1828UL
493#define SABRE_ICLR_KMS 0x1830UL
494#define SABRE_ICLR_FLPY 0x1838UL
495#define SABRE_ICLR_SHW 0x1840UL
496#define SABRE_ICLR_KBD 0x1848UL
497#define SABRE_ICLR_MS 0x1850UL
498#define SABRE_ICLR_SER 0x1858UL
499#define SABRE_ICLR_UE 0x1870UL
500#define SABRE_ICLR_CE 0x1878UL
501#define SABRE_ICLR_PCIERR 0x1880UL
502
503static unsigned long sabre_pcislot_imap_offset(unsigned long ino)
504{
505 unsigned int bus = (ino & 0x10) >> 4;
506 unsigned int slot = (ino & 0x0c) >> 2;
507
508 if (bus == 0)
509 return SABRE_IMAP_A_SLOT0 + (slot * 8);
510 else
511 return SABRE_IMAP_B_SLOT0 + (slot * 8);
512}
513
514static unsigned long __sabre_onboard_imap_off[] = {
515/*0x20*/ SABRE_IMAP_SCSI,
516/*0x21*/ SABRE_IMAP_ETH,
517/*0x22*/ SABRE_IMAP_BPP,
518/*0x23*/ SABRE_IMAP_AU_REC,
519/*0x24*/ SABRE_IMAP_AU_PLAY,
520/*0x25*/ SABRE_IMAP_PFAIL,
521/*0x26*/ SABRE_IMAP_KMS,
522/*0x27*/ SABRE_IMAP_FLPY,
523/*0x28*/ SABRE_IMAP_SHW,
524/*0x29*/ SABRE_IMAP_KBD,
525/*0x2a*/ SABRE_IMAP_MS,
526/*0x2b*/ SABRE_IMAP_SER,
527/*0x2c*/ 0 /* reserved */,
528/*0x2d*/ 0 /* reserved */,
529/*0x2e*/ SABRE_IMAP_UE,
530/*0x2f*/ SABRE_IMAP_CE,
531/*0x30*/ SABRE_IMAP_PCIERR,
532};
533#define SABRE_ONBOARD_IRQ_BASE 0x20
534#define SABRE_ONBOARD_IRQ_LAST 0x30
535#define sabre_onboard_imap_offset(__ino) \
536 __sabre_onboard_imap_off[(__ino) - SABRE_ONBOARD_IRQ_BASE]
537
538#define sabre_iclr_offset(ino) \
539 ((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
540 (SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
541
542static unsigned int sabre_irq_build(struct device_node *dp,
543 unsigned int ino,
544 void *_data)
545{
546 struct sabre_irq_data *irq_data = _data;
547 unsigned long controller_regs = irq_data->controller_regs;
548 struct linux_prom_pci_registers *regs;
549 unsigned long imap, iclr;
550 unsigned long imap_off, iclr_off;
551 int inofixup = 0;
552 int virt_irq;
553
554 ino &= 0x3f;
555 if (ino < SABRE_ONBOARD_IRQ_BASE) {
556 /* PCI slot */
557 imap_off = sabre_pcislot_imap_offset(ino);
558 } else {
559 /* onboard device */
560 if (ino > SABRE_ONBOARD_IRQ_LAST) {
561 prom_printf("sabre_irq_build: Wacky INO [%x]\n", ino);
562 prom_halt();
563 }
564 imap_off = sabre_onboard_imap_offset(ino);
565 }
566
567 /* Now build the IRQ bucket. */
568 imap = controller_regs + imap_off;
569 imap += 4;
570
571 iclr_off = sabre_iclr_offset(ino);
572 iclr = controller_regs + iclr_off;
573 iclr += 4;
574
575 if ((ino & 0x20) == 0)
576 inofixup = ino & 0x03;
577
578 virt_irq = build_irq(inofixup, iclr, imap);
579
580 regs = of_get_property(dp, "reg", NULL);
581 if (regs &&
582 ((regs->phys_hi >> 16) & 0xff) != irq_data->pci_first_busno) {
583 irq_install_pre_handler(virt_irq,
584 sabre_wsync_handler,
585 (void *) (long) regs->phys_hi,
586 (void *)
587 controller_regs +
588 SABRE_WRSYNC);
589 }
590
591 return virt_irq;
592}
593
594static void sabre_irq_trans_init(struct device_node *dp)
595{
596 struct linux_prom64_registers *regs;
597 struct sabre_irq_data *irq_data;
598 u32 *busrange;
599
600 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
601 dp->irq_trans->irq_build = sabre_irq_build;
602
603 irq_data = prom_early_alloc(sizeof(struct sabre_irq_data));
604
605 regs = of_get_property(dp, "reg", NULL);
606 irq_data->controller_regs = regs[0].phys_addr;
607
608 busrange = of_get_property(dp, "bus-range", NULL);
609 irq_data->pci_first_busno = busrange[0];
610
611 dp->irq_trans->data = irq_data;
612}
613
614/* SCHIZO interrupt mapping support. Unlike Psycho, for this controller the
615 * imap/iclr registers are per-PBM.
616 */
617#define SCHIZO_IMAP_BASE 0x1000UL
618#define SCHIZO_ICLR_BASE 0x1400UL
619
620static unsigned long schizo_imap_offset(unsigned long ino)
621{
622 return SCHIZO_IMAP_BASE + (ino * 8UL);
623}
624
625static unsigned long schizo_iclr_offset(unsigned long ino)
626{
627 return SCHIZO_ICLR_BASE + (ino * 8UL);
628}
629
630static unsigned long schizo_ino_to_iclr(unsigned long pbm_regs,
631 unsigned int ino)
632{
633 return pbm_regs + schizo_iclr_offset(ino) + 4;
634}
635
636static unsigned long schizo_ino_to_imap(unsigned long pbm_regs,
637 unsigned int ino)
638{
639 return pbm_regs + schizo_imap_offset(ino) + 4;
640}
641
642#define schizo_read(__reg) \
643({ u64 __ret; \
644 __asm__ __volatile__("ldxa [%1] %2, %0" \
645 : "=r" (__ret) \
646 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
647 : "memory"); \
648 __ret; \
649})
650#define schizo_write(__reg, __val) \
651 __asm__ __volatile__("stxa %0, [%1] %2" \
652 : /* no outputs */ \
653 : "r" (__val), "r" (__reg), \
654 "i" (ASI_PHYS_BYPASS_EC_E) \
655 : "memory")
656
657static void tomatillo_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
658{
659 unsigned long sync_reg = (unsigned long) _arg2;
660 u64 mask = 1UL << (ino & IMAP_INO);
661 u64 val;
662 int limit;
663
664 schizo_write(sync_reg, mask);
665
666 limit = 100000;
667 val = 0;
668 while (--limit) {
669 val = schizo_read(sync_reg);
670 if (!(val & mask))
671 break;
672 }
673 if (limit <= 0) {
674 printk("tomatillo_wsync_handler: DMA won't sync [%lx:%lx]\n",
675 val, mask);
676 }
677
678 if (_arg1) {
679 static unsigned char cacheline[64]
680 __attribute__ ((aligned (64)));
681
682 __asm__ __volatile__("rd %%fprs, %0\n\t"
683 "or %0, %4, %1\n\t"
684 "wr %1, 0x0, %%fprs\n\t"
685 "stda %%f0, [%5] %6\n\t"
686 "wr %0, 0x0, %%fprs\n\t"
687 "membar #Sync"
688 : "=&r" (mask), "=&r" (val)
689 : "0" (mask), "1" (val),
690 "i" (FPRS_FEF), "r" (&cacheline[0]),
691 "i" (ASI_BLK_COMMIT_P));
692 }
693}
694
695struct schizo_irq_data {
696 unsigned long pbm_regs;
697 unsigned long sync_reg;
698 u32 portid;
699 int chip_version;
700};
701
702static unsigned int schizo_irq_build(struct device_node *dp,
703 unsigned int ino,
704 void *_data)
705{
706 struct schizo_irq_data *irq_data = _data;
707 unsigned long pbm_regs = irq_data->pbm_regs;
708 unsigned long imap, iclr;
709 int ign_fixup;
710 int virt_irq;
711 int is_tomatillo;
712
713 ino &= 0x3f;
714
715 /* Now build the IRQ bucket. */
716 imap = schizo_ino_to_imap(pbm_regs, ino);
717 iclr = schizo_ino_to_iclr(pbm_regs, ino);
718
719 /* On Schizo, no inofixup occurs. This is because each
720 * INO has it's own IMAP register. On Psycho and Sabre
721 * there is only one IMAP register for each PCI slot even
722 * though four different INOs can be generated by each
723 * PCI slot.
724 *
725 * But, for JBUS variants (essentially, Tomatillo), we have
726 * to fixup the lowest bit of the interrupt group number.
727 */
728 ign_fixup = 0;
729
730 is_tomatillo = (irq_data->sync_reg != 0UL);
731
732 if (is_tomatillo) {
733 if (irq_data->portid & 1)
734 ign_fixup = (1 << 6);
735 }
736
737 virt_irq = build_irq(ign_fixup, iclr, imap);
738
739 if (is_tomatillo) {
740 irq_install_pre_handler(virt_irq,
741 tomatillo_wsync_handler,
742 ((irq_data->chip_version <= 4) ?
743 (void *) 1 : (void *) 0),
744 (void *) irq_data->sync_reg);
745 }
746
747 return virt_irq;
748}
749
750static void schizo_irq_trans_init(struct device_node *dp)
751{
752 struct linux_prom64_registers *regs;
753 struct schizo_irq_data *irq_data;
754
755 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
756 dp->irq_trans->irq_build = schizo_irq_build;
757
758 irq_data = prom_early_alloc(sizeof(struct schizo_irq_data));
759
760 regs = of_get_property(dp, "reg", NULL);
761 dp->irq_trans->data = irq_data;
762
763 irq_data->pbm_regs = regs[0].phys_addr;
764 irq_data->sync_reg = regs[3].phys_addr + 0x1a18UL;
765 irq_data->portid = of_getintprop_default(dp, "portid", 0);
766 irq_data->chip_version = of_getintprop_default(dp, "version#", 0);
767}
768
769static unsigned int pci_sun4v_irq_build(struct device_node *dp,
770 unsigned int devino,
771 void *_data)
772{
773 u32 devhandle = (u32) (unsigned long) _data;
774
775 return sun4v_build_irq(devhandle, devino);
776}
777
778static void pci_sun4v_irq_trans_init(struct device_node *dp)
779{
780 struct linux_prom64_registers *regs;
781
782 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
783 dp->irq_trans->irq_build = pci_sun4v_irq_build;
784
785 regs = of_get_property(dp, "reg", NULL);
786 dp->irq_trans->data = (void *) (unsigned long)
787 ((regs->phys_addr >> 32UL) & 0x0fffffff);
788}
789#endif /* CONFIG_PCI */
790
791#ifdef CONFIG_SBUS
792/* INO number to IMAP register offset for SYSIO external IRQ's.
793 * This should conform to both Sunfire/Wildfire server and Fusion
794 * desktop designs.
795 */
796#define SYSIO_IMAP_SLOT0 0x2c04UL
797#define SYSIO_IMAP_SLOT1 0x2c0cUL
798#define SYSIO_IMAP_SLOT2 0x2c14UL
799#define SYSIO_IMAP_SLOT3 0x2c1cUL
800#define SYSIO_IMAP_SCSI 0x3004UL
801#define SYSIO_IMAP_ETH 0x300cUL
802#define SYSIO_IMAP_BPP 0x3014UL
803#define SYSIO_IMAP_AUDIO 0x301cUL
804#define SYSIO_IMAP_PFAIL 0x3024UL
805#define SYSIO_IMAP_KMS 0x302cUL
806#define SYSIO_IMAP_FLPY 0x3034UL
807#define SYSIO_IMAP_SHW 0x303cUL
808#define SYSIO_IMAP_KBD 0x3044UL
809#define SYSIO_IMAP_MS 0x304cUL
810#define SYSIO_IMAP_SER 0x3054UL
811#define SYSIO_IMAP_TIM0 0x3064UL
812#define SYSIO_IMAP_TIM1 0x306cUL
813#define SYSIO_IMAP_UE 0x3074UL
814#define SYSIO_IMAP_CE 0x307cUL
815#define SYSIO_IMAP_SBERR 0x3084UL
816#define SYSIO_IMAP_PMGMT 0x308cUL
817#define SYSIO_IMAP_GFX 0x3094UL
818#define SYSIO_IMAP_EUPA 0x309cUL
819
820#define bogon ((unsigned long) -1)
821static unsigned long sysio_irq_offsets[] = {
822 /* SBUS Slot 0 --> 3, level 1 --> 7 */
823 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
824 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
825 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
826 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
827 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
828 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
829 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
830 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
831
832 /* Onboard devices (not relevant/used on SunFire). */
833 SYSIO_IMAP_SCSI,
834 SYSIO_IMAP_ETH,
835 SYSIO_IMAP_BPP,
836 bogon,
837 SYSIO_IMAP_AUDIO,
838 SYSIO_IMAP_PFAIL,
839 bogon,
840 bogon,
841 SYSIO_IMAP_KMS,
842 SYSIO_IMAP_FLPY,
843 SYSIO_IMAP_SHW,
844 SYSIO_IMAP_KBD,
845 SYSIO_IMAP_MS,
846 SYSIO_IMAP_SER,
847 bogon,
848 bogon,
849 SYSIO_IMAP_TIM0,
850 SYSIO_IMAP_TIM1,
851 bogon,
852 bogon,
853 SYSIO_IMAP_UE,
854 SYSIO_IMAP_CE,
855 SYSIO_IMAP_SBERR,
856 SYSIO_IMAP_PMGMT,
857};
858
859#undef bogon
860
861#define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
862
863/* Convert Interrupt Mapping register pointer to associated
864 * Interrupt Clear register pointer, SYSIO specific version.
865 */
866#define SYSIO_ICLR_UNUSED0 0x3400UL
867#define SYSIO_ICLR_SLOT0 0x340cUL
868#define SYSIO_ICLR_SLOT1 0x344cUL
869#define SYSIO_ICLR_SLOT2 0x348cUL
870#define SYSIO_ICLR_SLOT3 0x34ccUL
871static unsigned long sysio_imap_to_iclr(unsigned long imap)
872{
873 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
874 return imap + diff;
875}
876
877static unsigned int sbus_of_build_irq(struct device_node *dp,
878 unsigned int ino,
879 void *_data)
880{
881 unsigned long reg_base = (unsigned long) _data;
882 struct linux_prom_registers *regs;
883 unsigned long imap, iclr;
884 int sbus_slot = 0;
885 int sbus_level = 0;
886
887 ino &= 0x3f;
888
889 regs = of_get_property(dp, "reg", NULL);
890 if (regs)
891 sbus_slot = regs->which_io;
892
893 if (ino < 0x20)
894 ino += (sbus_slot * 8);
895
896 imap = sysio_irq_offsets[ino];
897 if (imap == ((unsigned long)-1)) {
898 prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
899 ino);
900 prom_halt();
901 }
902 imap += reg_base;
903
904 /* SYSIO inconsistency. For external SLOTS, we have to select
905 * the right ICLR register based upon the lower SBUS irq level
906 * bits.
907 */
908 if (ino >= 0x20) {
909 iclr = sysio_imap_to_iclr(imap);
910 } else {
911 sbus_level = ino & 0x7;
912
913 switch(sbus_slot) {
914 case 0:
915 iclr = reg_base + SYSIO_ICLR_SLOT0;
916 break;
917 case 1:
918 iclr = reg_base + SYSIO_ICLR_SLOT1;
919 break;
920 case 2:
921 iclr = reg_base + SYSIO_ICLR_SLOT2;
922 break;
923 default:
924 case 3:
925 iclr = reg_base + SYSIO_ICLR_SLOT3;
926 break;
927 };
928
929 iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
930 }
931 return build_irq(sbus_level, iclr, imap);
932}
933
934static void sbus_irq_trans_init(struct device_node *dp)
935{
936 struct linux_prom64_registers *regs;
937
938 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
939 dp->irq_trans->irq_build = sbus_of_build_irq;
940
941 regs = of_get_property(dp, "reg", NULL);
942 dp->irq_trans->data = (void *) (unsigned long) regs->phys_addr;
943}
944#endif /* CONFIG_SBUS */
945
946
947static unsigned int central_build_irq(struct device_node *dp,
948 unsigned int ino,
949 void *_data)
950{
951 struct device_node *central_dp = _data;
952 struct of_device *central_op = of_find_device_by_node(central_dp);
953 struct resource *res;
954 unsigned long imap, iclr;
955 u32 tmp;
956
957 if (!strcmp(dp->name, "eeprom")) {
958 res = &central_op->resource[5];
959 } else if (!strcmp(dp->name, "zs")) {
960 res = &central_op->resource[4];
961 } else if (!strcmp(dp->name, "clock-board")) {
962 res = &central_op->resource[3];
963 } else {
964 return ino;
965 }
966
967 imap = res->start + 0x00UL;
968 iclr = res->start + 0x10UL;
969
970 /* Set the INO state to idle, and disable. */
971 upa_writel(0, iclr);
972 upa_readl(iclr);
973
974 tmp = upa_readl(imap);
975 tmp &= ~0x80000000;
976 upa_writel(tmp, imap);
977
978 return build_irq(0, iclr, imap);
979}
980
981static void central_irq_trans_init(struct device_node *dp)
982{
983 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
984 dp->irq_trans->irq_build = central_build_irq;
985
986 dp->irq_trans->data = dp;
987}
988
989struct irq_trans {
990 const char *name;
991 void (*init)(struct device_node *);
992};
993
994#ifdef CONFIG_PCI
995static struct irq_trans pci_irq_trans_table[] = {
996 { "SUNW,sabre", sabre_irq_trans_init },
997 { "pci108e,a000", sabre_irq_trans_init },
998 { "pci108e,a001", sabre_irq_trans_init },
999 { "SUNW,psycho", psycho_irq_trans_init },
1000 { "pci108e,8000", psycho_irq_trans_init },
1001 { "SUNW,schizo", schizo_irq_trans_init },
1002 { "pci108e,8001", schizo_irq_trans_init },
1003 { "SUNW,schizo+", schizo_irq_trans_init },
1004 { "pci108e,8002", schizo_irq_trans_init },
1005 { "SUNW,tomatillo", schizo_irq_trans_init },
1006 { "pci108e,a801", schizo_irq_trans_init },
1007 { "SUNW,sun4v-pci", pci_sun4v_irq_trans_init },
1008};
1009#endif
1010
1011static void irq_trans_init(struct device_node *dp)
1012{
1013 const char *model;
1014 int i;
1015
1016 model = of_get_property(dp, "model", NULL);
1017 if (!model)
1018 model = of_get_property(dp, "compatible", NULL);
1019 if (!model)
1020 return;
1021
1022#ifdef CONFIG_PCI
1023 for (i = 0; i < ARRAY_SIZE(pci_irq_trans_table); i++) {
1024 struct irq_trans *t = &pci_irq_trans_table[i];
1025
1026 if (!strcmp(model, t->name))
1027 return t->init(dp);
1028 }
1029#endif
1030#ifdef CONFIG_SBUS
1031 if (!strcmp(dp->name, "sbus") ||
1032 !strcmp(dp->name, "sbi"))
1033 return sbus_irq_trans_init(dp);
1034#endif
1035 if (!strcmp(dp->name, "central"))
1036 return central_irq_trans_init(dp->child);
1037}
1038
286static int is_root_node(const struct device_node *dp) 1039static int is_root_node(const struct device_node *dp)
287{ 1040{
288 if (!dp) 1041 if (!dp)
@@ -706,10 +1459,10 @@ static struct device_node * __init create_node(phandle node)
706 dp->type = get_one_property(node, "device_type"); 1459 dp->type = get_one_property(node, "device_type");
707 dp->node = node; 1460 dp->node = node;
708 1461
709 /* Build interrupts later... */
710
711 dp->properties = build_prop_list(node); 1462 dp->properties = build_prop_list(node);
712 1463
1464 irq_trans_init(dp);
1465
713 return dp; 1466 return dp;
714} 1467}
715 1468
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 10:56:38 -0400