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authorDavid S. Miller <davem@sunset.davemloft.net>2007-05-27 23:24:47 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-05-29 05:50:15 -0400
commit679292993c77c06f7ade4e317c13256b92c2651b (patch)
tree9cff8cc7b9ad2f100e9fa1cda25de6c976c1c45e /arch/sparc64
parentb00ccd0f0b3fe8776aead63ec96313e84451b337 (diff)
[SPARC64]: Fix _PAGE_EXEC_4U check in sun4u I-TLB miss handler.
It was using an immediate _PAGE_EXEC_4U value in an 'and' instruction to perform the test. This doesn't work because the immediate field is signed 13-bit, this the mask being tested against the PTE was 0x1000 sign-extended to 32-bits instead of just plain 0x1000. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64')
-rw-r--r--arch/sparc64/kernel/itlb_miss.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/sparc64/kernel/itlb_miss.S b/arch/sparc64/kernel/itlb_miss.S
index ad46e2024f4b..5a8377b54955 100644
--- a/arch/sparc64/kernel/itlb_miss.S
+++ b/arch/sparc64/kernel/itlb_miss.S
@@ -11,12 +11,12 @@
11/* ITLB ** ICACHE line 2: TSB compare and TLB load */ 11/* ITLB ** ICACHE line 2: TSB compare and TLB load */
12 bne,pn %xcc, tsb_miss_itlb ! Miss 12 bne,pn %xcc, tsb_miss_itlb ! Miss
13 mov FAULT_CODE_ITLB, %g3 13 mov FAULT_CODE_ITLB, %g3
14 andcc %g5, _PAGE_EXEC_4U, %g0 ! Executable? 14 sethi %hi(_PAGE_EXEC_4U), %g4
15 andcc %g5, %g4, %g0 ! Executable?
15 be,pn %xcc, tsb_do_fault 16 be,pn %xcc, tsb_do_fault
16 nop ! Delay slot, fill me 17 nop ! Delay slot, fill me
17 stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load TLB 18 stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load TLB
18 retry ! Trap done 19 retry ! Trap done
19 nop
20 20
21/* ITLB ** ICACHE line 3: */ 21/* ITLB ** ICACHE line 3: */
22 nop 22 nop