aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sparc64
diff options
context:
space:
mode:
authorJeff Garzik <jgarzik@pobox.com>2005-10-11 01:48:37 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-10-11 01:48:37 -0400
commit1a04392bd6439876b1552793389cbb5be356ea54 (patch)
tree12af7b77e3b0848127f2d2871778c9c1f315578a /arch/sparc64
parent68399bb5080c1d96f2110b0a040b39d3ccd7a18a (diff)
parent3c92c2ba33cd7d666c5f83cc32aa590e794e91b0 (diff)
Merge branch 'master'
Diffstat (limited to 'arch/sparc64')
-rw-r--r--arch/sparc64/kernel/entry.S39
-rw-r--r--arch/sparc64/kernel/head.S127
-rw-r--r--arch/sparc64/kernel/irq.c1
-rw-r--r--arch/sparc64/kernel/power.c64
-rw-r--r--arch/sparc64/kernel/rtrap.S7
-rw-r--r--arch/sparc64/lib/VISsave.S8
6 files changed, 173 insertions, 73 deletions
diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S
index f685035dbdb8..11a848402fb1 100644
--- a/arch/sparc64/kernel/entry.S
+++ b/arch/sparc64/kernel/entry.S
@@ -33,7 +33,7 @@
33 /* This is trivial with the new code... */ 33 /* This is trivial with the new code... */
34 .globl do_fpdis 34 .globl do_fpdis
35do_fpdis: 35do_fpdis:
36 sethi %hi(TSTATE_PEF), %g4 ! IEU0 36 sethi %hi(TSTATE_PEF), %g4
37 rdpr %tstate, %g5 37 rdpr %tstate, %g5
38 andcc %g5, %g4, %g0 38 andcc %g5, %g4, %g0
39 be,pt %xcc, 1f 39 be,pt %xcc, 1f
@@ -50,18 +50,18 @@ do_fpdis:
50 add %g0, %g0, %g0 50 add %g0, %g0, %g0
51 ba,a,pt %xcc, rtrap_clr_l6 51 ba,a,pt %xcc, rtrap_clr_l6
52 52
531: ldub [%g6 + TI_FPSAVED], %g5 ! Load Group 531: ldub [%g6 + TI_FPSAVED], %g5
54 wr %g0, FPRS_FEF, %fprs ! LSU Group+4bubbles 54 wr %g0, FPRS_FEF, %fprs
55 andcc %g5, FPRS_FEF, %g0 ! IEU1 Group 55 andcc %g5, FPRS_FEF, %g0
56 be,a,pt %icc, 1f ! CTI 56 be,a,pt %icc, 1f
57 clr %g7 ! IEU0 57 clr %g7
58 ldx [%g6 + TI_GSR], %g7 ! Load Group 58 ldx [%g6 + TI_GSR], %g7
591: andcc %g5, FPRS_DL, %g0 ! IEU1 591: andcc %g5, FPRS_DL, %g0
60 bne,pn %icc, 2f ! CTI 60 bne,pn %icc, 2f
61 fzero %f0 ! FPA 61 fzero %f0
62 andcc %g5, FPRS_DU, %g0 ! IEU1 Group 62 andcc %g5, FPRS_DU, %g0
63 bne,pn %icc, 1f ! CTI 63 bne,pn %icc, 1f
64 fzero %f2 ! FPA 64 fzero %f2
65 faddd %f0, %f2, %f4 65 faddd %f0, %f2, %f4
66 fmuld %f0, %f2, %f6 66 fmuld %f0, %f2, %f6
67 faddd %f0, %f2, %f8 67 faddd %f0, %f2, %f8
@@ -104,8 +104,10 @@ do_fpdis:
104 add %g6, TI_FPREGS + 0xc0, %g2 104 add %g6, TI_FPREGS + 0xc0, %g2
105 faddd %f0, %f2, %f8 105 faddd %f0, %f2, %f8
106 fmuld %f0, %f2, %f10 106 fmuld %f0, %f2, %f10
107 ldda [%g1] ASI_BLK_S, %f32 ! grrr, where is ASI_BLK_NUCLEUS 8-( 107 membar #Sync
108 ldda [%g1] ASI_BLK_S, %f32
108 ldda [%g2] ASI_BLK_S, %f48 109 ldda [%g2] ASI_BLK_S, %f48
110 membar #Sync
109 faddd %f0, %f2, %f12 111 faddd %f0, %f2, %f12
110 fmuld %f0, %f2, %f14 112 fmuld %f0, %f2, %f14
111 faddd %f0, %f2, %f16 113 faddd %f0, %f2, %f16
@@ -116,7 +118,6 @@ do_fpdis:
116 fmuld %f0, %f2, %f26 118 fmuld %f0, %f2, %f26
117 faddd %f0, %f2, %f28 119 faddd %f0, %f2, %f28
118 fmuld %f0, %f2, %f30 120 fmuld %f0, %f2, %f30
119 membar #Sync
120 b,pt %xcc, fpdis_exit 121 b,pt %xcc, fpdis_exit
121 nop 122 nop
1222: andcc %g5, FPRS_DU, %g0 1232: andcc %g5, FPRS_DU, %g0
@@ -133,8 +134,10 @@ do_fpdis:
133 add %g6, TI_FPREGS + 0x40, %g2 134 add %g6, TI_FPREGS + 0x40, %g2
134 faddd %f32, %f34, %f36 135 faddd %f32, %f34, %f36
135 fmuld %f32, %f34, %f38 136 fmuld %f32, %f34, %f38
136 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-( 137 membar #Sync
138 ldda [%g1] ASI_BLK_S, %f0
137 ldda [%g2] ASI_BLK_S, %f16 139 ldda [%g2] ASI_BLK_S, %f16
140 membar #Sync
138 faddd %f32, %f34, %f40 141 faddd %f32, %f34, %f40
139 fmuld %f32, %f34, %f42 142 fmuld %f32, %f34, %f42
140 faddd %f32, %f34, %f44 143 faddd %f32, %f34, %f44
@@ -147,7 +150,6 @@ do_fpdis:
147 fmuld %f32, %f34, %f58 150 fmuld %f32, %f34, %f58
148 faddd %f32, %f34, %f60 151 faddd %f32, %f34, %f60
149 fmuld %f32, %f34, %f62 152 fmuld %f32, %f34, %f62
150 membar #Sync
151 ba,pt %xcc, fpdis_exit 153 ba,pt %xcc, fpdis_exit
152 nop 154 nop
1533: mov SECONDARY_CONTEXT, %g3 1553: mov SECONDARY_CONTEXT, %g3
@@ -158,7 +160,8 @@ do_fpdis:
158 stxa %g2, [%g3] ASI_DMMU 160 stxa %g2, [%g3] ASI_DMMU
159 membar #Sync 161 membar #Sync
160 mov 0x40, %g2 162 mov 0x40, %g2
161 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-( 163 membar #Sync
164 ldda [%g1] ASI_BLK_S, %f0
162 ldda [%g1 + %g2] ASI_BLK_S, %f16 165 ldda [%g1 + %g2] ASI_BLK_S, %f16
163 add %g1, 0x80, %g1 166 add %g1, 0x80, %g1
164 ldda [%g1] ASI_BLK_S, %f32 167 ldda [%g1] ASI_BLK_S, %f32
diff --git a/arch/sparc64/kernel/head.S b/arch/sparc64/kernel/head.S
index 24340496cdd3..f1dcdf8f7433 100644
--- a/arch/sparc64/kernel/head.S
+++ b/arch/sparc64/kernel/head.S
@@ -382,32 +382,79 @@ tlb_fixup_done:
382 nop 382 nop
383 /* Not reached... */ 383 /* Not reached... */
384 384
385/* IMPORTANT NOTE: Whenever making changes here, check 385 /* This is meant to allow the sharing of this code between
386 * trampoline.S as well. -jj */ 386 * boot processor invocation (via setup_tba() below) and
387 .globl setup_tba 387 * secondary processor startup (via trampoline.S). The
388setup_tba: /* i0 = is_starfire */ 388 * former does use this code, the latter does not yet due
389 save %sp, -160, %sp 389 * to some complexities. That should be fixed up at some
390 * point.
391 */
392 .globl setup_trap_table
393setup_trap_table:
394 save %sp, -192, %sp
395
396 /* Force interrupts to be disabled. Transferring over to
397 * the Linux trap table is a very delicate operation.
398 * Until we are actually on the Linux trap table, we cannot
399 * get the PAGE_OFFSET linear mappings translated. We need
400 * that mapping to be setup in order to initialize the firmware
401 * page tables.
402 *
403 * So there is this window of time, from the return from
404 * prom_set_trap_table() until inherit_prom_mappings_post()
405 * (in arch/sparc64/mm/init.c) completes, during which no
406 * firmware address space accesses can be made.
407 */
408 rdpr %pstate, %o1
409 andn %o1, PSTATE_IE, %o1
410 wrpr %o1, 0x0, %pstate
411 wrpr %g0, 15, %pil
390 412
391 rdpr %tba, %g7 413 /* Ok, now make the final valid firmware call to jump over
392 sethi %hi(prom_tba), %o1 414 * to the Linux trap table.
393 or %o1, %lo(prom_tba), %o1 415 */
394 stx %g7, [%o1] 416 call prom_set_trap_table
417 sethi %hi(sparc64_ttable_tl0), %o0
418
419 /* Start using proper page size encodings in ctx register. */
420 sethi %hi(sparc64_kern_pri_context), %g3
421 ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
422 mov PRIMARY_CONTEXT, %g1
423 stxa %g2, [%g1] ASI_DMMU
424 membar #Sync
425
426 /* The Linux trap handlers expect various trap global registers
427 * to be setup with some fixed values. So here we set these
428 * up very carefully. These globals are:
429 *
430 * Alternate Globals (PSTATE_AG):
431 *
432 * %g6 --> current_thread_info()
433 *
434 * MMU Globals (PSTATE_MG):
435 *
436 * %g1 --> TLB_SFSR
437 * %g2 --> ((_PAGE_VALID | _PAGE_SZ4MB |
438 * _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W)
439 * ^ 0xfffff80000000000)
440 * (this %g2 value is used for computing the PAGE_OFFSET kernel
441 * TLB entries quickly, the virtual address of the fault XOR'd
442 * with this %g2 value is the PTE to load into the TLB)
443 * %g3 --> VPTE_BASE_CHEETAH or VPTE_BASE_SPITFIRE
444 *
445 * Interrupt Globals (PSTATE_IG, setup by init_irqwork_curcpu()):
446 *
447 * %g6 --> __irq_work[smp_processor_id()]
448 */
395 449
396 /* Setup "Linux" globals 8-) */
397 rdpr %pstate, %o1 450 rdpr %pstate, %o1
398 mov %g6, %o2 451 mov %g6, %o2
399 wrpr %o1, (PSTATE_AG|PSTATE_IE), %pstate 452 wrpr %o1, PSTATE_AG, %pstate
400 sethi %hi(sparc64_ttable_tl0), %g1
401 wrpr %g1, %tba
402 mov %o2, %g6 453 mov %o2, %g6
403 454
404 /* Set up MMU globals */
405 wrpr %o1, (PSTATE_MG|PSTATE_IE), %pstate
406
407 /* Set fixed globals used by dTLB miss handler. */
408#define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZ4MB)^0xfffff80000000000) 455#define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZ4MB)^0xfffff80000000000)
409#define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W) 456#define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W)
410 457 wrpr %o1, PSTATE_MG, %pstate
411 mov TSB_REG, %g1 458 mov TSB_REG, %g1
412 stxa %g0, [%g1] ASI_DMMU 459 stxa %g0, [%g1] ASI_DMMU
413 membar #Sync 460 membar #Sync
@@ -419,17 +466,17 @@ setup_tba: /* i0 = is_starfire */
419 sllx %g2, 32, %g2 466 sllx %g2, 32, %g2
420 or %g2, KERN_LOWBITS, %g2 467 or %g2, KERN_LOWBITS, %g2
421 468
422 BRANCH_IF_ANY_CHEETAH(g3,g7,cheetah_vpte_base) 469 BRANCH_IF_ANY_CHEETAH(g3,g7,8f)
423 ba,pt %xcc, spitfire_vpte_base 470 ba,pt %xcc, 9f
424 nop 471 nop
425 472
426cheetah_vpte_base: 4738:
427 sethi %uhi(VPTE_BASE_CHEETAH), %g3 474 sethi %uhi(VPTE_BASE_CHEETAH), %g3
428 or %g3, %ulo(VPTE_BASE_CHEETAH), %g3 475 or %g3, %ulo(VPTE_BASE_CHEETAH), %g3
429 ba,pt %xcc, 2f 476 ba,pt %xcc, 2f
430 sllx %g3, 32, %g3 477 sllx %g3, 32, %g3
431 478
432spitfire_vpte_base: 4799:
433 sethi %uhi(VPTE_BASE_SPITFIRE), %g3 480 sethi %uhi(VPTE_BASE_SPITFIRE), %g3
434 or %g3, %ulo(VPTE_BASE_SPITFIRE), %g3 481 or %g3, %ulo(VPTE_BASE_SPITFIRE), %g3
435 sllx %g3, 32, %g3 482 sllx %g3, 32, %g3
@@ -455,29 +502,37 @@ spitfire_vpte_base:
455 sllx %o2, 32, %o2 502 sllx %o2, 32, %o2
456 wr %o2, %asr25 503 wr %o2, %asr25
457 504
458 /* Ok, we're done setting up all the state our trap mechanims needs,
459 * now get back into normal globals and let the PROM know what is up.
460 */
4612: 5052:
462 wrpr %g0, %g0, %wstate 506 wrpr %g0, %g0, %wstate
463 wrpr %o1, PSTATE_IE, %pstate 507 wrpr %o1, 0x0, %pstate
464 508
465 call init_irqwork_curcpu 509 call init_irqwork_curcpu
466 nop 510 nop
467 511
468 call prom_set_trap_table 512 /* Now we can turn interrupts back on. */
469 sethi %hi(sparc64_ttable_tl0), %o0
470
471 /* Start using proper page size encodings in ctx register. */
472 sethi %hi(sparc64_kern_pri_context), %g3
473 ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
474 mov PRIMARY_CONTEXT, %g1
475 stxa %g2, [%g1] ASI_DMMU
476 membar #Sync
477
478 rdpr %pstate, %o1 513 rdpr %pstate, %o1
479 or %o1, PSTATE_IE, %o1 514 or %o1, PSTATE_IE, %o1
480 wrpr %o1, 0, %pstate 515 wrpr %o1, 0, %pstate
516 wrpr %g0, 0x0, %pil
517
518 ret
519 restore
520
521 .globl setup_tba
522setup_tba: /* i0 = is_starfire */
523 save %sp, -192, %sp
524
525 /* The boot processor is the only cpu which invokes this
526 * routine, the other cpus set things up via trampoline.S.
527 * So save the OBP trap table address here.
528 */
529 rdpr %tba, %g7
530 sethi %hi(prom_tba), %o1
531 or %o1, %lo(prom_tba), %o1
532 stx %g7, [%o1]
533
534 call setup_trap_table
535 nop
481 536
482 ret 537 ret
483 restore 538 restore
diff --git a/arch/sparc64/kernel/irq.c b/arch/sparc64/kernel/irq.c
index c9b69167632a..233526ba3abe 100644
--- a/arch/sparc64/kernel/irq.c
+++ b/arch/sparc64/kernel/irq.c
@@ -27,6 +27,7 @@
27#include <asm/atomic.h> 27#include <asm/atomic.h>
28#include <asm/system.h> 28#include <asm/system.h>
29#include <asm/irq.h> 29#include <asm/irq.h>
30#include <asm/io.h>
30#include <asm/sbus.h> 31#include <asm/sbus.h>
31#include <asm/iommu.h> 32#include <asm/iommu.h>
32#include <asm/upa.h> 33#include <asm/upa.h>
diff --git a/arch/sparc64/kernel/power.c b/arch/sparc64/kernel/power.c
index 946cee0257ea..9e8362ea3104 100644
--- a/arch/sparc64/kernel/power.c
+++ b/arch/sparc64/kernel/power.c
@@ -17,6 +17,7 @@
17 17
18#include <asm/system.h> 18#include <asm/system.h>
19#include <asm/ebus.h> 19#include <asm/ebus.h>
20#include <asm/isa.h>
20#include <asm/auxio.h> 21#include <asm/auxio.h>
21 22
22#include <linux/unistd.h> 23#include <linux/unistd.h>
@@ -100,46 +101,83 @@ again:
100 return 0; 101 return 0;
101} 102}
102 103
103static int __init has_button_interrupt(struct linux_ebus_device *edev) 104static int __init has_button_interrupt(unsigned int irq, int prom_node)
104{ 105{
105 if (edev->irqs[0] == PCI_IRQ_NONE) 106 if (irq == PCI_IRQ_NONE)
106 return 0; 107 return 0;
107 if (!prom_node_has_property(edev->prom_node, "button")) 108 if (!prom_node_has_property(prom_node, "button"))
108 return 0; 109 return 0;
109 110
110 return 1; 111 return 1;
111} 112}
112 113
113void __init power_init(void) 114static int __init power_probe_ebus(struct resource **resp, unsigned int *irq_p, int *prom_node_p)
114{ 115{
115 struct linux_ebus *ebus; 116 struct linux_ebus *ebus;
116 struct linux_ebus_device *edev; 117 struct linux_ebus_device *edev;
118
119 for_each_ebus(ebus) {
120 for_each_ebusdev(edev, ebus) {
121 if (!strcmp(edev->prom_name, "power")) {
122 *resp = &edev->resource[0];
123 *irq_p = edev->irqs[0];
124 *prom_node_p = edev->prom_node;
125 return 0;
126 }
127 }
128 }
129 return -ENODEV;
130}
131
132static int __init power_probe_isa(struct resource **resp, unsigned int *irq_p, int *prom_node_p)
133{
134 struct sparc_isa_bridge *isa_bus;
135 struct sparc_isa_device *isa_dev;
136
137 for_each_isa(isa_bus) {
138 for_each_isadev(isa_dev, isa_bus) {
139 if (!strcmp(isa_dev->prom_name, "power")) {
140 *resp = &isa_dev->resource;
141 *irq_p = isa_dev->irq;
142 *prom_node_p = isa_dev->prom_node;
143 return 0;
144 }
145 }
146 }
147 return -ENODEV;
148}
149
150void __init power_init(void)
151{
152 struct resource *res = NULL;
153 unsigned int irq;
154 int prom_node;
117 static int invoked; 155 static int invoked;
118 156
119 if (invoked) 157 if (invoked)
120 return; 158 return;
121 invoked = 1; 159 invoked = 1;
122 160
123 for_each_ebus(ebus) { 161 if (!power_probe_ebus(&res, &irq, &prom_node))
124 for_each_ebusdev(edev, ebus) { 162 goto found;
125 if (!strcmp(edev->prom_name, "power")) 163
126 goto found; 164 if (!power_probe_isa(&res, &irq, &prom_node))
127 } 165 goto found;
128 } 166
129 return; 167 return;
130 168
131found: 169found:
132 power_reg = ioremap(edev->resource[0].start, 0x4); 170 power_reg = ioremap(res->start, 0x4);
133 printk("power: Control reg at %p ... ", power_reg); 171 printk("power: Control reg at %p ... ", power_reg);
134 poweroff_method = machine_halt; /* able to use the standard halt */ 172 poweroff_method = machine_halt; /* able to use the standard halt */
135 if (has_button_interrupt(edev)) { 173 if (has_button_interrupt(irq, prom_node)) {
136 if (kernel_thread(powerd, NULL, CLONE_FS) < 0) { 174 if (kernel_thread(powerd, NULL, CLONE_FS) < 0) {
137 printk("Failed to start power daemon.\n"); 175 printk("Failed to start power daemon.\n");
138 return; 176 return;
139 } 177 }
140 printk("powerd running.\n"); 178 printk("powerd running.\n");
141 179
142 if (request_irq(edev->irqs[0], 180 if (request_irq(irq,
143 power_handler, SA_SHIRQ, "power", NULL) < 0) 181 power_handler, SA_SHIRQ, "power", NULL) < 0)
144 printk("power: Error, cannot register IRQ handler.\n"); 182 printk("power: Error, cannot register IRQ handler.\n");
145 } else { 183 } else {
diff --git a/arch/sparc64/kernel/rtrap.S b/arch/sparc64/kernel/rtrap.S
index ecfb42a69a44..090dcca00d2a 100644
--- a/arch/sparc64/kernel/rtrap.S
+++ b/arch/sparc64/kernel/rtrap.S
@@ -312,32 +312,33 @@ kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
312 wr %g1, FPRS_FEF, %fprs 312 wr %g1, FPRS_FEF, %fprs
313 ldx [%o1 + %o5], %g1 313 ldx [%o1 + %o5], %g1
314 add %g6, TI_XFSR, %o1 314 add %g6, TI_XFSR, %o1
315 membar #StoreLoad | #LoadLoad
316 sll %o0, 8, %o2 315 sll %o0, 8, %o2
317 add %g6, TI_FPREGS, %o3 316 add %g6, TI_FPREGS, %o3
318 brz,pn %l6, 1f 317 brz,pn %l6, 1f
319 add %g6, TI_FPREGS+0x40, %o4 318 add %g6, TI_FPREGS+0x40, %o4
320 319
320 membar #Sync
321 ldda [%o3 + %o2] ASI_BLK_P, %f0 321 ldda [%o3 + %o2] ASI_BLK_P, %f0
322 ldda [%o4 + %o2] ASI_BLK_P, %f16 322 ldda [%o4 + %o2] ASI_BLK_P, %f16
323 membar #Sync
3231: andcc %l2, FPRS_DU, %g0 3241: andcc %l2, FPRS_DU, %g0
324 be,pn %icc, 1f 325 be,pn %icc, 1f
325 wr %g1, 0, %gsr 326 wr %g1, 0, %gsr
326 add %o2, 0x80, %o2 327 add %o2, 0x80, %o2
328 membar #Sync
327 ldda [%o3 + %o2] ASI_BLK_P, %f32 329 ldda [%o3 + %o2] ASI_BLK_P, %f32
328 ldda [%o4 + %o2] ASI_BLK_P, %f48 330 ldda [%o4 + %o2] ASI_BLK_P, %f48
329
3301: membar #Sync 3311: membar #Sync
331 ldx [%o1 + %o5], %fsr 332 ldx [%o1 + %o5], %fsr
3322: stb %l5, [%g6 + TI_FPDEPTH] 3332: stb %l5, [%g6 + TI_FPDEPTH]
333 ba,pt %xcc, rt_continue 334 ba,pt %xcc, rt_continue
334 nop 335 nop
3355: wr %g0, FPRS_FEF, %fprs 3365: wr %g0, FPRS_FEF, %fprs
336 membar #StoreLoad | #LoadLoad
337 sll %o0, 8, %o2 337 sll %o0, 8, %o2
338 338
339 add %g6, TI_FPREGS+0x80, %o3 339 add %g6, TI_FPREGS+0x80, %o3
340 add %g6, TI_FPREGS+0xc0, %o4 340 add %g6, TI_FPREGS+0xc0, %o4
341 membar #Sync
341 ldda [%o3 + %o2] ASI_BLK_P, %f32 342 ldda [%o3 + %o2] ASI_BLK_P, %f32
342 ldda [%o4 + %o2] ASI_BLK_P, %f48 343 ldda [%o4 + %o2] ASI_BLK_P, %f48
343 membar #Sync 344 membar #Sync
diff --git a/arch/sparc64/lib/VISsave.S b/arch/sparc64/lib/VISsave.S
index 4e18989bd602..a0ded5c5aa5c 100644
--- a/arch/sparc64/lib/VISsave.S
+++ b/arch/sparc64/lib/VISsave.S
@@ -59,15 +59,17 @@ vis1: ldub [%g6 + TI_FPSAVED], %g3
59 be,pn %icc, 9b 59 be,pn %icc, 9b
60 add %g6, TI_FPREGS, %g2 60 add %g6, TI_FPREGS, %g2
61 andcc %o5, FPRS_DL, %g0 61 andcc %o5, FPRS_DL, %g0
62 membar #StoreStore | #LoadStore
63 62
64 be,pn %icc, 4f 63 be,pn %icc, 4f
65 add %g6, TI_FPREGS+0x40, %g3 64 add %g6, TI_FPREGS+0x40, %g3
65 membar #Sync
66 stda %f0, [%g2 + %g1] ASI_BLK_P 66 stda %f0, [%g2 + %g1] ASI_BLK_P
67 stda %f16, [%g3 + %g1] ASI_BLK_P 67 stda %f16, [%g3 + %g1] ASI_BLK_P
68 membar #Sync
68 andcc %o5, FPRS_DU, %g0 69 andcc %o5, FPRS_DU, %g0
69 be,pn %icc, 5f 70 be,pn %icc, 5f
704: add %g1, 128, %g1 714: add %g1, 128, %g1
72 membar #Sync
71 stda %f32, [%g2 + %g1] ASI_BLK_P 73 stda %f32, [%g2 + %g1] ASI_BLK_P
72 74
73 stda %f48, [%g3 + %g1] ASI_BLK_P 75 stda %f48, [%g3 + %g1] ASI_BLK_P
@@ -87,7 +89,7 @@ vis1: ldub [%g6 + TI_FPSAVED], %g3
87 sll %g1, 5, %g1 89 sll %g1, 5, %g1
88 add %g6, TI_FPREGS+0xc0, %g3 90 add %g6, TI_FPREGS+0xc0, %g3
89 wr %g0, FPRS_FEF, %fprs 91 wr %g0, FPRS_FEF, %fprs
90 membar #StoreStore | #LoadStore 92 membar #Sync
91 stda %f32, [%g2 + %g1] ASI_BLK_P 93 stda %f32, [%g2 + %g1] ASI_BLK_P
92 stda %f48, [%g3 + %g1] ASI_BLK_P 94 stda %f48, [%g3 + %g1] ASI_BLK_P
93 membar #Sync 95 membar #Sync
@@ -128,8 +130,8 @@ VISenterhalf:
128 be,pn %icc, 4f 130 be,pn %icc, 4f
129 add %g6, TI_FPREGS, %g2 131 add %g6, TI_FPREGS, %g2
130 132
131 membar #StoreStore | #LoadStore
132 add %g6, TI_FPREGS+0x40, %g3 133 add %g6, TI_FPREGS+0x40, %g3
134 membar #Sync
133 stda %f0, [%g2 + %g1] ASI_BLK_P 135 stda %f0, [%g2 + %g1] ASI_BLK_P
134 stda %f16, [%g3 + %g1] ASI_BLK_P 136 stda %f16, [%g3 + %g1] ASI_BLK_P
135 membar #Sync 137 membar #Sync
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-08 03:44:04 -0500