diff options
author | David S. Miller <davem@davemloft.net> | 2006-01-31 21:33:00 -0500 |
---|---|---|
committer | David S. Miller <davem@sunset.davemloft.net> | 2006-03-20 04:11:22 -0500 |
commit | 4da808c352c290d3f762933d44d4ab90c2fd65f3 (patch) | |
tree | da99326440777580a19c345a5b0d52fbf800042b /arch/sparc64 | |
parent | 4753eb2ac7022b999e5e484f1a5dc001dba22bd3 (diff) |
[SPARC64]: Fix bogus flush instruction usage.
Some of the trap code was still assuming that alternate
global %g6 was hard coded with current_thread_info().
Let's just consistently flush at KERNBASE when we need
a pipeline synchronization. That's locked into the TLB
and will always work.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64')
-rw-r--r-- | arch/sparc64/kernel/etrap.S | 6 | ||||
-rw-r--r-- | arch/sparc64/kernel/rtrap.S | 3 | ||||
-rw-r--r-- | arch/sparc64/kernel/winfixup.S | 3 | ||||
-rw-r--r-- | arch/sparc64/lib/clear_page.S | 4 | ||||
-rw-r--r-- | arch/sparc64/mm/ultra.S | 31 |
5 files changed, 30 insertions, 17 deletions
diff --git a/arch/sparc64/kernel/etrap.S b/arch/sparc64/kernel/etrap.S index 8b3b6d720ed5..db7681017299 100644 --- a/arch/sparc64/kernel/etrap.S +++ b/arch/sparc64/kernel/etrap.S | |||
@@ -72,7 +72,8 @@ etrap_irq: | |||
72 | sethi %hi(sparc64_kern_pri_context), %g2 | 72 | sethi %hi(sparc64_kern_pri_context), %g2 |
73 | ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3 | 73 | ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3 |
74 | stxa %g3, [%l4] ASI_DMMU | 74 | stxa %g3, [%l4] ASI_DMMU |
75 | flush %l6 | 75 | sethi %hi(KERNBASE), %l4 |
76 | flush %l4 | ||
76 | wr %g0, ASI_AIUS, %asi | 77 | wr %g0, ASI_AIUS, %asi |
77 | 2: wrpr %g0, 0x0, %tl | 78 | 2: wrpr %g0, 0x0, %tl |
78 | mov %g4, %l4 | 79 | mov %g4, %l4 |
@@ -215,7 +216,8 @@ scetrap: | |||
215 | sethi %hi(sparc64_kern_pri_context), %g2 | 216 | sethi %hi(sparc64_kern_pri_context), %g2 |
216 | ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3 | 217 | ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3 |
217 | stxa %g3, [%l4] ASI_DMMU | 218 | stxa %g3, [%l4] ASI_DMMU |
218 | flush %l6 | 219 | sethi %hi(KERNBASE), %l4 |
220 | flush %l4 | ||
219 | 221 | ||
220 | mov ASI_AIUS, %l7 | 222 | mov ASI_AIUS, %l7 |
221 | 2: mov %g4, %l4 | 223 | 2: mov %g4, %l4 |
diff --git a/arch/sparc64/kernel/rtrap.S b/arch/sparc64/kernel/rtrap.S index 5a62ec5d531c..89794ebdcbcf 100644 --- a/arch/sparc64/kernel/rtrap.S +++ b/arch/sparc64/kernel/rtrap.S | |||
@@ -259,7 +259,8 @@ rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1 | |||
259 | ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1 | 259 | ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1 |
260 | or %l0, %l1, %l0 | 260 | or %l0, %l1, %l0 |
261 | stxa %l0, [%l7] ASI_DMMU | 261 | stxa %l0, [%l7] ASI_DMMU |
262 | flush %g6 | 262 | sethi %hi(KERNBASE), %l7 |
263 | flush %l7 | ||
263 | rdpr %wstate, %l1 | 264 | rdpr %wstate, %l1 |
264 | rdpr %otherwin, %l2 | 265 | rdpr %otherwin, %l2 |
265 | srl %l1, 3, %l1 | 266 | srl %l1, 3, %l1 |
diff --git a/arch/sparc64/kernel/winfixup.S b/arch/sparc64/kernel/winfixup.S index de588036df43..c0545d089c96 100644 --- a/arch/sparc64/kernel/winfixup.S +++ b/arch/sparc64/kernel/winfixup.S | |||
@@ -20,7 +20,8 @@ set_pcontext: | |||
20 | ldx [%l1 + %lo(sparc64_kern_pri_context)], %l1 | 20 | ldx [%l1 + %lo(sparc64_kern_pri_context)], %l1 |
21 | mov PRIMARY_CONTEXT, %g1 | 21 | mov PRIMARY_CONTEXT, %g1 |
22 | stxa %l1, [%g1] ASI_DMMU | 22 | stxa %l1, [%g1] ASI_DMMU |
23 | flush %g6 | 23 | sethi %hi(KERNBASE), %l1 |
24 | flush %l1 | ||
24 | retl | 25 | retl |
25 | nop | 26 | nop |
26 | 27 | ||
diff --git a/arch/sparc64/lib/clear_page.S b/arch/sparc64/lib/clear_page.S index b59884ef051d..cdc634bceba0 100644 --- a/arch/sparc64/lib/clear_page.S +++ b/arch/sparc64/lib/clear_page.S | |||
@@ -9,6 +9,7 @@ | |||
9 | #include <asm/page.h> | 9 | #include <asm/page.h> |
10 | #include <asm/pgtable.h> | 10 | #include <asm/pgtable.h> |
11 | #include <asm/spitfire.h> | 11 | #include <asm/spitfire.h> |
12 | #include <asm/head.h> | ||
12 | 13 | ||
13 | /* What we used to do was lock a TLB entry into a specific | 14 | /* What we used to do was lock a TLB entry into a specific |
14 | * TLB slot, clear the page with interrupts disabled, then | 15 | * TLB slot, clear the page with interrupts disabled, then |
@@ -66,7 +67,8 @@ clear_user_page: /* %o0=dest, %o1=vaddr */ | |||
66 | wrpr %o4, PSTATE_IE, %pstate | 67 | wrpr %o4, PSTATE_IE, %pstate |
67 | stxa %o0, [%g3] ASI_DMMU | 68 | stxa %o0, [%g3] ASI_DMMU |
68 | stxa %g1, [%g0] ASI_DTLB_DATA_IN | 69 | stxa %g1, [%g0] ASI_DTLB_DATA_IN |
69 | flush %g6 | 70 | sethi %hi(KERNBASE), %g1 |
71 | flush %g1 | ||
70 | wrpr %o4, 0x0, %pstate | 72 | wrpr %o4, 0x0, %pstate |
71 | 73 | ||
72 | mov 1, %o4 | 74 | mov 1, %o4 |
diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S index a87394824ec2..269ed57b3e9d 100644 --- a/arch/sparc64/mm/ultra.S +++ b/arch/sparc64/mm/ultra.S | |||
@@ -36,9 +36,10 @@ __flush_tlb_mm: /* %o0=(ctx & TAG_CONTEXT_BITS), %o1=SECONDARY_CONTEXT */ | |||
36 | mov 0x50, %g3 | 36 | mov 0x50, %g3 |
37 | stxa %g0, [%g3] ASI_DMMU_DEMAP | 37 | stxa %g0, [%g3] ASI_DMMU_DEMAP |
38 | stxa %g0, [%g3] ASI_IMMU_DEMAP | 38 | stxa %g0, [%g3] ASI_IMMU_DEMAP |
39 | sethi %hi(KERNBASE), %g3 | ||
40 | flush %g3 | ||
39 | retl | 41 | retl |
40 | flush %g6 | 42 | nop |
41 | nop | ||
42 | nop | 43 | nop |
43 | nop | 44 | nop |
44 | nop | 45 | nop |
@@ -72,7 +73,8 @@ __flush_tlb_pending: | |||
72 | brnz,pt %o1, 1b | 73 | brnz,pt %o1, 1b |
73 | nop | 74 | nop |
74 | stxa %g2, [%o4] ASI_DMMU | 75 | stxa %g2, [%o4] ASI_DMMU |
75 | flush %g6 | 76 | sethi %hi(KERNBASE), %o4 |
77 | flush %o4 | ||
76 | retl | 78 | retl |
77 | wrpr %g7, 0x0, %pstate | 79 | wrpr %g7, 0x0, %pstate |
78 | nop | 80 | nop |
@@ -94,8 +96,10 @@ __flush_tlb_kernel_range: /* %o0=start, %o1=end */ | |||
94 | membar #Sync | 96 | membar #Sync |
95 | brnz,pt %o3, 1b | 97 | brnz,pt %o3, 1b |
96 | sub %o3, %o4, %o3 | 98 | sub %o3, %o4, %o3 |
97 | 2: retl | 99 | 2: sethi %hi(KERNBASE), %o3 |
98 | flush %g6 | 100 | flush %o3 |
101 | retl | ||
102 | nop | ||
99 | 103 | ||
100 | __spitfire_flush_tlb_mm_slow: | 104 | __spitfire_flush_tlb_mm_slow: |
101 | rdpr %pstate, %g1 | 105 | rdpr %pstate, %g1 |
@@ -105,7 +109,8 @@ __spitfire_flush_tlb_mm_slow: | |||
105 | stxa %g0, [%g3] ASI_IMMU_DEMAP | 109 | stxa %g0, [%g3] ASI_IMMU_DEMAP |
106 | flush %g6 | 110 | flush %g6 |
107 | stxa %g2, [%o1] ASI_DMMU | 111 | stxa %g2, [%o1] ASI_DMMU |
108 | flush %g6 | 112 | sethi %hi(KERNBASE), %o1 |
113 | flush %o1 | ||
109 | retl | 114 | retl |
110 | wrpr %g1, 0, %pstate | 115 | wrpr %g1, 0, %pstate |
111 | 116 | ||
@@ -181,7 +186,7 @@ __flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */ | |||
181 | .previous | 186 | .previous |
182 | 187 | ||
183 | /* Cheetah specific versions, patched at boot time. */ | 188 | /* Cheetah specific versions, patched at boot time. */ |
184 | __cheetah_flush_tlb_mm: /* 18 insns */ | 189 | __cheetah_flush_tlb_mm: /* 19 insns */ |
185 | rdpr %pstate, %g7 | 190 | rdpr %pstate, %g7 |
186 | andn %g7, PSTATE_IE, %g2 | 191 | andn %g7, PSTATE_IE, %g2 |
187 | wrpr %g2, 0x0, %pstate | 192 | wrpr %g2, 0x0, %pstate |
@@ -196,12 +201,13 @@ __cheetah_flush_tlb_mm: /* 18 insns */ | |||
196 | stxa %g0, [%g3] ASI_DMMU_DEMAP | 201 | stxa %g0, [%g3] ASI_DMMU_DEMAP |
197 | stxa %g0, [%g3] ASI_IMMU_DEMAP | 202 | stxa %g0, [%g3] ASI_IMMU_DEMAP |
198 | stxa %g2, [%o2] ASI_DMMU | 203 | stxa %g2, [%o2] ASI_DMMU |
199 | flush %g6 | 204 | sethi %hi(KERNBASE), %o2 |
205 | flush %o2 | ||
200 | wrpr %g0, 0, %tl | 206 | wrpr %g0, 0, %tl |
201 | retl | 207 | retl |
202 | wrpr %g7, 0x0, %pstate | 208 | wrpr %g7, 0x0, %pstate |
203 | 209 | ||
204 | __cheetah_flush_tlb_pending: /* 26 insns */ | 210 | __cheetah_flush_tlb_pending: /* 27 insns */ |
205 | /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ | 211 | /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ |
206 | rdpr %pstate, %g7 | 212 | rdpr %pstate, %g7 |
207 | sllx %o1, 3, %o1 | 213 | sllx %o1, 3, %o1 |
@@ -225,7 +231,8 @@ __cheetah_flush_tlb_pending: /* 26 insns */ | |||
225 | brnz,pt %o1, 1b | 231 | brnz,pt %o1, 1b |
226 | nop | 232 | nop |
227 | stxa %g2, [%o4] ASI_DMMU | 233 | stxa %g2, [%o4] ASI_DMMU |
228 | flush %g6 | 234 | sethi %hi(KERNBASE), %o4 |
235 | flush %o4 | ||
229 | wrpr %g0, 0, %tl | 236 | wrpr %g0, 0, %tl |
230 | retl | 237 | retl |
231 | wrpr %g7, 0x0, %pstate | 238 | wrpr %g7, 0x0, %pstate |
@@ -265,14 +272,14 @@ cheetah_patch_cachetlbops: | |||
265 | sethi %hi(__cheetah_flush_tlb_mm), %o1 | 272 | sethi %hi(__cheetah_flush_tlb_mm), %o1 |
266 | or %o1, %lo(__cheetah_flush_tlb_mm), %o1 | 273 | or %o1, %lo(__cheetah_flush_tlb_mm), %o1 |
267 | call cheetah_patch_one | 274 | call cheetah_patch_one |
268 | mov 18, %o2 | 275 | mov 19, %o2 |
269 | 276 | ||
270 | sethi %hi(__flush_tlb_pending), %o0 | 277 | sethi %hi(__flush_tlb_pending), %o0 |
271 | or %o0, %lo(__flush_tlb_pending), %o0 | 278 | or %o0, %lo(__flush_tlb_pending), %o0 |
272 | sethi %hi(__cheetah_flush_tlb_pending), %o1 | 279 | sethi %hi(__cheetah_flush_tlb_pending), %o1 |
273 | or %o1, %lo(__cheetah_flush_tlb_pending), %o1 | 280 | or %o1, %lo(__cheetah_flush_tlb_pending), %o1 |
274 | call cheetah_patch_one | 281 | call cheetah_patch_one |
275 | mov 26, %o2 | 282 | mov 27, %o2 |
276 | 283 | ||
277 | #ifdef DCACHE_ALIASING_POSSIBLE | 284 | #ifdef DCACHE_ALIASING_POSSIBLE |
278 | sethi %hi(__flush_dcache_page), %o0 | 285 | sethi %hi(__flush_dcache_page), %o0 |