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authorDavid S. Miller <davem@davemloft.net>2008-11-15 16:33:25 -0500
committerDavid S. Miller <davem@davemloft.net>2008-12-04 12:16:47 -0500
commit293666b7a17cb7a389fc274980439212386a19c4 (patch)
tree075cc7661d2113cf04da7130b3383979d8024206 /arch/sparc64/mm
parent64f2dde3f743c8a1ad8c0a1aa74166c1034afd92 (diff)
sparc64: Stop using memory barriers for atomics and locks.
The kernel always executes in the TSO memory model now, so none of this stuff is necessary any more. With helpful feedback from Nick Piggin. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/mm')
-rw-r--r--arch/sparc64/mm/init.c2
-rw-r--r--arch/sparc64/mm/tsb.c4
-rw-r--r--arch/sparc64/mm/ultra.S2
3 files changed, 1 insertions, 7 deletions
diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
index 185f34679110..4bd63968400d 100644
--- a/arch/sparc64/mm/init.c
+++ b/arch/sparc64/mm/init.c
@@ -214,7 +214,6 @@ static inline void set_dcache_dirty(struct page *page, int this_cpu)
214 "or %%g1, %0, %%g1\n\t" 214 "or %%g1, %0, %%g1\n\t"
215 "casx [%2], %%g7, %%g1\n\t" 215 "casx [%2], %%g7, %%g1\n\t"
216 "cmp %%g7, %%g1\n\t" 216 "cmp %%g7, %%g1\n\t"
217 "membar #StoreLoad | #StoreStore\n\t"
218 "bne,pn %%xcc, 1b\n\t" 217 "bne,pn %%xcc, 1b\n\t"
219 " nop" 218 " nop"
220 : /* no outputs */ 219 : /* no outputs */
@@ -236,7 +235,6 @@ static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
236 " andn %%g7, %1, %%g1\n\t" 235 " andn %%g7, %1, %%g1\n\t"
237 "casx [%2], %%g7, %%g1\n\t" 236 "casx [%2], %%g7, %%g1\n\t"
238 "cmp %%g7, %%g1\n\t" 237 "cmp %%g7, %%g1\n\t"
239 "membar #StoreLoad | #StoreStore\n\t"
240 "bne,pn %%xcc, 1b\n\t" 238 "bne,pn %%xcc, 1b\n\t"
241 " nop\n" 239 " nop\n"
242 "2:" 240 "2:"
diff --git a/arch/sparc64/mm/tsb.c b/arch/sparc64/mm/tsb.c
index 587f8efb2e05..f0282fad632a 100644
--- a/arch/sparc64/mm/tsb.c
+++ b/arch/sparc64/mm/tsb.c
@@ -41,10 +41,8 @@ void flush_tsb_kernel_range(unsigned long start, unsigned long end)
41 KERNEL_TSB_NENTRIES); 41 KERNEL_TSB_NENTRIES);
42 struct tsb *ent = &swapper_tsb[hash]; 42 struct tsb *ent = &swapper_tsb[hash];
43 43
44 if (tag_compare(ent->tag, v)) { 44 if (tag_compare(ent->tag, v))
45 ent->tag = (1UL << TSB_TAG_INVALID_BIT); 45 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
46 membar_storeload_storestore();
47 }
48 } 46 }
49} 47}
50 48
diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S
index 86773e89dc1b..e4c146f7c7e9 100644
--- a/arch/sparc64/mm/ultra.S
+++ b/arch/sparc64/mm/ultra.S
@@ -125,7 +125,6 @@ __spitfire_flush_tlb_mm_slow:
125 .align 32 125 .align 32
126 .globl __flush_icache_page 126 .globl __flush_icache_page
127__flush_icache_page: /* %o0 = phys_page */ 127__flush_icache_page: /* %o0 = phys_page */
128 membar #StoreStore
129 srlx %o0, PAGE_SHIFT, %o0 128 srlx %o0, PAGE_SHIFT, %o0
130 sethi %uhi(PAGE_OFFSET), %g1 129 sethi %uhi(PAGE_OFFSET), %g1
131 sllx %o0, PAGE_SHIFT, %o0 130 sllx %o0, PAGE_SHIFT, %o0
@@ -507,7 +506,6 @@ xcall_fetch_glob_regs:
507 sllx %g2, TRAP_BLOCK_SZ_SHIFT, %g2 506 sllx %g2, TRAP_BLOCK_SZ_SHIFT, %g2
508 add %g7, %g2, %g7 507 add %g7, %g2, %g7
509 ldx [%g7 + TRAP_PER_CPU_THREAD], %g3 508 ldx [%g7 + TRAP_PER_CPU_THREAD], %g3
510 membar #StoreStore
511 stx %g3, [%g1 + GR_SNAP_THREAD] 509 stx %g3, [%g1 + GR_SNAP_THREAD]
512 retry 510 retry
513 511