[SPARC64]: Avoid membar instructions in delay slots.

In particular, avoid membar instructions in the delay
slot of a jmpl instruction.

UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51

The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.

If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.

We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.

Signed-off-by: David S. Miller <davem@davemloft.net>

2 files changed, 6 insertions, 3 deletions

diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
index 9c5222075da9..8fc413cb6acd 100644
--- a/arch/sparc64/mm/init.c
+++ b/arch/sparc64/mm/init.c
@@ -136,8 +136,9 @@ static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
                              "or        %%g1, %0, %%g1\n\t"
                              "casx      [%2], %%g7, %%g1\n\t"
                              "cmp       %%g7, %%g1\n\t"
+                             "membar    #StoreLoad | #StoreStore\n\t"
                              "bne,pn    %%xcc, 1b\n\t"
-                             " membar   #StoreLoad | #StoreStore"
+                             " nop"
                              : /* no outputs */
                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
                              : "g1", "g7");
@@ -157,8 +158,9 @@ static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long c
                              " andn     %%g7, %1, %%g1\n\t"
                              "casx      [%2], %%g7, %%g1\n\t"
                              "cmp       %%g7, %%g1\n\t"
+                             "membar    #StoreLoad | #StoreStore\n\t"
                              "bne,pn    %%xcc, 1b\n\t"
-                             " membar   #StoreLoad | #StoreStore\n"
+                             " nop\n"
                              "2:"
                              : /* no outputs */
                              : "r" (cpu), "r" (mask), "r" (&page->flags),
diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S
index 7a0934321010..7a2431d3abc7 100644
--- a/arch/sparc64/mm/ultra.S
+++ b/arch/sparc64/mm/ultra.S
@@ -266,8 +266,9 @@ __cheetah_flush_tlb_pending:	/* 22 insns */
          andn           %o3, 1, %o3
         stxa            %g0, [%o3] ASI_IMMU_DEMAP
 2:      stxa            %g0, [%o3] ASI_DMMU_DEMAP       
+        membar          #Sync
         brnz,pt         %o1, 1b
-         membar         #Sync
+         nop
         stxa            %g2, [%o4] ASI_DMMU
         flush           %g6
         wrpr            %g0, 0, %tl