[SPARC64]: Remove most limitations to kernel image size.

Currently kernel images are limited to 8MB in size, and this causes
problems especially when enabling features that take up a lot of
kernel image space such as lockdep.

The code now will align the kernel image size up to 4MB and map that
many locked TLB entries.  So, the only practical limitation is the
number of available locked TLB entries which is 16 on Cheetah and 64
on pre-Cheetah sparc64 cpus.  Niagara cpus don't actually have hw
locked TLB entry support.  Rather, the hypervisor transparently
provides support for "locked" TLB entries since it runs with physical
addressing and does the initial TLB miss processing.

Fully utilizing this change requires some help from SILO, a patch for
which will be submitted to the maintainer.  Essentially, SILO will
only currently map up to 8MB for the kernel image and that needs to be
increased.

Note that neither this patch nor the SILO bits will help with network
booting.  The openfirmware code will only map up to a certain amount
of kernel image during a network boot and there isn't much we can to
about that other than to implemented a layered network booting
facility.  Solaris has this, and calls it "wanboot" and we may
implement something similar at some point.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 14 insertions, 24 deletions

diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
index b5c30416fdac..466fd6cffac9 100644
--- a/arch/sparc64/mm/init.c
+++ b/arch/sparc64/mm/init.c
@@ -166,7 +166,7 @@ unsigned long sparc64_kern_pri_context __read_mostly;
 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 unsigned long sparc64_kern_sec_context __read_mostly;
 
-int bigkernel = 0;
+int num_kernel_image_mappings;
 
 #ifdef CONFIG_DEBUG_DCFLUSH
 atomic_t dcpage_flushes = ATOMIC_INIT(0);
@@ -572,7 +572,7 @@ static unsigned long kern_large_tte(unsigned long paddr);
 static void __init remap_kernel(void)
 {
         unsigned long phys_page, tte_vaddr, tte_data;
-        int tlb_ent = sparc64_highest_locked_tlbent();
+        int i, tlb_ent = sparc64_highest_locked_tlbent();
 
         tte_vaddr = (unsigned long) KERNBASE;
         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
@@ -582,27 +582,20 @@ static void __init remap_kernel(void)
 
         /* Now lock us into the TLBs via Hypervisor or OBP. */
         if (tlb_type == hypervisor) {
-                hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
-                hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
-                if (bigkernel) {
-                        tte_vaddr += 0x400000;
-                        tte_data += 0x400000;
+                for (i = 0; i < num_kernel_image_mappings; i++) {
                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
+                        tte_vaddr += 0x400000;
+                        tte_data += 0x400000;
                 }
         } else {
-                prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
-                prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
-                if (bigkernel) {
-                        tlb_ent -= 1;
-                        prom_dtlb_load(tlb_ent,
-                                       tte_data + 0x400000, 
-                                       tte_vaddr + 0x400000);
-                        prom_itlb_load(tlb_ent,
-                                       tte_data + 0x400000, 
-                                       tte_vaddr + 0x400000);
+                for (i = 0; i < num_kernel_image_mappings; i++) {
+                        prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
+                        prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
+                        tte_vaddr += 0x400000;
+                        tte_data += 0x400000;
                 }
-                sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
+                sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
         }
         if (tlb_type == cheetah_plus) {
                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
@@ -1352,12 +1345,9 @@ void __init paging_init(void)
         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
 
         real_end = (unsigned long)_end;
-        if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
-                bigkernel = 1;
-        if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
-                prom_printf("paging_init: Kernel > 8MB, too large.\n");
-                prom_halt();
-        }
+        num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
+        printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
+               num_kernel_image_mappings);
 
         /* Set kernel pgd to upper alias so physical page computations
          * work.