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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/sparc64/mm
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/sparc64/mm')
-rw-r--r--arch/sparc64/mm/Makefile10
-rw-r--r--arch/sparc64/mm/extable.c80
-rw-r--r--arch/sparc64/mm/fault.c527
-rw-r--r--arch/sparc64/mm/generic.c182
-rw-r--r--arch/sparc64/mm/hugetlbpage.c310
-rw-r--r--arch/sparc64/mm/init.c1769
-rw-r--r--arch/sparc64/mm/tlb.c151
-rw-r--r--arch/sparc64/mm/ultra.S583
8 files changed, 3612 insertions, 0 deletions
diff --git a/arch/sparc64/mm/Makefile b/arch/sparc64/mm/Makefile
new file mode 100644
index 000000000000..cda87333a77b
--- /dev/null
+++ b/arch/sparc64/mm/Makefile
@@ -0,0 +1,10 @@
1# $Id: Makefile,v 1.8 2000/12/14 22:57:25 davem Exp $
2# Makefile for the linux Sparc64-specific parts of the memory manager.
3#
4
5EXTRA_AFLAGS := -ansi
6EXTRA_CFLAGS := -Werror
7
8obj-y := ultra.o tlb.o fault.o init.o generic.o extable.o
9
10obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
diff --git a/arch/sparc64/mm/extable.c b/arch/sparc64/mm/extable.c
new file mode 100644
index 000000000000..ec334297ff4f
--- /dev/null
+++ b/arch/sparc64/mm/extable.c
@@ -0,0 +1,80 @@
1/*
2 * linux/arch/sparc64/mm/extable.c
3 */
4
5#include <linux/config.h>
6#include <linux/module.h>
7#include <asm/uaccess.h>
8
9extern const struct exception_table_entry __start___ex_table[];
10extern const struct exception_table_entry __stop___ex_table[];
11
12void sort_extable(struct exception_table_entry *start,
13 struct exception_table_entry *finish)
14{
15}
16
17/* Caller knows they are in a range if ret->fixup == 0 */
18const struct exception_table_entry *
19search_extable(const struct exception_table_entry *start,
20 const struct exception_table_entry *last,
21 unsigned long value)
22{
23 const struct exception_table_entry *walk;
24
25 /* Single insn entries are encoded as:
26 * word 1: insn address
27 * word 2: fixup code address
28 *
29 * Range entries are encoded as:
30 * word 1: first insn address
31 * word 2: 0
32 * word 3: last insn address + 4 bytes
33 * word 4: fixup code address
34 *
35 * See asm/uaccess.h for more details.
36 */
37
38 /* 1. Try to find an exact match. */
39 for (walk = start; walk <= last; walk++) {
40 if (walk->fixup == 0) {
41 /* A range entry, skip both parts. */
42 walk++;
43 continue;
44 }
45
46 if (walk->insn == value)
47 return walk;
48 }
49
50 /* 2. Try to find a range match. */
51 for (walk = start; walk <= (last - 1); walk++) {
52 if (walk->fixup)
53 continue;
54
55 if (walk[0].insn <= value && walk[1].insn > value)
56 return walk;
57
58 walk++;
59 }
60
61 return NULL;
62}
63
64/* Special extable search, which handles ranges. Returns fixup */
65unsigned long search_extables_range(unsigned long addr, unsigned long *g2)
66{
67 const struct exception_table_entry *entry;
68
69 entry = search_exception_tables(addr);
70 if (!entry)
71 return 0;
72
73 /* Inside range? Fix g2 and return correct fixup */
74 if (!entry->fixup) {
75 *g2 = (addr - entry->insn) / 4;
76 return (entry + 1)->fixup;
77 }
78
79 return entry->fixup;
80}
diff --git a/arch/sparc64/mm/fault.c b/arch/sparc64/mm/fault.c
new file mode 100644
index 000000000000..3ffee7b51aed
--- /dev/null
+++ b/arch/sparc64/mm/fault.c
@@ -0,0 +1,527 @@
1/* $Id: fault.c,v 1.59 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/fault.c: Page fault handlers for the 64-bit Sparc.
3 *
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz)
6 */
7
8#include <asm/head.h>
9
10#include <linux/string.h>
11#include <linux/types.h>
12#include <linux/sched.h>
13#include <linux/ptrace.h>
14#include <linux/mman.h>
15#include <linux/signal.h>
16#include <linux/mm.h>
17#include <linux/module.h>
18#include <linux/smp_lock.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21
22#include <asm/page.h>
23#include <asm/pgtable.h>
24#include <asm/openprom.h>
25#include <asm/oplib.h>
26#include <asm/uaccess.h>
27#include <asm/asi.h>
28#include <asm/lsu.h>
29#include <asm/sections.h>
30#include <asm/kdebug.h>
31
32#define ELEMENTS(arr) (sizeof (arr)/sizeof (arr[0]))
33
34extern struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
35
36/*
37 * To debug kernel during syscall entry.
38 */
39void syscall_trace_entry(struct pt_regs *regs)
40{
41 printk("scall entry: %s[%d]/cpu%d: %d\n", current->comm, current->pid, smp_processor_id(), (int) regs->u_regs[UREG_G1]);
42}
43
44/*
45 * To debug kernel during syscall exit.
46 */
47void syscall_trace_exit(struct pt_regs *regs)
48{
49 printk("scall exit: %s[%d]/cpu%d: %d\n", current->comm, current->pid, smp_processor_id(), (int) regs->u_regs[UREG_G1]);
50}
51
52/*
53 * To debug kernel to catch accesses to certain virtual/physical addresses.
54 * Mode = 0 selects physical watchpoints, mode = 1 selects virtual watchpoints.
55 * flags = VM_READ watches memread accesses, flags = VM_WRITE watches memwrite accesses.
56 * Caller passes in a 64bit aligned addr, with mask set to the bytes that need to be
57 * watched. This is only useful on a single cpu machine for now. After the watchpoint
58 * is detected, the process causing it will be killed, thus preventing an infinite loop.
59 */
60void set_brkpt(unsigned long addr, unsigned char mask, int flags, int mode)
61{
62 unsigned long lsubits;
63
64 __asm__ __volatile__("ldxa [%%g0] %1, %0"
65 : "=r" (lsubits)
66 : "i" (ASI_LSU_CONTROL));
67 lsubits &= ~(LSU_CONTROL_PM | LSU_CONTROL_VM |
68 LSU_CONTROL_PR | LSU_CONTROL_VR |
69 LSU_CONTROL_PW | LSU_CONTROL_VW);
70
71 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
72 "membar #Sync"
73 : /* no outputs */
74 : "r" (addr), "r" (mode ? VIRT_WATCHPOINT : PHYS_WATCHPOINT),
75 "i" (ASI_DMMU));
76
77 lsubits |= ((unsigned long)mask << (mode ? 25 : 33));
78 if (flags & VM_READ)
79 lsubits |= (mode ? LSU_CONTROL_VR : LSU_CONTROL_PR);
80 if (flags & VM_WRITE)
81 lsubits |= (mode ? LSU_CONTROL_VW : LSU_CONTROL_PW);
82 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
83 "membar #Sync"
84 : /* no outputs */
85 : "r" (lsubits), "i" (ASI_LSU_CONTROL)
86 : "memory");
87}
88
89/* Nice, simple, prom library does all the sweating for us. ;) */
90unsigned long __init prom_probe_memory (void)
91{
92 register struct linux_mlist_p1275 *mlist;
93 register unsigned long bytes, base_paddr, tally;
94 register int i;
95
96 i = 0;
97 mlist = *prom_meminfo()->p1275_available;
98 bytes = tally = mlist->num_bytes;
99 base_paddr = mlist->start_adr;
100
101 sp_banks[0].base_addr = base_paddr;
102 sp_banks[0].num_bytes = bytes;
103
104 while (mlist->theres_more != (void *) 0) {
105 i++;
106 mlist = mlist->theres_more;
107 bytes = mlist->num_bytes;
108 tally += bytes;
109 if (i >= SPARC_PHYS_BANKS-1) {
110 printk ("The machine has more banks than "
111 "this kernel can support\n"
112 "Increase the SPARC_PHYS_BANKS "
113 "setting (currently %d)\n",
114 SPARC_PHYS_BANKS);
115 i = SPARC_PHYS_BANKS-1;
116 break;
117 }
118
119 sp_banks[i].base_addr = mlist->start_adr;
120 sp_banks[i].num_bytes = mlist->num_bytes;
121 }
122
123 i++;
124 sp_banks[i].base_addr = 0xdeadbeefbeefdeadUL;
125 sp_banks[i].num_bytes = 0;
126
127 /* Now mask all bank sizes on a page boundary, it is all we can
128 * use anyways.
129 */
130 for (i = 0; sp_banks[i].num_bytes != 0; i++)
131 sp_banks[i].num_bytes &= PAGE_MASK;
132
133 return tally;
134}
135
136static void unhandled_fault(unsigned long address, struct task_struct *tsk,
137 struct pt_regs *regs)
138{
139 if ((unsigned long) address < PAGE_SIZE) {
140 printk(KERN_ALERT "Unable to handle kernel NULL "
141 "pointer dereference\n");
142 } else {
143 printk(KERN_ALERT "Unable to handle kernel paging request "
144 "at virtual address %016lx\n", (unsigned long)address);
145 }
146 printk(KERN_ALERT "tsk->{mm,active_mm}->context = %016lx\n",
147 (tsk->mm ?
148 CTX_HWBITS(tsk->mm->context) :
149 CTX_HWBITS(tsk->active_mm->context)));
150 printk(KERN_ALERT "tsk->{mm,active_mm}->pgd = %016lx\n",
151 (tsk->mm ? (unsigned long) tsk->mm->pgd :
152 (unsigned long) tsk->active_mm->pgd));
153 if (notify_die(DIE_GPF, "general protection fault", regs,
154 0, 0, SIGSEGV) == NOTIFY_STOP)
155 return;
156 die_if_kernel("Oops", regs);
157}
158
159static void bad_kernel_pc(struct pt_regs *regs)
160{
161 unsigned long *ksp;
162
163 printk(KERN_CRIT "OOPS: Bogus kernel PC [%016lx] in fault handler\n",
164 regs->tpc);
165 __asm__("mov %%sp, %0" : "=r" (ksp));
166 show_stack(current, ksp);
167 unhandled_fault(regs->tpc, current, regs);
168}
169
170/*
171 * We now make sure that mmap_sem is held in all paths that call
172 * this. Additionally, to prevent kswapd from ripping ptes from
173 * under us, raise interrupts around the time that we look at the
174 * pte, kswapd will have to wait to get his smp ipi response from
175 * us. This saves us having to get page_table_lock.
176 */
177static unsigned int get_user_insn(unsigned long tpc)
178{
179 pgd_t *pgdp = pgd_offset(current->mm, tpc);
180 pud_t *pudp;
181 pmd_t *pmdp;
182 pte_t *ptep, pte;
183 unsigned long pa;
184 u32 insn = 0;
185 unsigned long pstate;
186
187 if (pgd_none(*pgdp))
188 goto outret;
189 pudp = pud_offset(pgdp, tpc);
190 if (pud_none(*pudp))
191 goto outret;
192 pmdp = pmd_offset(pudp, tpc);
193 if (pmd_none(*pmdp))
194 goto outret;
195
196 /* This disables preemption for us as well. */
197 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
198 __asm__ __volatile__("wrpr %0, %1, %%pstate"
199 : : "r" (pstate), "i" (PSTATE_IE));
200 ptep = pte_offset_map(pmdp, tpc);
201 pte = *ptep;
202 if (!pte_present(pte))
203 goto out;
204
205 pa = (pte_val(pte) & _PAGE_PADDR);
206 pa += (tpc & ~PAGE_MASK);
207
208 /* Use phys bypass so we don't pollute dtlb/dcache. */
209 __asm__ __volatile__("lduwa [%1] %2, %0"
210 : "=r" (insn)
211 : "r" (pa), "i" (ASI_PHYS_USE_EC));
212
213out:
214 pte_unmap(ptep);
215 __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
216outret:
217 return insn;
218}
219
220extern unsigned long compute_effective_address(struct pt_regs *, unsigned int, unsigned int);
221
222static void do_fault_siginfo(int code, int sig, struct pt_regs *regs,
223 unsigned int insn, int fault_code)
224{
225 siginfo_t info;
226
227 info.si_code = code;
228 info.si_signo = sig;
229 info.si_errno = 0;
230 if (fault_code & FAULT_CODE_ITLB)
231 info.si_addr = (void __user *) regs->tpc;
232 else
233 info.si_addr = (void __user *)
234 compute_effective_address(regs, insn, 0);
235 info.si_trapno = 0;
236 force_sig_info(sig, &info, current);
237}
238
239extern int handle_ldf_stq(u32, struct pt_regs *);
240extern int handle_ld_nf(u32, struct pt_regs *);
241
242static unsigned int get_fault_insn(struct pt_regs *regs, unsigned int insn)
243{
244 if (!insn) {
245 if (!regs->tpc || (regs->tpc & 0x3))
246 return 0;
247 if (regs->tstate & TSTATE_PRIV) {
248 insn = *(unsigned int *) regs->tpc;
249 } else {
250 insn = get_user_insn(regs->tpc);
251 }
252 }
253 return insn;
254}
255
256static void do_kernel_fault(struct pt_regs *regs, int si_code, int fault_code,
257 unsigned int insn, unsigned long address)
258{
259 unsigned long g2;
260 unsigned char asi = ASI_P;
261
262 if ((!insn) && (regs->tstate & TSTATE_PRIV))
263 goto cannot_handle;
264
265 /* If user insn could be read (thus insn is zero), that
266 * is fine. We will just gun down the process with a signal
267 * in that case.
268 */
269
270 if (!(fault_code & (FAULT_CODE_WRITE|FAULT_CODE_ITLB)) &&
271 (insn & 0xc0800000) == 0xc0800000) {
272 if (insn & 0x2000)
273 asi = (regs->tstate >> 24);
274 else
275 asi = (insn >> 5);
276 if ((asi & 0xf2) == 0x82) {
277 if (insn & 0x1000000) {
278 handle_ldf_stq(insn, regs);
279 } else {
280 /* This was a non-faulting load. Just clear the
281 * destination register(s) and continue with the next
282 * instruction. -jj
283 */
284 handle_ld_nf(insn, regs);
285 }
286 return;
287 }
288 }
289
290 g2 = regs->u_regs[UREG_G2];
291
292 /* Is this in ex_table? */
293 if (regs->tstate & TSTATE_PRIV) {
294 unsigned long fixup;
295
296 if (asi == ASI_P && (insn & 0xc0800000) == 0xc0800000) {
297 if (insn & 0x2000)
298 asi = (regs->tstate >> 24);
299 else
300 asi = (insn >> 5);
301 }
302
303 /* Look in asi.h: All _S asis have LS bit set */
304 if ((asi & 0x1) &&
305 (fixup = search_extables_range(regs->tpc, &g2))) {
306 regs->tpc = fixup;
307 regs->tnpc = regs->tpc + 4;
308 regs->u_regs[UREG_G2] = g2;
309 return;
310 }
311 } else {
312 /* The si_code was set to make clear whether
313 * this was a SEGV_MAPERR or SEGV_ACCERR fault.
314 */
315 do_fault_siginfo(si_code, SIGSEGV, regs, insn, fault_code);
316 return;
317 }
318
319cannot_handle:
320 unhandled_fault (address, current, regs);
321}
322
323asmlinkage void do_sparc64_fault(struct pt_regs *regs)
324{
325 struct mm_struct *mm = current->mm;
326 struct vm_area_struct *vma;
327 unsigned int insn = 0;
328 int si_code, fault_code;
329 unsigned long address;
330
331 fault_code = get_thread_fault_code();
332
333 if (notify_die(DIE_PAGE_FAULT, "page_fault", regs,
334 fault_code, 0, SIGSEGV) == NOTIFY_STOP)
335 return;
336
337 si_code = SEGV_MAPERR;
338 address = current_thread_info()->fault_address;
339
340 if ((fault_code & FAULT_CODE_ITLB) &&
341 (fault_code & FAULT_CODE_DTLB))
342 BUG();
343
344 if (regs->tstate & TSTATE_PRIV) {
345 unsigned long tpc = regs->tpc;
346
347 /* Sanity check the PC. */
348 if ((tpc >= KERNBASE && tpc < (unsigned long) _etext) ||
349 (tpc >= MODULES_VADDR && tpc < MODULES_END)) {
350 /* Valid, no problems... */
351 } else {
352 bad_kernel_pc(regs);
353 return;
354 }
355 }
356
357 /*
358 * If we're in an interrupt or have no user
359 * context, we must not take the fault..
360 */
361 if (in_atomic() || !mm)
362 goto intr_or_no_mm;
363
364 if (test_thread_flag(TIF_32BIT)) {
365 if (!(regs->tstate & TSTATE_PRIV))
366 regs->tpc &= 0xffffffff;
367 address &= 0xffffffff;
368 }
369
370 if (!down_read_trylock(&mm->mmap_sem)) {
371 if ((regs->tstate & TSTATE_PRIV) &&
372 !search_exception_tables(regs->tpc)) {
373 insn = get_fault_insn(regs, insn);
374 goto handle_kernel_fault;
375 }
376 down_read(&mm->mmap_sem);
377 }
378
379 vma = find_vma(mm, address);
380 if (!vma)
381 goto bad_area;
382
383 /* Pure DTLB misses do not tell us whether the fault causing
384 * load/store/atomic was a write or not, it only says that there
385 * was no match. So in such a case we (carefully) read the
386 * instruction to try and figure this out. It's an optimization
387 * so it's ok if we can't do this.
388 *
389 * Special hack, window spill/fill knows the exact fault type.
390 */
391 if (((fault_code &
392 (FAULT_CODE_DTLB | FAULT_CODE_WRITE | FAULT_CODE_WINFIXUP)) == FAULT_CODE_DTLB) &&
393 (vma->vm_flags & VM_WRITE) != 0) {
394 insn = get_fault_insn(regs, 0);
395 if (!insn)
396 goto continue_fault;
397 if ((insn & 0xc0200000) == 0xc0200000 &&
398 (insn & 0x1780000) != 0x1680000) {
399 /* Don't bother updating thread struct value,
400 * because update_mmu_cache only cares which tlb
401 * the access came from.
402 */
403 fault_code |= FAULT_CODE_WRITE;
404 }
405 }
406continue_fault:
407
408 if (vma->vm_start <= address)
409 goto good_area;
410 if (!(vma->vm_flags & VM_GROWSDOWN))
411 goto bad_area;
412 if (!(fault_code & FAULT_CODE_WRITE)) {
413 /* Non-faulting loads shouldn't expand stack. */
414 insn = get_fault_insn(regs, insn);
415 if ((insn & 0xc0800000) == 0xc0800000) {
416 unsigned char asi;
417
418 if (insn & 0x2000)
419 asi = (regs->tstate >> 24);
420 else
421 asi = (insn >> 5);
422 if ((asi & 0xf2) == 0x82)
423 goto bad_area;
424 }
425 }
426 if (expand_stack(vma, address))
427 goto bad_area;
428 /*
429 * Ok, we have a good vm_area for this memory access, so
430 * we can handle it..
431 */
432good_area:
433 si_code = SEGV_ACCERR;
434
435 /* If we took a ITLB miss on a non-executable page, catch
436 * that here.
437 */
438 if ((fault_code & FAULT_CODE_ITLB) && !(vma->vm_flags & VM_EXEC)) {
439 BUG_ON(address != regs->tpc);
440 BUG_ON(regs->tstate & TSTATE_PRIV);
441 goto bad_area;
442 }
443
444 if (fault_code & FAULT_CODE_WRITE) {
445 if (!(vma->vm_flags & VM_WRITE))
446 goto bad_area;
447
448 /* Spitfire has an icache which does not snoop
449 * processor stores. Later processors do...
450 */
451 if (tlb_type == spitfire &&
452 (vma->vm_flags & VM_EXEC) != 0 &&
453 vma->vm_file != NULL)
454 set_thread_fault_code(fault_code |
455 FAULT_CODE_BLKCOMMIT);
456 } else {
457 /* Allow reads even for write-only mappings */
458 if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
459 goto bad_area;
460 }
461
462 switch (handle_mm_fault(mm, vma, address, (fault_code & FAULT_CODE_WRITE))) {
463 case VM_FAULT_MINOR:
464 current->min_flt++;
465 break;
466 case VM_FAULT_MAJOR:
467 current->maj_flt++;
468 break;
469 case VM_FAULT_SIGBUS:
470 goto do_sigbus;
471 case VM_FAULT_OOM:
472 goto out_of_memory;
473 default:
474 BUG();
475 }
476
477 up_read(&mm->mmap_sem);
478 goto fault_done;
479
480 /*
481 * Something tried to access memory that isn't in our memory map..
482 * Fix it, but check if it's kernel or user first..
483 */
484bad_area:
485 insn = get_fault_insn(regs, insn);
486 up_read(&mm->mmap_sem);
487
488handle_kernel_fault:
489 do_kernel_fault(regs, si_code, fault_code, insn, address);
490
491 goto fault_done;
492
493/*
494 * We ran out of memory, or some other thing happened to us that made
495 * us unable to handle the page fault gracefully.
496 */
497out_of_memory:
498 insn = get_fault_insn(regs, insn);
499 up_read(&mm->mmap_sem);
500 printk("VM: killing process %s\n", current->comm);
501 if (!(regs->tstate & TSTATE_PRIV))
502 do_exit(SIGKILL);
503 goto handle_kernel_fault;
504
505intr_or_no_mm:
506 insn = get_fault_insn(regs, 0);
507 goto handle_kernel_fault;
508
509do_sigbus:
510 insn = get_fault_insn(regs, insn);
511 up_read(&mm->mmap_sem);
512
513 /*
514 * Send a sigbus, regardless of whether we were in kernel
515 * or user mode.
516 */
517 do_fault_siginfo(BUS_ADRERR, SIGBUS, regs, insn, fault_code);
518
519 /* Kernel mode? Handle exceptions or die */
520 if (regs->tstate & TSTATE_PRIV)
521 goto handle_kernel_fault;
522
523fault_done:
524 /* These values are no longer needed, clear them. */
525 set_thread_fault_code(0);
526 current_thread_info()->fault_address = 0;
527}
diff --git a/arch/sparc64/mm/generic.c b/arch/sparc64/mm/generic.c
new file mode 100644
index 000000000000..6b31f6117a95
--- /dev/null
+++ b/arch/sparc64/mm/generic.c
@@ -0,0 +1,182 @@
1/* $Id: generic.c,v 1.18 2001/12/21 04:56:15 davem Exp $
2 * generic.c: Generic Sparc mm routines that are not dependent upon
3 * MMU type but are Sparc specific.
4 *
5 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
6 */
7
8#include <linux/kernel.h>
9#include <linux/mm.h>
10#include <linux/swap.h>
11#include <linux/pagemap.h>
12
13#include <asm/pgalloc.h>
14#include <asm/pgtable.h>
15#include <asm/page.h>
16#include <asm/tlbflush.h>
17
18/* Remap IO memory, the same way as remap_pfn_range(), but use
19 * the obio memory space.
20 *
21 * They use a pgprot that sets PAGE_IO and does not check the
22 * mem_map table as this is independent of normal memory.
23 */
24static inline void io_remap_pte_range(struct mm_struct *mm, pte_t * pte,
25 unsigned long address,
26 unsigned long size,
27 unsigned long offset, pgprot_t prot,
28 int space)
29{
30 unsigned long end;
31
32 /* clear hack bit that was used as a write_combine side-effect flag */
33 offset &= ~0x1UL;
34 address &= ~PMD_MASK;
35 end = address + size;
36 if (end > PMD_SIZE)
37 end = PMD_SIZE;
38 do {
39 pte_t entry;
40 unsigned long curend = address + PAGE_SIZE;
41
42 entry = mk_pte_io(offset, prot, space);
43 if (!(address & 0xffff)) {
44 if (!(address & 0x3fffff) && !(offset & 0x3ffffe) && end >= address + 0x400000) {
45 entry = mk_pte_io(offset,
46 __pgprot(pgprot_val (prot) | _PAGE_SZ4MB),
47 space);
48 curend = address + 0x400000;
49 offset += 0x400000;
50 } else if (!(address & 0x7ffff) && !(offset & 0x7fffe) && end >= address + 0x80000) {
51 entry = mk_pte_io(offset,
52 __pgprot(pgprot_val (prot) | _PAGE_SZ512K),
53 space);
54 curend = address + 0x80000;
55 offset += 0x80000;
56 } else if (!(offset & 0xfffe) && end >= address + 0x10000) {
57 entry = mk_pte_io(offset,
58 __pgprot(pgprot_val (prot) | _PAGE_SZ64K),
59 space);
60 curend = address + 0x10000;
61 offset += 0x10000;
62 } else
63 offset += PAGE_SIZE;
64 } else
65 offset += PAGE_SIZE;
66
67 do {
68 BUG_ON(!pte_none(*pte));
69 set_pte_at(mm, address, pte, entry);
70 address += PAGE_SIZE;
71 pte++;
72 } while (address < curend);
73 } while (address < end);
74}
75
76static inline int io_remap_pmd_range(struct mm_struct *mm, pmd_t * pmd, unsigned long address, unsigned long size,
77 unsigned long offset, pgprot_t prot, int space)
78{
79 unsigned long end;
80
81 address &= ~PGDIR_MASK;
82 end = address + size;
83 if (end > PGDIR_SIZE)
84 end = PGDIR_SIZE;
85 offset -= address;
86 do {
87 pte_t * pte = pte_alloc_map(mm, pmd, address);
88 if (!pte)
89 return -ENOMEM;
90 io_remap_pte_range(mm, pte, address, end - address, address + offset, prot, space);
91 pte_unmap(pte);
92 address = (address + PMD_SIZE) & PMD_MASK;
93 pmd++;
94 } while (address < end);
95 return 0;
96}
97
98static inline int io_remap_pud_range(struct mm_struct *mm, pud_t * pud, unsigned long address, unsigned long size,
99 unsigned long offset, pgprot_t prot, int space)
100{
101 unsigned long end;
102
103 address &= ~PUD_MASK;
104 end = address + size;
105 if (end > PUD_SIZE)
106 end = PUD_SIZE;
107 offset -= address;
108 do {
109 pmd_t *pmd = pmd_alloc(mm, pud, address);
110 if (!pud)
111 return -ENOMEM;
112 io_remap_pmd_range(mm, pmd, address, end - address, address + offset, prot, space);
113 address = (address + PUD_SIZE) & PUD_MASK;
114 pud++;
115 } while (address < end);
116 return 0;
117}
118
119int io_remap_page_range(struct vm_area_struct *vma, unsigned long from, unsigned long offset, unsigned long size, pgprot_t prot, int space)
120{
121 int error = 0;
122 pgd_t * dir;
123 unsigned long beg = from;
124 unsigned long end = from + size;
125 struct mm_struct *mm = vma->vm_mm;
126
127 prot = __pgprot(pg_iobits);
128 offset -= from;
129 dir = pgd_offset(mm, from);
130 flush_cache_range(vma, beg, end);
131
132 spin_lock(&mm->page_table_lock);
133 while (from < end) {
134 pud_t *pud = pud_alloc(mm, dir, from);
135 error = -ENOMEM;
136 if (!pud)
137 break;
138 error = io_remap_pud_range(mm, pud, from, end - from, offset + from, prot, space);
139 if (error)
140 break;
141 from = (from + PGDIR_SIZE) & PGDIR_MASK;
142 dir++;
143 }
144 flush_tlb_range(vma, beg, end);
145 spin_unlock(&mm->page_table_lock);
146
147 return error;
148}
149
150int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
151 unsigned long pfn, unsigned long size, pgprot_t prot)
152{
153 int error = 0;
154 pgd_t * dir;
155 unsigned long beg = from;
156 unsigned long end = from + size;
157 struct mm_struct *mm = vma->vm_mm;
158 int space = GET_IOSPACE(pfn);
159 unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT;
160
161 prot = __pgprot(pg_iobits);
162 offset -= from;
163 dir = pgd_offset(mm, from);
164 flush_cache_range(vma, beg, end);
165
166 spin_lock(&mm->page_table_lock);
167 while (from < end) {
168 pud_t *pud = pud_alloc(current->mm, dir, from);
169 error = -ENOMEM;
170 if (!pud)
171 break;
172 error = io_remap_pud_range(mm, pud, from, end - from, offset + from, prot, space);
173 if (error)
174 break;
175 from = (from + PGDIR_SIZE) & PGDIR_MASK;
176 dir++;
177 }
178 flush_tlb_range(vma, beg, end);
179 spin_unlock(&mm->page_table_lock);
180
181 return error;
182}
diff --git a/arch/sparc64/mm/hugetlbpage.c b/arch/sparc64/mm/hugetlbpage.c
new file mode 100644
index 000000000000..5a1f831b2de1
--- /dev/null
+++ b/arch/sparc64/mm/hugetlbpage.c
@@ -0,0 +1,310 @@
1/*
2 * SPARC64 Huge TLB page support.
3 *
4 * Copyright (C) 2002, 2003 David S. Miller (davem@redhat.com)
5 */
6
7#include <linux/config.h>
8#include <linux/init.h>
9#include <linux/module.h>
10#include <linux/fs.h>
11#include <linux/mm.h>
12#include <linux/hugetlb.h>
13#include <linux/pagemap.h>
14#include <linux/smp_lock.h>
15#include <linux/slab.h>
16#include <linux/sysctl.h>
17
18#include <asm/mman.h>
19#include <asm/pgalloc.h>
20#include <asm/tlb.h>
21#include <asm/tlbflush.h>
22#include <asm/cacheflush.h>
23#include <asm/mmu_context.h>
24
25static pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr)
26{
27 pgd_t *pgd;
28 pud_t *pud;
29 pmd_t *pmd;
30 pte_t *pte = NULL;
31
32 pgd = pgd_offset(mm, addr);
33 if (pgd) {
34 pud = pud_offset(pgd, addr);
35 if (pud) {
36 pmd = pmd_alloc(mm, pud, addr);
37 if (pmd)
38 pte = pte_alloc_map(mm, pmd, addr);
39 }
40 }
41 return pte;
42}
43
44static pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
45{
46 pgd_t *pgd;
47 pud_t *pud;
48 pmd_t *pmd;
49 pte_t *pte = NULL;
50
51 pgd = pgd_offset(mm, addr);
52 if (pgd) {
53 pud = pud_offset(pgd, addr);
54 if (pud) {
55 pmd = pmd_offset(pud, addr);
56 if (pmd)
57 pte = pte_offset_map(pmd, addr);
58 }
59 }
60 return pte;
61}
62
63#define mk_pte_huge(entry) do { pte_val(entry) |= _PAGE_SZHUGE; } while (0)
64
65static void set_huge_pte(struct mm_struct *mm, struct vm_area_struct *vma,
66 unsigned long addr,
67 struct page *page, pte_t * page_table, int write_access)
68{
69 unsigned long i;
70 pte_t entry;
71
72 add_mm_counter(mm, rss, HPAGE_SIZE / PAGE_SIZE);
73
74 if (write_access)
75 entry = pte_mkwrite(pte_mkdirty(mk_pte(page,
76 vma->vm_page_prot)));
77 else
78 entry = pte_wrprotect(mk_pte(page, vma->vm_page_prot));
79 entry = pte_mkyoung(entry);
80 mk_pte_huge(entry);
81
82 for (i = 0; i < (1 << HUGETLB_PAGE_ORDER); i++) {
83 set_pte_at(mm, addr, page_table, entry);
84 page_table++;
85 addr += PAGE_SIZE;
86
87 pte_val(entry) += PAGE_SIZE;
88 }
89}
90
91/*
92 * This function checks for proper alignment of input addr and len parameters.
93 */
94int is_aligned_hugepage_range(unsigned long addr, unsigned long len)
95{
96 if (len & ~HPAGE_MASK)
97 return -EINVAL;
98 if (addr & ~HPAGE_MASK)
99 return -EINVAL;
100 return 0;
101}
102
103int copy_hugetlb_page_range(struct mm_struct *dst, struct mm_struct *src,
104 struct vm_area_struct *vma)
105{
106 pte_t *src_pte, *dst_pte, entry;
107 struct page *ptepage;
108 unsigned long addr = vma->vm_start;
109 unsigned long end = vma->vm_end;
110 int i;
111
112 while (addr < end) {
113 dst_pte = huge_pte_alloc(dst, addr);
114 if (!dst_pte)
115 goto nomem;
116 src_pte = huge_pte_offset(src, addr);
117 BUG_ON(!src_pte || pte_none(*src_pte));
118 entry = *src_pte;
119 ptepage = pte_page(entry);
120 get_page(ptepage);
121 for (i = 0; i < (1 << HUGETLB_PAGE_ORDER); i++) {
122 set_pte_at(dst, addr, dst_pte, entry);
123 pte_val(entry) += PAGE_SIZE;
124 dst_pte++;
125 addr += PAGE_SIZE;
126 }
127 add_mm_counter(dst, rss, HPAGE_SIZE / PAGE_SIZE);
128 }
129 return 0;
130
131nomem:
132 return -ENOMEM;
133}
134
135int follow_hugetlb_page(struct mm_struct *mm, struct vm_area_struct *vma,
136 struct page **pages, struct vm_area_struct **vmas,
137 unsigned long *position, int *length, int i)
138{
139 unsigned long vaddr = *position;
140 int remainder = *length;
141
142 WARN_ON(!is_vm_hugetlb_page(vma));
143
144 while (vaddr < vma->vm_end && remainder) {
145 if (pages) {
146 pte_t *pte;
147 struct page *page;
148
149 pte = huge_pte_offset(mm, vaddr);
150
151 /* hugetlb should be locked, and hence, prefaulted */
152 BUG_ON(!pte || pte_none(*pte));
153
154 page = pte_page(*pte);
155
156 WARN_ON(!PageCompound(page));
157
158 get_page(page);
159 pages[i] = page;
160 }
161
162 if (vmas)
163 vmas[i] = vma;
164
165 vaddr += PAGE_SIZE;
166 --remainder;
167 ++i;
168 }
169
170 *length = remainder;
171 *position = vaddr;
172
173 return i;
174}
175
176struct page *follow_huge_addr(struct mm_struct *mm,
177 unsigned long address, int write)
178{
179 return ERR_PTR(-EINVAL);
180}
181
182int pmd_huge(pmd_t pmd)
183{
184 return 0;
185}
186
187struct page *follow_huge_pmd(struct mm_struct *mm, unsigned long address,
188 pmd_t *pmd, int write)
189{
190 return NULL;
191}
192
193void unmap_hugepage_range(struct vm_area_struct *vma,
194 unsigned long start, unsigned long end)
195{
196 struct mm_struct *mm = vma->vm_mm;
197 unsigned long address;
198 pte_t *pte;
199 struct page *page;
200 int i;
201
202 BUG_ON(start & (HPAGE_SIZE - 1));
203 BUG_ON(end & (HPAGE_SIZE - 1));
204
205 for (address = start; address < end; address += HPAGE_SIZE) {
206 pte = huge_pte_offset(mm, address);
207 BUG_ON(!pte);
208 if (pte_none(*pte))
209 continue;
210 page = pte_page(*pte);
211 put_page(page);
212 for (i = 0; i < (1 << HUGETLB_PAGE_ORDER); i++) {
213 pte_clear(mm, address+(i*PAGE_SIZE), pte);
214 pte++;
215 }
216 }
217 add_mm_counter(mm, rss, -((end - start) >> PAGE_SHIFT));
218 flush_tlb_range(vma, start, end);
219}
220
221static void context_reload(void *__data)
222{
223 struct mm_struct *mm = __data;
224
225 if (mm == current->mm)
226 load_secondary_context(mm);
227}
228
229int hugetlb_prefault(struct address_space *mapping, struct vm_area_struct *vma)
230{
231 struct mm_struct *mm = current->mm;
232 unsigned long addr;
233 int ret = 0;
234
235 /* On UltraSPARC-III+ and later, configure the second half of
236 * the Data-TLB for huge pages.
237 */
238 if (tlb_type == cheetah_plus) {
239 unsigned long ctx;
240
241 spin_lock(&ctx_alloc_lock);
242 ctx = mm->context.sparc64_ctx_val;
243 ctx &= ~CTX_PGSZ_MASK;
244 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
245 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
246
247 if (ctx != mm->context.sparc64_ctx_val) {
248 /* When changing the page size fields, we
249 * must perform a context flush so that no
250 * stale entries match. This flush must
251 * occur with the original context register
252 * settings.
253 */
254 do_flush_tlb_mm(mm);
255
256 /* Reload the context register of all processors
257 * also executing in this address space.
258 */
259 mm->context.sparc64_ctx_val = ctx;
260 on_each_cpu(context_reload, mm, 0, 0);
261 }
262 spin_unlock(&ctx_alloc_lock);
263 }
264
265 BUG_ON(vma->vm_start & ~HPAGE_MASK);
266 BUG_ON(vma->vm_end & ~HPAGE_MASK);
267
268 spin_lock(&mm->page_table_lock);
269 for (addr = vma->vm_start; addr < vma->vm_end; addr += HPAGE_SIZE) {
270 unsigned long idx;
271 pte_t *pte = huge_pte_alloc(mm, addr);
272 struct page *page;
273
274 if (!pte) {
275 ret = -ENOMEM;
276 goto out;
277 }
278 if (!pte_none(*pte))
279 continue;
280
281 idx = ((addr - vma->vm_start) >> HPAGE_SHIFT)
282 + (vma->vm_pgoff >> (HPAGE_SHIFT - PAGE_SHIFT));
283 page = find_get_page(mapping, idx);
284 if (!page) {
285 /* charge the fs quota first */
286 if (hugetlb_get_quota(mapping)) {
287 ret = -ENOMEM;
288 goto out;
289 }
290 page = alloc_huge_page();
291 if (!page) {
292 hugetlb_put_quota(mapping);
293 ret = -ENOMEM;
294 goto out;
295 }
296 ret = add_to_page_cache(page, mapping, idx, GFP_ATOMIC);
297 if (! ret) {
298 unlock_page(page);
299 } else {
300 hugetlb_put_quota(mapping);
301 free_huge_page(page);
302 goto out;
303 }
304 }
305 set_huge_pte(mm, vma, addr, page, pte, vma->vm_flags & VM_WRITE);
306 }
307out:
308 spin_unlock(&mm->page_table_lock);
309 return ret;
310}
diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
new file mode 100644
index 000000000000..89022ccaa75b
--- /dev/null
+++ b/arch/sparc64/mm/init.c
@@ -0,0 +1,1769 @@
1/* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/config.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
16#include <linux/slab.h>
17#include <linux/initrd.h>
18#include <linux/swap.h>
19#include <linux/pagemap.h>
20#include <linux/fs.h>
21#include <linux/seq_file.h>
22
23#include <asm/head.h>
24#include <asm/system.h>
25#include <asm/page.h>
26#include <asm/pgalloc.h>
27#include <asm/pgtable.h>
28#include <asm/oplib.h>
29#include <asm/iommu.h>
30#include <asm/io.h>
31#include <asm/uaccess.h>
32#include <asm/mmu_context.h>
33#include <asm/tlbflush.h>
34#include <asm/dma.h>
35#include <asm/starfire.h>
36#include <asm/tlb.h>
37#include <asm/spitfire.h>
38#include <asm/sections.h>
39
40extern void device_scan(void);
41
42struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
43
44unsigned long *sparc64_valid_addr_bitmap;
45
46/* Ugly, but necessary... -DaveM */
47unsigned long phys_base;
48unsigned long kern_base;
49unsigned long kern_size;
50unsigned long pfn_base;
51
52/* This is even uglier. We have a problem where the kernel may not be
53 * located at phys_base. However, initial __alloc_bootmem() calls need to
54 * be adjusted to be within the 4-8Megs that the kernel is mapped to, else
55 * those page mappings wont work. Things are ok after inherit_prom_mappings
56 * is called though. Dave says he'll clean this up some other time.
57 * -- BenC
58 */
59static unsigned long bootmap_base;
60
61/* get_new_mmu_context() uses "cache + 1". */
62DEFINE_SPINLOCK(ctx_alloc_lock);
63unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
64#define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
65unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
66
67/* References to special section boundaries */
68extern char _start[], _end[];
69
70/* Initial ramdisk setup */
71extern unsigned long sparc_ramdisk_image64;
72extern unsigned int sparc_ramdisk_image;
73extern unsigned int sparc_ramdisk_size;
74
75struct page *mem_map_zero;
76
77int bigkernel = 0;
78
79/* XXX Tune this... */
80#define PGT_CACHE_LOW 25
81#define PGT_CACHE_HIGH 50
82
83void check_pgt_cache(void)
84{
85 preempt_disable();
86 if (pgtable_cache_size > PGT_CACHE_HIGH) {
87 do {
88 if (pgd_quicklist)
89 free_pgd_slow(get_pgd_fast());
90 if (pte_quicklist[0])
91 free_pte_slow(pte_alloc_one_fast(NULL, 0));
92 if (pte_quicklist[1])
93 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
94 } while (pgtable_cache_size > PGT_CACHE_LOW);
95 }
96 preempt_enable();
97}
98
99#ifdef CONFIG_DEBUG_DCFLUSH
100atomic_t dcpage_flushes = ATOMIC_INIT(0);
101#ifdef CONFIG_SMP
102atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
103#endif
104#endif
105
106__inline__ void flush_dcache_page_impl(struct page *page)
107{
108#ifdef CONFIG_DEBUG_DCFLUSH
109 atomic_inc(&dcpage_flushes);
110#endif
111
112#ifdef DCACHE_ALIASING_POSSIBLE
113 __flush_dcache_page(page_address(page),
114 ((tlb_type == spitfire) &&
115 page_mapping(page) != NULL));
116#else
117 if (page_mapping(page) != NULL &&
118 tlb_type == spitfire)
119 __flush_icache_page(__pa(page_address(page)));
120#endif
121}
122
123#define PG_dcache_dirty PG_arch_1
124
125#define dcache_dirty_cpu(page) \
126 (((page)->flags >> 24) & (NR_CPUS - 1UL))
127
128static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
129{
130 unsigned long mask = this_cpu;
131 unsigned long non_cpu_bits = ~((NR_CPUS - 1UL) << 24UL);
132 mask = (mask << 24) | (1UL << PG_dcache_dirty);
133 __asm__ __volatile__("1:\n\t"
134 "ldx [%2], %%g7\n\t"
135 "and %%g7, %1, %%g1\n\t"
136 "or %%g1, %0, %%g1\n\t"
137 "casx [%2], %%g7, %%g1\n\t"
138 "cmp %%g7, %%g1\n\t"
139 "bne,pn %%xcc, 1b\n\t"
140 " membar #StoreLoad | #StoreStore"
141 : /* no outputs */
142 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
143 : "g1", "g7");
144}
145
146static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
147{
148 unsigned long mask = (1UL << PG_dcache_dirty);
149
150 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
151 "1:\n\t"
152 "ldx [%2], %%g7\n\t"
153 "srlx %%g7, 24, %%g1\n\t"
154 "and %%g1, %3, %%g1\n\t"
155 "cmp %%g1, %0\n\t"
156 "bne,pn %%icc, 2f\n\t"
157 " andn %%g7, %1, %%g1\n\t"
158 "casx [%2], %%g7, %%g1\n\t"
159 "cmp %%g7, %%g1\n\t"
160 "bne,pn %%xcc, 1b\n\t"
161 " membar #StoreLoad | #StoreStore\n"
162 "2:"
163 : /* no outputs */
164 : "r" (cpu), "r" (mask), "r" (&page->flags),
165 "i" (NR_CPUS - 1UL)
166 : "g1", "g7");
167}
168
169extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code);
170
171void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
172{
173 struct page *page;
174 unsigned long pfn;
175 unsigned long pg_flags;
176
177 pfn = pte_pfn(pte);
178 if (pfn_valid(pfn) &&
179 (page = pfn_to_page(pfn), page_mapping(page)) &&
180 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
181 int cpu = ((pg_flags >> 24) & (NR_CPUS - 1UL));
182 int this_cpu = get_cpu();
183
184 /* This is just to optimize away some function calls
185 * in the SMP case.
186 */
187 if (cpu == this_cpu)
188 flush_dcache_page_impl(page);
189 else
190 smp_flush_dcache_page_impl(page, cpu);
191
192 clear_dcache_dirty_cpu(page, cpu);
193
194 put_cpu();
195 }
196
197 if (get_thread_fault_code())
198 __update_mmu_cache(CTX_NRBITS(vma->vm_mm->context),
199 address, pte, get_thread_fault_code());
200}
201
202void flush_dcache_page(struct page *page)
203{
204 struct address_space *mapping = page_mapping(page);
205 int dirty = test_bit(PG_dcache_dirty, &page->flags);
206 int dirty_cpu = dcache_dirty_cpu(page);
207 int this_cpu = get_cpu();
208
209 if (mapping && !mapping_mapped(mapping)) {
210 if (dirty) {
211 if (dirty_cpu == this_cpu)
212 goto out;
213 smp_flush_dcache_page_impl(page, dirty_cpu);
214 }
215 set_dcache_dirty(page, this_cpu);
216 } else {
217 /* We could delay the flush for the !page_mapping
218 * case too. But that case is for exec env/arg
219 * pages and those are %99 certainly going to get
220 * faulted into the tlb (and thus flushed) anyways.
221 */
222 flush_dcache_page_impl(page);
223 }
224
225out:
226 put_cpu();
227}
228
229void flush_icache_range(unsigned long start, unsigned long end)
230{
231 /* Cheetah has coherent I-cache. */
232 if (tlb_type == spitfire) {
233 unsigned long kaddr;
234
235 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
236 __flush_icache_page(__get_phys(kaddr));
237 }
238}
239
240unsigned long page_to_pfn(struct page *page)
241{
242 return (unsigned long) ((page - mem_map) + pfn_base);
243}
244
245struct page *pfn_to_page(unsigned long pfn)
246{
247 return (mem_map + (pfn - pfn_base));
248}
249
250void show_mem(void)
251{
252 printk("Mem-info:\n");
253 show_free_areas();
254 printk("Free swap: %6ldkB\n",
255 nr_swap_pages << (PAGE_SHIFT-10));
256 printk("%ld pages of RAM\n", num_physpages);
257 printk("%d free pages\n", nr_free_pages());
258 printk("%d pages in page table cache\n",pgtable_cache_size);
259}
260
261void mmu_info(struct seq_file *m)
262{
263 if (tlb_type == cheetah)
264 seq_printf(m, "MMU Type\t: Cheetah\n");
265 else if (tlb_type == cheetah_plus)
266 seq_printf(m, "MMU Type\t: Cheetah+\n");
267 else if (tlb_type == spitfire)
268 seq_printf(m, "MMU Type\t: Spitfire\n");
269 else
270 seq_printf(m, "MMU Type\t: ???\n");
271
272#ifdef CONFIG_DEBUG_DCFLUSH
273 seq_printf(m, "DCPageFlushes\t: %d\n",
274 atomic_read(&dcpage_flushes));
275#ifdef CONFIG_SMP
276 seq_printf(m, "DCPageFlushesXC\t: %d\n",
277 atomic_read(&dcpage_flushes_xcall));
278#endif /* CONFIG_SMP */
279#endif /* CONFIG_DEBUG_DCFLUSH */
280}
281
282struct linux_prom_translation {
283 unsigned long virt;
284 unsigned long size;
285 unsigned long data;
286};
287
288extern unsigned long prom_boot_page;
289extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
290extern int prom_get_mmu_ihandle(void);
291extern void register_prom_callbacks(void);
292
293/* Exported for SMP bootup purposes. */
294unsigned long kern_locked_tte_data;
295
296void __init early_pgtable_allocfail(char *type)
297{
298 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
299 prom_halt();
300}
301
302#define BASE_PAGE_SIZE 8192
303static pmd_t *prompmd;
304
305/*
306 * Translate PROM's mapping we capture at boot time into physical address.
307 * The second parameter is only set from prom_callback() invocations.
308 */
309unsigned long prom_virt_to_phys(unsigned long promva, int *error)
310{
311 pmd_t *pmdp = prompmd + ((promva >> 23) & 0x7ff);
312 pte_t *ptep;
313 unsigned long base;
314
315 if (pmd_none(*pmdp)) {
316 if (error)
317 *error = 1;
318 return(0);
319 }
320 ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff);
321 if (!pte_present(*ptep)) {
322 if (error)
323 *error = 1;
324 return(0);
325 }
326 if (error) {
327 *error = 0;
328 return(pte_val(*ptep));
329 }
330 base = pte_val(*ptep) & _PAGE_PADDR;
331 return(base + (promva & (BASE_PAGE_SIZE - 1)));
332}
333
334static void inherit_prom_mappings(void)
335{
336 struct linux_prom_translation *trans;
337 unsigned long phys_page, tte_vaddr, tte_data;
338 void (*remap_func)(unsigned long, unsigned long, int);
339 pmd_t *pmdp;
340 pte_t *ptep;
341 int node, n, i, tsz;
342 extern unsigned int obp_iaddr_patch[2], obp_daddr_patch[2];
343
344 node = prom_finddevice("/virtual-memory");
345 n = prom_getproplen(node, "translations");
346 if (n == 0 || n == -1) {
347 prom_printf("Couldn't get translation property\n");
348 prom_halt();
349 }
350 n += 5 * sizeof(struct linux_prom_translation);
351 for (tsz = 1; tsz < n; tsz <<= 1)
352 /* empty */;
353 trans = __alloc_bootmem(tsz, SMP_CACHE_BYTES, bootmap_base);
354 if (trans == NULL) {
355 prom_printf("inherit_prom_mappings: Cannot alloc translations.\n");
356 prom_halt();
357 }
358 memset(trans, 0, tsz);
359
360 if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
361 prom_printf("Couldn't get translation property\n");
362 prom_halt();
363 }
364 n = n / sizeof(*trans);
365
366 /*
367 * The obp translations are saved based on 8k pagesize, since obp can
368 * use a mixture of pagesizes. Misses to the 0xf0000000 - 0x100000000,
369 * ie obp range, are handled in entry.S and do not use the vpte scheme
370 * (see rant in inherit_locked_prom_mappings()).
371 */
372#define OBP_PMD_SIZE 2048
373 prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE, bootmap_base);
374 if (prompmd == NULL)
375 early_pgtable_allocfail("pmd");
376 memset(prompmd, 0, OBP_PMD_SIZE);
377 for (i = 0; i < n; i++) {
378 unsigned long vaddr;
379
380 if (trans[i].virt >= LOW_OBP_ADDRESS && trans[i].virt < HI_OBP_ADDRESS) {
381 for (vaddr = trans[i].virt;
382 ((vaddr < trans[i].virt + trans[i].size) &&
383 (vaddr < HI_OBP_ADDRESS));
384 vaddr += BASE_PAGE_SIZE) {
385 unsigned long val;
386
387 pmdp = prompmd + ((vaddr >> 23) & 0x7ff);
388 if (pmd_none(*pmdp)) {
389 ptep = __alloc_bootmem(BASE_PAGE_SIZE,
390 BASE_PAGE_SIZE,
391 bootmap_base);
392 if (ptep == NULL)
393 early_pgtable_allocfail("pte");
394 memset(ptep, 0, BASE_PAGE_SIZE);
395 pmd_set(pmdp, ptep);
396 }
397 ptep = (pte_t *)__pmd_page(*pmdp) +
398 ((vaddr >> 13) & 0x3ff);
399
400 val = trans[i].data;
401
402 /* Clear diag TTE bits. */
403 if (tlb_type == spitfire)
404 val &= ~0x0003fe0000000000UL;
405
406 set_pte_at(&init_mm, vaddr,
407 ptep, __pte(val | _PAGE_MODIFIED));
408 trans[i].data += BASE_PAGE_SIZE;
409 }
410 }
411 }
412 phys_page = __pa(prompmd);
413 obp_iaddr_patch[0] |= (phys_page >> 10);
414 obp_iaddr_patch[1] |= (phys_page & 0x3ff);
415 flushi((long)&obp_iaddr_patch[0]);
416 obp_daddr_patch[0] |= (phys_page >> 10);
417 obp_daddr_patch[1] |= (phys_page & 0x3ff);
418 flushi((long)&obp_daddr_patch[0]);
419
420 /* Now fixup OBP's idea about where we really are mapped. */
421 prom_printf("Remapping the kernel... ");
422
423 /* Spitfire Errata #32 workaround */
424 /* NOTE: Using plain zero for the context value is
425 * correct here, we are not using the Linux trap
426 * tables yet so we should not use the special
427 * UltraSPARC-III+ page size encodings yet.
428 */
429 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
430 "flush %%g6"
431 : /* No outputs */
432 : "r" (0), "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
433
434 switch (tlb_type) {
435 default:
436 case spitfire:
437 phys_page = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
438 break;
439
440 case cheetah:
441 case cheetah_plus:
442 phys_page = cheetah_get_litlb_data(sparc64_highest_locked_tlbent());
443 break;
444 };
445
446 phys_page &= _PAGE_PADDR;
447 phys_page += ((unsigned long)&prom_boot_page -
448 (unsigned long)KERNBASE);
449
450 if (tlb_type == spitfire) {
451 /* Lock this into i/d tlb entry 59 */
452 __asm__ __volatile__(
453 "stxa %%g0, [%2] %3\n\t"
454 "stxa %0, [%1] %4\n\t"
455 "membar #Sync\n\t"
456 "flush %%g6\n\t"
457 "stxa %%g0, [%2] %5\n\t"
458 "stxa %0, [%1] %6\n\t"
459 "membar #Sync\n\t"
460 "flush %%g6"
461 : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
462 _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
463 "r" (59 << 3), "r" (TLB_TAG_ACCESS),
464 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
465 "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
466 : "memory");
467 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
468 /* Lock this into i/d tlb-0 entry 11 */
469 __asm__ __volatile__(
470 "stxa %%g0, [%2] %3\n\t"
471 "stxa %0, [%1] %4\n\t"
472 "membar #Sync\n\t"
473 "flush %%g6\n\t"
474 "stxa %%g0, [%2] %5\n\t"
475 "stxa %0, [%1] %6\n\t"
476 "membar #Sync\n\t"
477 "flush %%g6"
478 : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
479 _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
480 "r" ((0 << 16) | (11 << 3)), "r" (TLB_TAG_ACCESS),
481 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
482 "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
483 : "memory");
484 } else {
485 /* Implement me :-) */
486 BUG();
487 }
488
489 tte_vaddr = (unsigned long) KERNBASE;
490
491 /* Spitfire Errata #32 workaround */
492 /* NOTE: Using plain zero for the context value is
493 * correct here, we are not using the Linux trap
494 * tables yet so we should not use the special
495 * UltraSPARC-III+ page size encodings yet.
496 */
497 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
498 "flush %%g6"
499 : /* No outputs */
500 : "r" (0),
501 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
502
503 if (tlb_type == spitfire)
504 tte_data = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
505 else
506 tte_data = cheetah_get_ldtlb_data(sparc64_highest_locked_tlbent());
507
508 kern_locked_tte_data = tte_data;
509
510 remap_func = (void *) ((unsigned long) &prom_remap -
511 (unsigned long) &prom_boot_page);
512
513
514 /* Spitfire Errata #32 workaround */
515 /* NOTE: Using plain zero for the context value is
516 * correct here, we are not using the Linux trap
517 * tables yet so we should not use the special
518 * UltraSPARC-III+ page size encodings yet.
519 */
520 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
521 "flush %%g6"
522 : /* No outputs */
523 : "r" (0),
524 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
525
526 remap_func((tlb_type == spitfire ?
527 (spitfire_get_dtlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR) :
528 (cheetah_get_litlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR)),
529 (unsigned long) KERNBASE,
530 prom_get_mmu_ihandle());
531
532 if (bigkernel)
533 remap_func(((tte_data + 0x400000) & _PAGE_PADDR),
534 (unsigned long) KERNBASE + 0x400000, prom_get_mmu_ihandle());
535
536 /* Flush out that temporary mapping. */
537 spitfire_flush_dtlb_nucleus_page(0x0);
538 spitfire_flush_itlb_nucleus_page(0x0);
539
540 /* Now lock us back into the TLBs via OBP. */
541 prom_dtlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
542 prom_itlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
543 if (bigkernel) {
544 prom_dtlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
545 tte_vaddr + 0x400000);
546 prom_itlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
547 tte_vaddr + 0x400000);
548 }
549
550 /* Re-read translations property. */
551 if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
552 prom_printf("Couldn't get translation property\n");
553 prom_halt();
554 }
555 n = n / sizeof(*trans);
556
557 for (i = 0; i < n; i++) {
558 unsigned long vaddr = trans[i].virt;
559 unsigned long size = trans[i].size;
560
561 if (vaddr < 0xf0000000UL) {
562 unsigned long avoid_start = (unsigned long) KERNBASE;
563 unsigned long avoid_end = avoid_start + (4 * 1024 * 1024);
564
565 if (bigkernel)
566 avoid_end += (4 * 1024 * 1024);
567 if (vaddr < avoid_start) {
568 unsigned long top = vaddr + size;
569
570 if (top > avoid_start)
571 top = avoid_start;
572 prom_unmap(top - vaddr, vaddr);
573 }
574 if ((vaddr + size) > avoid_end) {
575 unsigned long bottom = vaddr;
576
577 if (bottom < avoid_end)
578 bottom = avoid_end;
579 prom_unmap((vaddr + size) - bottom, bottom);
580 }
581 }
582 }
583
584 prom_printf("done.\n");
585
586 register_prom_callbacks();
587}
588
589/* The OBP specifications for sun4u mark 0xfffffffc00000000 and
590 * upwards as reserved for use by the firmware (I wonder if this
591 * will be the same on Cheetah...). We use this virtual address
592 * range for the VPTE table mappings of the nucleus so we need
593 * to zap them when we enter the PROM. -DaveM
594 */
595static void __flush_nucleus_vptes(void)
596{
597 unsigned long prom_reserved_base = 0xfffffffc00000000UL;
598 int i;
599
600 /* Only DTLB must be checked for VPTE entries. */
601 if (tlb_type == spitfire) {
602 for (i = 0; i < 63; i++) {
603 unsigned long tag;
604
605 /* Spitfire Errata #32 workaround */
606 /* NOTE: Always runs on spitfire, so no cheetah+
607 * page size encodings.
608 */
609 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
610 "flush %%g6"
611 : /* No outputs */
612 : "r" (0),
613 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
614
615 tag = spitfire_get_dtlb_tag(i);
616 if (((tag & ~(PAGE_MASK)) == 0) &&
617 ((tag & (PAGE_MASK)) >= prom_reserved_base)) {
618 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
619 "membar #Sync"
620 : /* no outputs */
621 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
622 spitfire_put_dtlb_data(i, 0x0UL);
623 }
624 }
625 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
626 for (i = 0; i < 512; i++) {
627 unsigned long tag = cheetah_get_dtlb_tag(i, 2);
628
629 if ((tag & ~PAGE_MASK) == 0 &&
630 (tag & PAGE_MASK) >= prom_reserved_base) {
631 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
632 "membar #Sync"
633 : /* no outputs */
634 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
635 cheetah_put_dtlb_data(i, 0x0UL, 2);
636 }
637
638 if (tlb_type != cheetah_plus)
639 continue;
640
641 tag = cheetah_get_dtlb_tag(i, 3);
642
643 if ((tag & ~PAGE_MASK) == 0 &&
644 (tag & PAGE_MASK) >= prom_reserved_base) {
645 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
646 "membar #Sync"
647 : /* no outputs */
648 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
649 cheetah_put_dtlb_data(i, 0x0UL, 3);
650 }
651 }
652 } else {
653 /* Implement me :-) */
654 BUG();
655 }
656}
657
658static int prom_ditlb_set;
659struct prom_tlb_entry {
660 int tlb_ent;
661 unsigned long tlb_tag;
662 unsigned long tlb_data;
663};
664struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
665
666void prom_world(int enter)
667{
668 unsigned long pstate;
669 int i;
670
671 if (!enter)
672 set_fs((mm_segment_t) { get_thread_current_ds() });
673
674 if (!prom_ditlb_set)
675 return;
676
677 /* Make sure the following runs atomically. */
678 __asm__ __volatile__("flushw\n\t"
679 "rdpr %%pstate, %0\n\t"
680 "wrpr %0, %1, %%pstate"
681 : "=r" (pstate)
682 : "i" (PSTATE_IE));
683
684 if (enter) {
685 /* Kick out nucleus VPTEs. */
686 __flush_nucleus_vptes();
687
688 /* Install PROM world. */
689 for (i = 0; i < 16; i++) {
690 if (prom_dtlb[i].tlb_ent != -1) {
691 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
692 "membar #Sync"
693 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
694 "i" (ASI_DMMU));
695 if (tlb_type == spitfire)
696 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
697 prom_dtlb[i].tlb_data);
698 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
699 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
700 prom_dtlb[i].tlb_data);
701 }
702 if (prom_itlb[i].tlb_ent != -1) {
703 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
704 "membar #Sync"
705 : : "r" (prom_itlb[i].tlb_tag),
706 "r" (TLB_TAG_ACCESS),
707 "i" (ASI_IMMU));
708 if (tlb_type == spitfire)
709 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
710 prom_itlb[i].tlb_data);
711 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
712 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
713 prom_itlb[i].tlb_data);
714 }
715 }
716 } else {
717 for (i = 0; i < 16; i++) {
718 if (prom_dtlb[i].tlb_ent != -1) {
719 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
720 "membar #Sync"
721 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
722 if (tlb_type == spitfire)
723 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
724 else
725 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
726 }
727 if (prom_itlb[i].tlb_ent != -1) {
728 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
729 "membar #Sync"
730 : : "r" (TLB_TAG_ACCESS),
731 "i" (ASI_IMMU));
732 if (tlb_type == spitfire)
733 spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
734 else
735 cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
736 }
737 }
738 }
739 __asm__ __volatile__("wrpr %0, 0, %%pstate"
740 : : "r" (pstate));
741}
742
743void inherit_locked_prom_mappings(int save_p)
744{
745 int i;
746 int dtlb_seen = 0;
747 int itlb_seen = 0;
748
749 /* Fucking losing PROM has more mappings in the TLB, but
750 * it (conveniently) fails to mention any of these in the
751 * translations property. The only ones that matter are
752 * the locked PROM tlb entries, so we impose the following
753 * irrecovable rule on the PROM, it is allowed 8 locked
754 * entries in the ITLB and 8 in the DTLB.
755 *
756 * Supposedly the upper 16GB of the address space is
757 * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
758 * SOMEWHERE!!!!!!!!!!!!!!!!! Furthermore the entire interface
759 * used between the client program and the firmware on sun5
760 * systems to coordinate mmu mappings is also COMPLETELY
761 * UNDOCUMENTED!!!!!! Thanks S(t)un!
762 */
763 if (save_p) {
764 for (i = 0; i < 16; i++) {
765 prom_itlb[i].tlb_ent = -1;
766 prom_dtlb[i].tlb_ent = -1;
767 }
768 }
769 if (tlb_type == spitfire) {
770 int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel;
771 for (i = 0; i < high; i++) {
772 unsigned long data;
773
774 /* Spitfire Errata #32 workaround */
775 /* NOTE: Always runs on spitfire, so no cheetah+
776 * page size encodings.
777 */
778 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
779 "flush %%g6"
780 : /* No outputs */
781 : "r" (0),
782 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
783
784 data = spitfire_get_dtlb_data(i);
785 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
786 unsigned long tag;
787
788 /* Spitfire Errata #32 workaround */
789 /* NOTE: Always runs on spitfire, so no
790 * cheetah+ page size encodings.
791 */
792 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
793 "flush %%g6"
794 : /* No outputs */
795 : "r" (0),
796 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
797
798 tag = spitfire_get_dtlb_tag(i);
799 if (save_p) {
800 prom_dtlb[dtlb_seen].tlb_ent = i;
801 prom_dtlb[dtlb_seen].tlb_tag = tag;
802 prom_dtlb[dtlb_seen].tlb_data = data;
803 }
804 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
805 "membar #Sync"
806 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
807 spitfire_put_dtlb_data(i, 0x0UL);
808
809 dtlb_seen++;
810 if (dtlb_seen > 15)
811 break;
812 }
813 }
814
815 for (i = 0; i < high; i++) {
816 unsigned long data;
817
818 /* Spitfire Errata #32 workaround */
819 /* NOTE: Always runs on spitfire, so no
820 * cheetah+ page size encodings.
821 */
822 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
823 "flush %%g6"
824 : /* No outputs */
825 : "r" (0),
826 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
827
828 data = spitfire_get_itlb_data(i);
829 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
830 unsigned long tag;
831
832 /* Spitfire Errata #32 workaround */
833 /* NOTE: Always runs on spitfire, so no
834 * cheetah+ page size encodings.
835 */
836 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
837 "flush %%g6"
838 : /* No outputs */
839 : "r" (0),
840 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
841
842 tag = spitfire_get_itlb_tag(i);
843 if (save_p) {
844 prom_itlb[itlb_seen].tlb_ent = i;
845 prom_itlb[itlb_seen].tlb_tag = tag;
846 prom_itlb[itlb_seen].tlb_data = data;
847 }
848 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
849 "membar #Sync"
850 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
851 spitfire_put_itlb_data(i, 0x0UL);
852
853 itlb_seen++;
854 if (itlb_seen > 15)
855 break;
856 }
857 }
858 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
859 int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel;
860
861 for (i = 0; i < high; i++) {
862 unsigned long data;
863
864 data = cheetah_get_ldtlb_data(i);
865 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
866 unsigned long tag;
867
868 tag = cheetah_get_ldtlb_tag(i);
869 if (save_p) {
870 prom_dtlb[dtlb_seen].tlb_ent = i;
871 prom_dtlb[dtlb_seen].tlb_tag = tag;
872 prom_dtlb[dtlb_seen].tlb_data = data;
873 }
874 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
875 "membar #Sync"
876 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
877 cheetah_put_ldtlb_data(i, 0x0UL);
878
879 dtlb_seen++;
880 if (dtlb_seen > 15)
881 break;
882 }
883 }
884
885 for (i = 0; i < high; i++) {
886 unsigned long data;
887
888 data = cheetah_get_litlb_data(i);
889 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
890 unsigned long tag;
891
892 tag = cheetah_get_litlb_tag(i);
893 if (save_p) {
894 prom_itlb[itlb_seen].tlb_ent = i;
895 prom_itlb[itlb_seen].tlb_tag = tag;
896 prom_itlb[itlb_seen].tlb_data = data;
897 }
898 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
899 "membar #Sync"
900 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
901 cheetah_put_litlb_data(i, 0x0UL);
902
903 itlb_seen++;
904 if (itlb_seen > 15)
905 break;
906 }
907 }
908 } else {
909 /* Implement me :-) */
910 BUG();
911 }
912 if (save_p)
913 prom_ditlb_set = 1;
914}
915
916/* Give PROM back his world, done during reboots... */
917void prom_reload_locked(void)
918{
919 int i;
920
921 for (i = 0; i < 16; i++) {
922 if (prom_dtlb[i].tlb_ent != -1) {
923 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
924 "membar #Sync"
925 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
926 "i" (ASI_DMMU));
927 if (tlb_type == spitfire)
928 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
929 prom_dtlb[i].tlb_data);
930 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
931 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
932 prom_dtlb[i].tlb_data);
933 }
934
935 if (prom_itlb[i].tlb_ent != -1) {
936 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
937 "membar #Sync"
938 : : "r" (prom_itlb[i].tlb_tag),
939 "r" (TLB_TAG_ACCESS),
940 "i" (ASI_IMMU));
941 if (tlb_type == spitfire)
942 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
943 prom_itlb[i].tlb_data);
944 else
945 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
946 prom_itlb[i].tlb_data);
947 }
948 }
949}
950
951#ifdef DCACHE_ALIASING_POSSIBLE
952void __flush_dcache_range(unsigned long start, unsigned long end)
953{
954 unsigned long va;
955
956 if (tlb_type == spitfire) {
957 int n = 0;
958
959 for (va = start; va < end; va += 32) {
960 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
961 if (++n >= 512)
962 break;
963 }
964 } else {
965 start = __pa(start);
966 end = __pa(end);
967 for (va = start; va < end; va += 32)
968 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
969 "membar #Sync"
970 : /* no outputs */
971 : "r" (va),
972 "i" (ASI_DCACHE_INVALIDATE));
973 }
974}
975#endif /* DCACHE_ALIASING_POSSIBLE */
976
977/* If not locked, zap it. */
978void __flush_tlb_all(void)
979{
980 unsigned long pstate;
981 int i;
982
983 __asm__ __volatile__("flushw\n\t"
984 "rdpr %%pstate, %0\n\t"
985 "wrpr %0, %1, %%pstate"
986 : "=r" (pstate)
987 : "i" (PSTATE_IE));
988 if (tlb_type == spitfire) {
989 for (i = 0; i < 64; i++) {
990 /* Spitfire Errata #32 workaround */
991 /* NOTE: Always runs on spitfire, so no
992 * cheetah+ page size encodings.
993 */
994 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
995 "flush %%g6"
996 : /* No outputs */
997 : "r" (0),
998 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
999
1000 if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
1001 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1002 "membar #Sync"
1003 : /* no outputs */
1004 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1005 spitfire_put_dtlb_data(i, 0x0UL);
1006 }
1007
1008 /* Spitfire Errata #32 workaround */
1009 /* NOTE: Always runs on spitfire, so no
1010 * cheetah+ page size encodings.
1011 */
1012 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1013 "flush %%g6"
1014 : /* No outputs */
1015 : "r" (0),
1016 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1017
1018 if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
1019 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1020 "membar #Sync"
1021 : /* no outputs */
1022 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1023 spitfire_put_itlb_data(i, 0x0UL);
1024 }
1025 }
1026 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1027 cheetah_flush_dtlb_all();
1028 cheetah_flush_itlb_all();
1029 }
1030 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1031 : : "r" (pstate));
1032}
1033
1034/* Caller does TLB context flushing on local CPU if necessary.
1035 * The caller also ensures that CTX_VALID(mm->context) is false.
1036 *
1037 * We must be careful about boundary cases so that we never
1038 * let the user have CTX 0 (nucleus) or we ever use a CTX
1039 * version of zero (and thus NO_CONTEXT would not be caught
1040 * by version mis-match tests in mmu_context.h).
1041 */
1042void get_new_mmu_context(struct mm_struct *mm)
1043{
1044 unsigned long ctx, new_ctx;
1045 unsigned long orig_pgsz_bits;
1046
1047
1048 spin_lock(&ctx_alloc_lock);
1049 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
1050 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
1051 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
1052 if (new_ctx >= (1 << CTX_NR_BITS)) {
1053 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
1054 if (new_ctx >= ctx) {
1055 int i;
1056 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
1057 CTX_FIRST_VERSION;
1058 if (new_ctx == 1)
1059 new_ctx = CTX_FIRST_VERSION;
1060
1061 /* Don't call memset, for 16 entries that's just
1062 * plain silly...
1063 */
1064 mmu_context_bmap[0] = 3;
1065 mmu_context_bmap[1] = 0;
1066 mmu_context_bmap[2] = 0;
1067 mmu_context_bmap[3] = 0;
1068 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
1069 mmu_context_bmap[i + 0] = 0;
1070 mmu_context_bmap[i + 1] = 0;
1071 mmu_context_bmap[i + 2] = 0;
1072 mmu_context_bmap[i + 3] = 0;
1073 }
1074 goto out;
1075 }
1076 }
1077 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
1078 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
1079out:
1080 tlb_context_cache = new_ctx;
1081 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
1082 spin_unlock(&ctx_alloc_lock);
1083}
1084
1085#ifndef CONFIG_SMP
1086struct pgtable_cache_struct pgt_quicklists;
1087#endif
1088
1089/* OK, we have to color these pages. The page tables are accessed
1090 * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S
1091 * code, as well as by PAGE_OFFSET range direct-mapped addresses by
1092 * other parts of the kernel. By coloring, we make sure that the tlbmiss
1093 * fast handlers do not get data from old/garbage dcache lines that
1094 * correspond to an old/stale virtual address (user/kernel) that
1095 * previously mapped the pagetable page while accessing vpte range
1096 * addresses. The idea is that if the vpte color and PAGE_OFFSET range
1097 * color is the same, then when the kernel initializes the pagetable
1098 * using the later address range, accesses with the first address
1099 * range will see the newly initialized data rather than the garbage.
1100 */
1101#ifdef DCACHE_ALIASING_POSSIBLE
1102#define DC_ALIAS_SHIFT 1
1103#else
1104#define DC_ALIAS_SHIFT 0
1105#endif
1106pte_t *__pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
1107{
1108 struct page *page;
1109 unsigned long color;
1110
1111 {
1112 pte_t *ptep = pte_alloc_one_fast(mm, address);
1113
1114 if (ptep)
1115 return ptep;
1116 }
1117
1118 color = VPTE_COLOR(address);
1119 page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
1120 if (page) {
1121 unsigned long *to_free;
1122 unsigned long paddr;
1123 pte_t *pte;
1124
1125#ifdef DCACHE_ALIASING_POSSIBLE
1126 set_page_count(page, 1);
1127 ClearPageCompound(page);
1128
1129 set_page_count((page + 1), 1);
1130 ClearPageCompound(page + 1);
1131#endif
1132 paddr = (unsigned long) page_address(page);
1133 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1134
1135 if (!color) {
1136 pte = (pte_t *) paddr;
1137 to_free = (unsigned long *) (paddr + PAGE_SIZE);
1138 } else {
1139 pte = (pte_t *) (paddr + PAGE_SIZE);
1140 to_free = (unsigned long *) paddr;
1141 }
1142
1143#ifdef DCACHE_ALIASING_POSSIBLE
1144 /* Now free the other one up, adjust cache size. */
1145 preempt_disable();
1146 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1147 pte_quicklist[color ^ 0x1] = to_free;
1148 pgtable_cache_size++;
1149 preempt_enable();
1150#endif
1151
1152 return pte;
1153 }
1154 return NULL;
1155}
1156
1157void sparc_ultra_dump_itlb(void)
1158{
1159 int slot;
1160
1161 if (tlb_type == spitfire) {
1162 printk ("Contents of itlb: ");
1163 for (slot = 0; slot < 14; slot++) printk (" ");
1164 printk ("%2x:%016lx,%016lx\n",
1165 0,
1166 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1167 for (slot = 1; slot < 64; slot+=3) {
1168 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1169 slot,
1170 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1171 slot+1,
1172 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1173 slot+2,
1174 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1175 }
1176 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1177 printk ("Contents of itlb0:\n");
1178 for (slot = 0; slot < 16; slot+=2) {
1179 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1180 slot,
1181 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
1182 slot+1,
1183 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
1184 }
1185 printk ("Contents of itlb2:\n");
1186 for (slot = 0; slot < 128; slot+=2) {
1187 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1188 slot,
1189 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1190 slot+1,
1191 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1192 }
1193 }
1194}
1195
1196void sparc_ultra_dump_dtlb(void)
1197{
1198 int slot;
1199
1200 if (tlb_type == spitfire) {
1201 printk ("Contents of dtlb: ");
1202 for (slot = 0; slot < 14; slot++) printk (" ");
1203 printk ("%2x:%016lx,%016lx\n", 0,
1204 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1205 for (slot = 1; slot < 64; slot+=3) {
1206 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1207 slot,
1208 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1209 slot+1,
1210 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1211 slot+2,
1212 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1213 }
1214 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1215 printk ("Contents of dtlb0:\n");
1216 for (slot = 0; slot < 16; slot+=2) {
1217 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1218 slot,
1219 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1220 slot+1,
1221 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1222 }
1223 printk ("Contents of dtlb2:\n");
1224 for (slot = 0; slot < 512; slot+=2) {
1225 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1226 slot,
1227 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1228 slot+1,
1229 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1230 }
1231 if (tlb_type == cheetah_plus) {
1232 printk ("Contents of dtlb3:\n");
1233 for (slot = 0; slot < 512; slot+=2) {
1234 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1235 slot,
1236 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1237 slot+1,
1238 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1239 }
1240 }
1241 }
1242}
1243
1244extern unsigned long cmdline_memory_size;
1245
1246unsigned long __init bootmem_init(unsigned long *pages_avail)
1247{
1248 unsigned long bootmap_size, start_pfn, end_pfn;
1249 unsigned long end_of_phys_memory = 0UL;
1250 unsigned long bootmap_pfn, bytes_avail, size;
1251 int i;
1252
1253#ifdef CONFIG_DEBUG_BOOTMEM
1254 prom_printf("bootmem_init: Scan sp_banks, ");
1255#endif
1256
1257 bytes_avail = 0UL;
1258 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1259 end_of_phys_memory = sp_banks[i].base_addr +
1260 sp_banks[i].num_bytes;
1261 bytes_avail += sp_banks[i].num_bytes;
1262 if (cmdline_memory_size) {
1263 if (bytes_avail > cmdline_memory_size) {
1264 unsigned long slack = bytes_avail - cmdline_memory_size;
1265
1266 bytes_avail -= slack;
1267 end_of_phys_memory -= slack;
1268
1269 sp_banks[i].num_bytes -= slack;
1270 if (sp_banks[i].num_bytes == 0) {
1271 sp_banks[i].base_addr = 0xdeadbeef;
1272 } else {
1273 sp_banks[i+1].num_bytes = 0;
1274 sp_banks[i+1].base_addr = 0xdeadbeef;
1275 }
1276 break;
1277 }
1278 }
1279 }
1280
1281 *pages_avail = bytes_avail >> PAGE_SHIFT;
1282
1283 /* Start with page aligned address of last symbol in kernel
1284 * image. The kernel is hard mapped below PAGE_OFFSET in a
1285 * 4MB locked TLB translation.
1286 */
1287 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1288
1289 bootmap_pfn = start_pfn;
1290
1291 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1292
1293#ifdef CONFIG_BLK_DEV_INITRD
1294 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1295 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
1296 unsigned long ramdisk_image = sparc_ramdisk_image ?
1297 sparc_ramdisk_image : sparc_ramdisk_image64;
1298 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1299 ramdisk_image -= KERNBASE;
1300 initrd_start = ramdisk_image + phys_base;
1301 initrd_end = initrd_start + sparc_ramdisk_size;
1302 if (initrd_end > end_of_phys_memory) {
1303 printk(KERN_CRIT "initrd extends beyond end of memory "
1304 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1305 initrd_end, end_of_phys_memory);
1306 initrd_start = 0;
1307 }
1308 if (initrd_start) {
1309 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1310 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1311 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1312 }
1313 }
1314#endif
1315 /* Initialize the boot-time allocator. */
1316 max_pfn = max_low_pfn = end_pfn;
1317 min_low_pfn = pfn_base;
1318
1319#ifdef CONFIG_DEBUG_BOOTMEM
1320 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1321 min_low_pfn, bootmap_pfn, max_low_pfn);
1322#endif
1323 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1324
1325 bootmap_base = bootmap_pfn << PAGE_SHIFT;
1326
1327 /* Now register the available physical memory with the
1328 * allocator.
1329 */
1330 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1331#ifdef CONFIG_DEBUG_BOOTMEM
1332 prom_printf("free_bootmem(sp_banks:%d): base[%lx] size[%lx]\n",
1333 i, sp_banks[i].base_addr, sp_banks[i].num_bytes);
1334#endif
1335 free_bootmem(sp_banks[i].base_addr, sp_banks[i].num_bytes);
1336 }
1337
1338#ifdef CONFIG_BLK_DEV_INITRD
1339 if (initrd_start) {
1340 size = initrd_end - initrd_start;
1341
1342 /* Resert the initrd image area. */
1343#ifdef CONFIG_DEBUG_BOOTMEM
1344 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1345 initrd_start, initrd_end);
1346#endif
1347 reserve_bootmem(initrd_start, size);
1348 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1349
1350 initrd_start += PAGE_OFFSET;
1351 initrd_end += PAGE_OFFSET;
1352 }
1353#endif
1354 /* Reserve the kernel text/data/bss. */
1355#ifdef CONFIG_DEBUG_BOOTMEM
1356 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1357#endif
1358 reserve_bootmem(kern_base, kern_size);
1359 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1360
1361 /* Reserve the bootmem map. We do not account for it
1362 * in pages_avail because we will release that memory
1363 * in free_all_bootmem.
1364 */
1365 size = bootmap_size;
1366#ifdef CONFIG_DEBUG_BOOTMEM
1367 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1368 (bootmap_pfn << PAGE_SHIFT), size);
1369#endif
1370 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1371 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1372
1373 return end_pfn;
1374}
1375
1376/* paging_init() sets up the page tables */
1377
1378extern void cheetah_ecache_flush_init(void);
1379
1380static unsigned long last_valid_pfn;
1381
1382void __init paging_init(void)
1383{
1384 extern pmd_t swapper_pmd_dir[1024];
1385 extern unsigned int sparc64_vpte_patchme1[1];
1386 extern unsigned int sparc64_vpte_patchme2[1];
1387 unsigned long alias_base = kern_base + PAGE_OFFSET;
1388 unsigned long second_alias_page = 0;
1389 unsigned long pt, flags, end_pfn, pages_avail;
1390 unsigned long shift = alias_base - ((unsigned long)KERNBASE);
1391 unsigned long real_end;
1392
1393 set_bit(0, mmu_context_bmap);
1394
1395 real_end = (unsigned long)_end;
1396 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1397 bigkernel = 1;
1398#ifdef CONFIG_BLK_DEV_INITRD
1399 if (sparc_ramdisk_image || sparc_ramdisk_image64)
1400 real_end = (PAGE_ALIGN(real_end) + PAGE_ALIGN(sparc_ramdisk_size));
1401#endif
1402
1403 /* We assume physical memory starts at some 4mb multiple,
1404 * if this were not true we wouldn't boot up to this point
1405 * anyways.
1406 */
1407 pt = kern_base | _PAGE_VALID | _PAGE_SZ4MB;
1408 pt |= _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W;
1409 local_irq_save(flags);
1410 if (tlb_type == spitfire) {
1411 __asm__ __volatile__(
1412 " stxa %1, [%0] %3\n"
1413 " stxa %2, [%5] %4\n"
1414 " membar #Sync\n"
1415 " flush %%g6\n"
1416 " nop\n"
1417 " nop\n"
1418 " nop\n"
1419 : /* No outputs */
1420 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1421 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (61 << 3)
1422 : "memory");
1423 if (real_end >= KERNBASE + 0x340000) {
1424 second_alias_page = alias_base + 0x400000;
1425 __asm__ __volatile__(
1426 " stxa %1, [%0] %3\n"
1427 " stxa %2, [%5] %4\n"
1428 " membar #Sync\n"
1429 " flush %%g6\n"
1430 " nop\n"
1431 " nop\n"
1432 " nop\n"
1433 : /* No outputs */
1434 : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1435 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (60 << 3)
1436 : "memory");
1437 }
1438 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1439 __asm__ __volatile__(
1440 " stxa %1, [%0] %3\n"
1441 " stxa %2, [%5] %4\n"
1442 " membar #Sync\n"
1443 " flush %%g6\n"
1444 " nop\n"
1445 " nop\n"
1446 " nop\n"
1447 : /* No outputs */
1448 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1449 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (13<<3))
1450 : "memory");
1451 if (real_end >= KERNBASE + 0x340000) {
1452 second_alias_page = alias_base + 0x400000;
1453 __asm__ __volatile__(
1454 " stxa %1, [%0] %3\n"
1455 " stxa %2, [%5] %4\n"
1456 " membar #Sync\n"
1457 " flush %%g6\n"
1458 " nop\n"
1459 " nop\n"
1460 " nop\n"
1461 : /* No outputs */
1462 : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1463 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (12<<3))
1464 : "memory");
1465 }
1466 }
1467 local_irq_restore(flags);
1468
1469 /* Now set kernel pgd to upper alias so physical page computations
1470 * work.
1471 */
1472 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1473
1474 memset(swapper_pmd_dir, 0, sizeof(swapper_pmd_dir));
1475
1476 /* Now can init the kernel/bad page tables. */
1477 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1478 swapper_pmd_dir + (shift / sizeof(pgd_t)));
1479
1480 sparc64_vpte_patchme1[0] |=
1481 (((unsigned long)pgd_val(init_mm.pgd[0])) >> 10);
1482 sparc64_vpte_patchme2[0] |=
1483 (((unsigned long)pgd_val(init_mm.pgd[0])) & 0x3ff);
1484 flushi((long)&sparc64_vpte_patchme1[0]);
1485
1486 /* Setup bootmem... */
1487 pages_avail = 0;
1488 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1489
1490 /* Inherit non-locked OBP mappings. */
1491 inherit_prom_mappings();
1492
1493 /* Ok, we can use our TLB miss and window trap handlers safely.
1494 * We need to do a quick peek here to see if we are on StarFire
1495 * or not, so setup_tba can setup the IRQ globals correctly (it
1496 * needs to get the hard smp processor id correctly).
1497 */
1498 {
1499 extern void setup_tba(int);
1500 setup_tba(this_is_starfire);
1501 }
1502
1503 inherit_locked_prom_mappings(1);
1504
1505 /* We only created DTLB mapping of this stuff. */
1506 spitfire_flush_dtlb_nucleus_page(alias_base);
1507 if (second_alias_page)
1508 spitfire_flush_dtlb_nucleus_page(second_alias_page);
1509
1510 __flush_tlb_all();
1511
1512 {
1513 unsigned long zones_size[MAX_NR_ZONES];
1514 unsigned long zholes_size[MAX_NR_ZONES];
1515 unsigned long npages;
1516 int znum;
1517
1518 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1519 zones_size[znum] = zholes_size[znum] = 0;
1520
1521 npages = end_pfn - pfn_base;
1522 zones_size[ZONE_DMA] = npages;
1523 zholes_size[ZONE_DMA] = npages - pages_avail;
1524
1525 free_area_init_node(0, &contig_page_data, zones_size,
1526 phys_base >> PAGE_SHIFT, zholes_size);
1527 }
1528
1529 device_scan();
1530}
1531
1532/* Ok, it seems that the prom can allocate some more memory chunks
1533 * as a side effect of some prom calls we perform during the
1534 * boot sequence. My most likely theory is that it is from the
1535 * prom_set_traptable() call, and OBP is allocating a scratchpad
1536 * for saving client program register state etc.
1537 */
1538static void __init sort_memlist(struct linux_mlist_p1275 *thislist)
1539{
1540 int swapi = 0;
1541 int i, mitr;
1542 unsigned long tmpaddr, tmpsize;
1543 unsigned long lowest;
1544
1545 for (i = 0; thislist[i].theres_more != 0; i++) {
1546 lowest = thislist[i].start_adr;
1547 for (mitr = i+1; thislist[mitr-1].theres_more != 0; mitr++)
1548 if (thislist[mitr].start_adr < lowest) {
1549 lowest = thislist[mitr].start_adr;
1550 swapi = mitr;
1551 }
1552 if (lowest == thislist[i].start_adr)
1553 continue;
1554 tmpaddr = thislist[swapi].start_adr;
1555 tmpsize = thislist[swapi].num_bytes;
1556 for (mitr = swapi; mitr > i; mitr--) {
1557 thislist[mitr].start_adr = thislist[mitr-1].start_adr;
1558 thislist[mitr].num_bytes = thislist[mitr-1].num_bytes;
1559 }
1560 thislist[i].start_adr = tmpaddr;
1561 thislist[i].num_bytes = tmpsize;
1562 }
1563}
1564
1565void __init rescan_sp_banks(void)
1566{
1567 struct linux_prom64_registers memlist[64];
1568 struct linux_mlist_p1275 avail[64], *mlist;
1569 unsigned long bytes, base_paddr;
1570 int num_regs, node = prom_finddevice("/memory");
1571 int i;
1572
1573 num_regs = prom_getproperty(node, "available",
1574 (char *) memlist, sizeof(memlist));
1575 num_regs = (num_regs / sizeof(struct linux_prom64_registers));
1576 for (i = 0; i < num_regs; i++) {
1577 avail[i].start_adr = memlist[i].phys_addr;
1578 avail[i].num_bytes = memlist[i].reg_size;
1579 avail[i].theres_more = &avail[i + 1];
1580 }
1581 avail[i - 1].theres_more = NULL;
1582 sort_memlist(avail);
1583
1584 mlist = &avail[0];
1585 i = 0;
1586 bytes = mlist->num_bytes;
1587 base_paddr = mlist->start_adr;
1588
1589 sp_banks[0].base_addr = base_paddr;
1590 sp_banks[0].num_bytes = bytes;
1591
1592 while (mlist->theres_more != NULL){
1593 i++;
1594 mlist = mlist->theres_more;
1595 bytes = mlist->num_bytes;
1596 if (i >= SPARC_PHYS_BANKS-1) {
1597 printk ("The machine has more banks than "
1598 "this kernel can support\n"
1599 "Increase the SPARC_PHYS_BANKS "
1600 "setting (currently %d)\n",
1601 SPARC_PHYS_BANKS);
1602 i = SPARC_PHYS_BANKS-1;
1603 break;
1604 }
1605
1606 sp_banks[i].base_addr = mlist->start_adr;
1607 sp_banks[i].num_bytes = mlist->num_bytes;
1608 }
1609
1610 i++;
1611 sp_banks[i].base_addr = 0xdeadbeefbeefdeadUL;
1612 sp_banks[i].num_bytes = 0;
1613
1614 for (i = 0; sp_banks[i].num_bytes != 0; i++)
1615 sp_banks[i].num_bytes &= PAGE_MASK;
1616}
1617
1618static void __init taint_real_pages(void)
1619{
1620 struct sparc_phys_banks saved_sp_banks[SPARC_PHYS_BANKS];
1621 int i;
1622
1623 for (i = 0; i < SPARC_PHYS_BANKS; i++) {
1624 saved_sp_banks[i].base_addr =
1625 sp_banks[i].base_addr;
1626 saved_sp_banks[i].num_bytes =
1627 sp_banks[i].num_bytes;
1628 }
1629
1630 rescan_sp_banks();
1631
1632 /* Find changes discovered in the sp_bank rescan and
1633 * reserve the lost portions in the bootmem maps.
1634 */
1635 for (i = 0; saved_sp_banks[i].num_bytes; i++) {
1636 unsigned long old_start, old_end;
1637
1638 old_start = saved_sp_banks[i].base_addr;
1639 old_end = old_start +
1640 saved_sp_banks[i].num_bytes;
1641 while (old_start < old_end) {
1642 int n;
1643
1644 for (n = 0; sp_banks[n].num_bytes; n++) {
1645 unsigned long new_start, new_end;
1646
1647 new_start = sp_banks[n].base_addr;
1648 new_end = new_start + sp_banks[n].num_bytes;
1649
1650 if (new_start <= old_start &&
1651 new_end >= (old_start + PAGE_SIZE)) {
1652 set_bit (old_start >> 22,
1653 sparc64_valid_addr_bitmap);
1654 goto do_next_page;
1655 }
1656 }
1657 reserve_bootmem(old_start, PAGE_SIZE);
1658
1659 do_next_page:
1660 old_start += PAGE_SIZE;
1661 }
1662 }
1663}
1664
1665void __init mem_init(void)
1666{
1667 unsigned long codepages, datapages, initpages;
1668 unsigned long addr, last;
1669 int i;
1670
1671 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1672 i += 1;
1673 sparc64_valid_addr_bitmap = (unsigned long *)
1674 __alloc_bootmem(i << 3, SMP_CACHE_BYTES, bootmap_base);
1675 if (sparc64_valid_addr_bitmap == NULL) {
1676 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1677 prom_halt();
1678 }
1679 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1680
1681 addr = PAGE_OFFSET + kern_base;
1682 last = PAGE_ALIGN(kern_size) + addr;
1683 while (addr < last) {
1684 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1685 addr += PAGE_SIZE;
1686 }
1687
1688 taint_real_pages();
1689
1690 max_mapnr = last_valid_pfn - pfn_base;
1691 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1692
1693#ifdef CONFIG_DEBUG_BOOTMEM
1694 prom_printf("mem_init: Calling free_all_bootmem().\n");
1695#endif
1696 totalram_pages = num_physpages = free_all_bootmem() - 1;
1697
1698 /*
1699 * Set up the zero page, mark it reserved, so that page count
1700 * is not manipulated when freeing the page from user ptes.
1701 */
1702 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1703 if (mem_map_zero == NULL) {
1704 prom_printf("paging_init: Cannot alloc zero page.\n");
1705 prom_halt();
1706 }
1707 SetPageReserved(mem_map_zero);
1708
1709 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1710 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1711 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1712 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1713 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1714 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1715
1716 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1717 nr_free_pages() << (PAGE_SHIFT-10),
1718 codepages << (PAGE_SHIFT-10),
1719 datapages << (PAGE_SHIFT-10),
1720 initpages << (PAGE_SHIFT-10),
1721 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1722
1723 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1724 cheetah_ecache_flush_init();
1725}
1726
1727void free_initmem (void)
1728{
1729 unsigned long addr, initend;
1730
1731 /*
1732 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1733 */
1734 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1735 initend = (unsigned long)(__init_end) & PAGE_MASK;
1736 for (; addr < initend; addr += PAGE_SIZE) {
1737 unsigned long page;
1738 struct page *p;
1739
1740 page = (addr +
1741 ((unsigned long) __va(kern_base)) -
1742 ((unsigned long) KERNBASE));
1743 memset((void *)addr, 0xcc, PAGE_SIZE);
1744 p = virt_to_page(page);
1745
1746 ClearPageReserved(p);
1747 set_page_count(p, 1);
1748 __free_page(p);
1749 num_physpages++;
1750 totalram_pages++;
1751 }
1752}
1753
1754#ifdef CONFIG_BLK_DEV_INITRD
1755void free_initrd_mem(unsigned long start, unsigned long end)
1756{
1757 if (start < end)
1758 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1759 for (; start < end; start += PAGE_SIZE) {
1760 struct page *p = virt_to_page(start);
1761
1762 ClearPageReserved(p);
1763 set_page_count(p, 1);
1764 __free_page(p);
1765 num_physpages++;
1766 totalram_pages++;
1767 }
1768}
1769#endif
diff --git a/arch/sparc64/mm/tlb.c b/arch/sparc64/mm/tlb.c
new file mode 100644
index 000000000000..90ca99d0b89c
--- /dev/null
+++ b/arch/sparc64/mm/tlb.c
@@ -0,0 +1,151 @@
1/* arch/sparc64/mm/tlb.c
2 *
3 * Copyright (C) 2004 David S. Miller <davem@redhat.com>
4 */
5
6#include <linux/kernel.h>
7#include <linux/init.h>
8#include <linux/percpu.h>
9#include <linux/mm.h>
10#include <linux/swap.h>
11
12#include <asm/pgtable.h>
13#include <asm/pgalloc.h>
14#include <asm/tlbflush.h>
15#include <asm/cacheflush.h>
16#include <asm/mmu_context.h>
17#include <asm/tlb.h>
18
19/* Heavily inspired by the ppc64 code. */
20
21DEFINE_PER_CPU(struct mmu_gather, mmu_gathers) =
22 { NULL, 0, 0, 0, 0, 0, { 0 }, { NULL }, };
23
24void flush_tlb_pending(void)
25{
26 struct mmu_gather *mp = &__get_cpu_var(mmu_gathers);
27
28 if (mp->tlb_nr) {
29 if (CTX_VALID(mp->mm->context)) {
30#ifdef CONFIG_SMP
31 smp_flush_tlb_pending(mp->mm, mp->tlb_nr,
32 &mp->vaddrs[0]);
33#else
34 __flush_tlb_pending(CTX_HWBITS(mp->mm->context),
35 mp->tlb_nr, &mp->vaddrs[0]);
36#endif
37 }
38 mp->tlb_nr = 0;
39 }
40}
41
42void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig)
43{
44 struct mmu_gather *mp = &__get_cpu_var(mmu_gathers);
45 unsigned long nr;
46
47 vaddr &= PAGE_MASK;
48 if (pte_exec(orig))
49 vaddr |= 0x1UL;
50
51 if (pte_dirty(orig)) {
52 unsigned long paddr, pfn = pte_pfn(orig);
53 struct address_space *mapping;
54 struct page *page;
55
56 if (!pfn_valid(pfn))
57 goto no_cache_flush;
58
59 page = pfn_to_page(pfn);
60 if (PageReserved(page))
61 goto no_cache_flush;
62
63 /* A real file page? */
64 mapping = page_mapping(page);
65 if (!mapping)
66 goto no_cache_flush;
67
68 paddr = (unsigned long) page_address(page);
69 if ((paddr ^ vaddr) & (1 << 13))
70 flush_dcache_page_all(mm, page);
71 }
72
73no_cache_flush:
74
75 if (mp->tlb_frozen)
76 return;
77
78 nr = mp->tlb_nr;
79
80 if (unlikely(nr != 0 && mm != mp->mm)) {
81 flush_tlb_pending();
82 nr = 0;
83 }
84
85 if (nr == 0)
86 mp->mm = mm;
87
88 mp->vaddrs[nr] = vaddr;
89 mp->tlb_nr = ++nr;
90 if (nr >= TLB_BATCH_NR)
91 flush_tlb_pending();
92}
93
94void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start, unsigned long end)
95{
96 struct mmu_gather *mp = &__get_cpu_var(mmu_gathers);
97 unsigned long nr = mp->tlb_nr;
98 long s = start, e = end, vpte_base;
99
100 if (mp->tlb_frozen)
101 return;
102
103 /* If start is greater than end, that is a real problem. */
104 BUG_ON(start > end);
105
106 /* However, straddling the VA space hole is quite normal. */
107 s &= PMD_MASK;
108 e = (e + PMD_SIZE - 1) & PMD_MASK;
109
110 vpte_base = (tlb_type == spitfire ?
111 VPTE_BASE_SPITFIRE :
112 VPTE_BASE_CHEETAH);
113
114 if (unlikely(nr != 0 && mm != mp->mm)) {
115 flush_tlb_pending();
116 nr = 0;
117 }
118
119 if (nr == 0)
120 mp->mm = mm;
121
122 start = vpte_base + (s >> (PAGE_SHIFT - 3));
123 end = vpte_base + (e >> (PAGE_SHIFT - 3));
124
125 /* If the request straddles the VA space hole, we
126 * need to swap start and end. The reason this
127 * occurs is that "vpte_base" is the center of
128 * the linear page table mapping area. Thus,
129 * high addresses with the sign bit set map to
130 * addresses below vpte_base and non-sign bit
131 * addresses map to addresses above vpte_base.
132 */
133 if (end < start) {
134 unsigned long tmp = start;
135
136 start = end;
137 end = tmp;
138 }
139
140 while (start < end) {
141 mp->vaddrs[nr] = start;
142 mp->tlb_nr = ++nr;
143 if (nr >= TLB_BATCH_NR) {
144 flush_tlb_pending();
145 nr = 0;
146 }
147 start += PAGE_SIZE;
148 }
149 if (nr)
150 flush_tlb_pending();
151}
diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S
new file mode 100644
index 000000000000..7a0934321010
--- /dev/null
+++ b/arch/sparc64/mm/ultra.S
@@ -0,0 +1,583 @@
1/* $Id: ultra.S,v 1.72 2002/02/09 19:49:31 davem Exp $
2 * ultra.S: Don't expand these all over the place...
3 *
4 * Copyright (C) 1997, 2000 David S. Miller (davem@redhat.com)
5 */
6
7#include <linux/config.h>
8#include <asm/asi.h>
9#include <asm/pgtable.h>
10#include <asm/page.h>
11#include <asm/spitfire.h>
12#include <asm/mmu_context.h>
13#include <asm/pil.h>
14#include <asm/head.h>
15#include <asm/thread_info.h>
16#include <asm/cacheflush.h>
17
18 /* Basically, most of the Spitfire vs. Cheetah madness
19 * has to do with the fact that Cheetah does not support
20 * IMMU flushes out of the secondary context. Someone needs
21 * to throw a south lake birthday party for the folks
22 * in Microelectronics who refused to fix this shit.
23 */
24
25 /* This file is meant to be read efficiently by the CPU, not humans.
26 * Staraj sie tego nikomu nie pierdolnac...
27 */
28 .text
29 .align 32
30 .globl __flush_tlb_mm
31__flush_tlb_mm: /* %o0=(ctx & TAG_CONTEXT_BITS), %o1=SECONDARY_CONTEXT */
32 ldxa [%o1] ASI_DMMU, %g2
33 cmp %g2, %o0
34 bne,pn %icc, __spitfire_flush_tlb_mm_slow
35 mov 0x50, %g3
36 stxa %g0, [%g3] ASI_DMMU_DEMAP
37 stxa %g0, [%g3] ASI_IMMU_DEMAP
38 retl
39 flush %g6
40 nop
41 nop
42 nop
43 nop
44 nop
45 nop
46 nop
47 nop
48
49 .align 32
50 .globl __flush_tlb_pending
51__flush_tlb_pending:
52 /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
53 rdpr %pstate, %g7
54 sllx %o1, 3, %o1
55 andn %g7, PSTATE_IE, %g2
56 wrpr %g2, %pstate
57 mov SECONDARY_CONTEXT, %o4
58 ldxa [%o4] ASI_DMMU, %g2
59 stxa %o0, [%o4] ASI_DMMU
601: sub %o1, (1 << 3), %o1
61 ldx [%o2 + %o1], %o3
62 andcc %o3, 1, %g0
63 andn %o3, 1, %o3
64 be,pn %icc, 2f
65 or %o3, 0x10, %o3
66 stxa %g0, [%o3] ASI_IMMU_DEMAP
672: stxa %g0, [%o3] ASI_DMMU_DEMAP
68 membar #Sync
69 brnz,pt %o1, 1b
70 nop
71 stxa %g2, [%o4] ASI_DMMU
72 flush %g6
73 retl
74 wrpr %g7, 0x0, %pstate
75
76 .align 32
77 .globl __flush_tlb_kernel_range
78__flush_tlb_kernel_range: /* %o0=start, %o1=end */
79 cmp %o0, %o1
80 be,pn %xcc, 2f
81 sethi %hi(PAGE_SIZE), %o4
82 sub %o1, %o0, %o3
83 sub %o3, %o4, %o3
84 or %o0, 0x20, %o0 ! Nucleus
851: stxa %g0, [%o0 + %o3] ASI_DMMU_DEMAP
86 stxa %g0, [%o0 + %o3] ASI_IMMU_DEMAP
87 membar #Sync
88 brnz,pt %o3, 1b
89 sub %o3, %o4, %o3
902: retl
91 flush %g6
92
93__spitfire_flush_tlb_mm_slow:
94 rdpr %pstate, %g1
95 wrpr %g1, PSTATE_IE, %pstate
96 stxa %o0, [%o1] ASI_DMMU
97 stxa %g0, [%g3] ASI_DMMU_DEMAP
98 stxa %g0, [%g3] ASI_IMMU_DEMAP
99 flush %g6
100 stxa %g2, [%o1] ASI_DMMU
101 flush %g6
102 retl
103 wrpr %g1, 0, %pstate
104
105/*
106 * The following code flushes one page_size worth.
107 */
108#if (PAGE_SHIFT == 13)
109#define ITAG_MASK 0xfe
110#elif (PAGE_SHIFT == 16)
111#define ITAG_MASK 0x7fe
112#else
113#error unsupported PAGE_SIZE
114#endif
115 .align 32
116 .globl __flush_icache_page
117__flush_icache_page: /* %o0 = phys_page */
118 membar #StoreStore
119 srlx %o0, PAGE_SHIFT, %o0
120 sethi %uhi(PAGE_OFFSET), %g1
121 sllx %o0, PAGE_SHIFT, %o0
122 sethi %hi(PAGE_SIZE), %g2
123 sllx %g1, 32, %g1
124 add %o0, %g1, %o0
1251: subcc %g2, 32, %g2
126 bne,pt %icc, 1b
127 flush %o0 + %g2
128 retl
129 nop
130
131#ifdef DCACHE_ALIASING_POSSIBLE
132
133#if (PAGE_SHIFT != 13)
134#error only page shift of 13 is supported by dcache flush
135#endif
136
137#define DTAG_MASK 0x3
138
139 .align 64
140 .globl __flush_dcache_page
141__flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */
142 sethi %uhi(PAGE_OFFSET), %g1
143 sllx %g1, 32, %g1
144 sub %o0, %g1, %o0
145 clr %o4
146 srlx %o0, 11, %o0
147 sethi %hi(1 << 14), %o2
1481: ldxa [%o4] ASI_DCACHE_TAG, %o3 ! LSU Group
149 add %o4, (1 << 5), %o4 ! IEU0
150 ldxa [%o4] ASI_DCACHE_TAG, %g1 ! LSU Group
151 add %o4, (1 << 5), %o4 ! IEU0
152 ldxa [%o4] ASI_DCACHE_TAG, %g2 ! LSU Group o3 available
153 add %o4, (1 << 5), %o4 ! IEU0
154 andn %o3, DTAG_MASK, %o3 ! IEU1
155 ldxa [%o4] ASI_DCACHE_TAG, %g3 ! LSU Group
156 add %o4, (1 << 5), %o4 ! IEU0
157 andn %g1, DTAG_MASK, %g1 ! IEU1
158 cmp %o0, %o3 ! IEU1 Group
159 be,a,pn %xcc, dflush1 ! CTI
160 sub %o4, (4 << 5), %o4 ! IEU0 (Group)
161 cmp %o0, %g1 ! IEU1 Group
162 andn %g2, DTAG_MASK, %g2 ! IEU0
163 be,a,pn %xcc, dflush2 ! CTI
164 sub %o4, (3 << 5), %o4 ! IEU0 (Group)
165 cmp %o0, %g2 ! IEU1 Group
166 andn %g3, DTAG_MASK, %g3 ! IEU0
167 be,a,pn %xcc, dflush3 ! CTI
168 sub %o4, (2 << 5), %o4 ! IEU0 (Group)
169 cmp %o0, %g3 ! IEU1 Group
170 be,a,pn %xcc, dflush4 ! CTI
171 sub %o4, (1 << 5), %o4 ! IEU0
1722: cmp %o4, %o2 ! IEU1 Group
173 bne,pt %xcc, 1b ! CTI
174 nop ! IEU0
175
176 /* The I-cache does not snoop local stores so we
177 * better flush that too when necessary.
178 */
179 brnz,pt %o1, __flush_icache_page
180 sllx %o0, 11, %o0
181 retl
182 nop
183
184dflush1:stxa %g0, [%o4] ASI_DCACHE_TAG
185 add %o4, (1 << 5), %o4
186dflush2:stxa %g0, [%o4] ASI_DCACHE_TAG
187 add %o4, (1 << 5), %o4
188dflush3:stxa %g0, [%o4] ASI_DCACHE_TAG
189 add %o4, (1 << 5), %o4
190dflush4:stxa %g0, [%o4] ASI_DCACHE_TAG
191 add %o4, (1 << 5), %o4
192 membar #Sync
193 ba,pt %xcc, 2b
194 nop
195#endif /* DCACHE_ALIASING_POSSIBLE */
196
197 .align 32
198__prefill_dtlb:
199 rdpr %pstate, %g7
200 wrpr %g7, PSTATE_IE, %pstate
201 mov TLB_TAG_ACCESS, %g1
202 stxa %o5, [%g1] ASI_DMMU
203 stxa %o2, [%g0] ASI_DTLB_DATA_IN
204 flush %g6
205 retl
206 wrpr %g7, %pstate
207__prefill_itlb:
208 rdpr %pstate, %g7
209 wrpr %g7, PSTATE_IE, %pstate
210 mov TLB_TAG_ACCESS, %g1
211 stxa %o5, [%g1] ASI_IMMU
212 stxa %o2, [%g0] ASI_ITLB_DATA_IN
213 flush %g6
214 retl
215 wrpr %g7, %pstate
216
217 .globl __update_mmu_cache
218__update_mmu_cache: /* %o0=hw_context, %o1=address, %o2=pte, %o3=fault_code */
219 srlx %o1, PAGE_SHIFT, %o1
220 andcc %o3, FAULT_CODE_DTLB, %g0
221 sllx %o1, PAGE_SHIFT, %o5
222 bne,pt %xcc, __prefill_dtlb
223 or %o5, %o0, %o5
224 ba,a,pt %xcc, __prefill_itlb
225
226 /* Cheetah specific versions, patched at boot time.
227 *
228 * This writes of the PRIMARY_CONTEXT register in this file are
229 * safe even on Cheetah+ and later wrt. the page size fields.
230 * The nucleus page size fields do not matter because we make
231 * no data references, and these instructions execute out of a
232 * locked I-TLB entry sitting in the fully assosciative I-TLB.
233 * This sequence should also never trap.
234 */
235__cheetah_flush_tlb_mm: /* 15 insns */
236 rdpr %pstate, %g7
237 andn %g7, PSTATE_IE, %g2
238 wrpr %g2, 0x0, %pstate
239 wrpr %g0, 1, %tl
240 mov PRIMARY_CONTEXT, %o2
241 mov 0x40, %g3
242 ldxa [%o2] ASI_DMMU, %g2
243 stxa %o0, [%o2] ASI_DMMU
244 stxa %g0, [%g3] ASI_DMMU_DEMAP
245 stxa %g0, [%g3] ASI_IMMU_DEMAP
246 stxa %g2, [%o2] ASI_DMMU
247 flush %g6
248 wrpr %g0, 0, %tl
249 retl
250 wrpr %g7, 0x0, %pstate
251
252__cheetah_flush_tlb_pending: /* 22 insns */
253 /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
254 rdpr %pstate, %g7
255 sllx %o1, 3, %o1
256 andn %g7, PSTATE_IE, %g2
257 wrpr %g2, 0x0, %pstate
258 wrpr %g0, 1, %tl
259 mov PRIMARY_CONTEXT, %o4
260 ldxa [%o4] ASI_DMMU, %g2
261 stxa %o0, [%o4] ASI_DMMU
2621: sub %o1, (1 << 3), %o1
263 ldx [%o2 + %o1], %o3
264 andcc %o3, 1, %g0
265 be,pn %icc, 2f
266 andn %o3, 1, %o3
267 stxa %g0, [%o3] ASI_IMMU_DEMAP
2682: stxa %g0, [%o3] ASI_DMMU_DEMAP
269 brnz,pt %o1, 1b
270 membar #Sync
271 stxa %g2, [%o4] ASI_DMMU
272 flush %g6
273 wrpr %g0, 0, %tl
274 retl
275 wrpr %g7, 0x0, %pstate
276
277#ifdef DCACHE_ALIASING_POSSIBLE
278flush_dcpage_cheetah: /* 11 insns */
279 sethi %uhi(PAGE_OFFSET), %g1
280 sllx %g1, 32, %g1
281 sub %o0, %g1, %o0
282 sethi %hi(PAGE_SIZE), %o4
2831: subcc %o4, (1 << 5), %o4
284 stxa %g0, [%o0 + %o4] ASI_DCACHE_INVALIDATE
285 membar #Sync
286 bne,pt %icc, 1b
287 nop
288 retl /* I-cache flush never needed on Cheetah, see callers. */
289 nop
290#endif /* DCACHE_ALIASING_POSSIBLE */
291
292cheetah_patch_one:
2931: lduw [%o1], %g1
294 stw %g1, [%o0]
295 flush %o0
296 subcc %o2, 1, %o2
297 add %o1, 4, %o1
298 bne,pt %icc, 1b
299 add %o0, 4, %o0
300 retl
301 nop
302
303 .globl cheetah_patch_cachetlbops
304cheetah_patch_cachetlbops:
305 save %sp, -128, %sp
306
307 sethi %hi(__flush_tlb_mm), %o0
308 or %o0, %lo(__flush_tlb_mm), %o0
309 sethi %hi(__cheetah_flush_tlb_mm), %o1
310 or %o1, %lo(__cheetah_flush_tlb_mm), %o1
311 call cheetah_patch_one
312 mov 15, %o2
313
314 sethi %hi(__flush_tlb_pending), %o0
315 or %o0, %lo(__flush_tlb_pending), %o0
316 sethi %hi(__cheetah_flush_tlb_pending), %o1
317 or %o1, %lo(__cheetah_flush_tlb_pending), %o1
318 call cheetah_patch_one
319 mov 22, %o2
320
321#ifdef DCACHE_ALIASING_POSSIBLE
322 sethi %hi(__flush_dcache_page), %o0
323 or %o0, %lo(__flush_dcache_page), %o0
324 sethi %hi(flush_dcpage_cheetah), %o1
325 or %o1, %lo(flush_dcpage_cheetah), %o1
326 call cheetah_patch_one
327 mov 11, %o2
328#endif /* DCACHE_ALIASING_POSSIBLE */
329
330 ret
331 restore
332
333#ifdef CONFIG_SMP
334 /* These are all called by the slaves of a cross call, at
335 * trap level 1, with interrupts fully disabled.
336 *
337 * Register usage:
338 * %g5 mm->context (all tlb flushes)
339 * %g1 address arg 1 (tlb page and range flushes)
340 * %g7 address arg 2 (tlb range flush only)
341 *
342 * %g6 ivector table, don't touch
343 * %g2 scratch 1
344 * %g3 scratch 2
345 * %g4 scratch 3
346 *
347 * TODO: Make xcall TLB range flushes use the tricks above... -DaveM
348 */
349 .align 32
350 .globl xcall_flush_tlb_mm
351xcall_flush_tlb_mm:
352 mov PRIMARY_CONTEXT, %g2
353 mov 0x40, %g4
354 ldxa [%g2] ASI_DMMU, %g3
355 stxa %g5, [%g2] ASI_DMMU
356 stxa %g0, [%g4] ASI_DMMU_DEMAP
357 stxa %g0, [%g4] ASI_IMMU_DEMAP
358 stxa %g3, [%g2] ASI_DMMU
359 retry
360
361 .globl xcall_flush_tlb_pending
362xcall_flush_tlb_pending:
363 /* %g5=context, %g1=nr, %g7=vaddrs[] */
364 sllx %g1, 3, %g1
365 mov PRIMARY_CONTEXT, %g4
366 ldxa [%g4] ASI_DMMU, %g2
367 stxa %g5, [%g4] ASI_DMMU
3681: sub %g1, (1 << 3), %g1
369 ldx [%g7 + %g1], %g5
370 andcc %g5, 0x1, %g0
371 be,pn %icc, 2f
372
373 andn %g5, 0x1, %g5
374 stxa %g0, [%g5] ASI_IMMU_DEMAP
3752: stxa %g0, [%g5] ASI_DMMU_DEMAP
376 membar #Sync
377 brnz,pt %g1, 1b
378 nop
379 stxa %g2, [%g4] ASI_DMMU
380 retry
381
382 .globl xcall_flush_tlb_kernel_range
383xcall_flush_tlb_kernel_range:
384 sethi %hi(PAGE_SIZE - 1), %g2
385 or %g2, %lo(PAGE_SIZE - 1), %g2
386 andn %g1, %g2, %g1
387 andn %g7, %g2, %g7
388 sub %g7, %g1, %g3
389 add %g2, 1, %g2
390 sub %g3, %g2, %g3
391 or %g1, 0x20, %g1 ! Nucleus
3921: stxa %g0, [%g1 + %g3] ASI_DMMU_DEMAP
393 stxa %g0, [%g1 + %g3] ASI_IMMU_DEMAP
394 membar #Sync
395 brnz,pt %g3, 1b
396 sub %g3, %g2, %g3
397 retry
398 nop
399 nop
400
401 /* This runs in a very controlled environment, so we do
402 * not need to worry about BH races etc.
403 */
404 .globl xcall_sync_tick
405xcall_sync_tick:
406 rdpr %pstate, %g2
407 wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
408 rdpr %pil, %g2
409 wrpr %g0, 15, %pil
410 sethi %hi(109f), %g7
411 b,pt %xcc, etrap_irq
412109: or %g7, %lo(109b), %g7
413 call smp_synchronize_tick_client
414 nop
415 clr %l6
416 b rtrap_xcall
417 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
418
419 /* NOTE: This is SPECIAL!! We do etrap/rtrap however
420 * we choose to deal with the "BH's run with
421 * %pil==15" problem (described in asm/pil.h)
422 * by just invoking rtrap directly past where
423 * BH's are checked for.
424 *
425 * We do it like this because we do not want %pil==15
426 * lockups to prevent regs being reported.
427 */
428 .globl xcall_report_regs
429xcall_report_regs:
430 rdpr %pstate, %g2
431 wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
432 rdpr %pil, %g2
433 wrpr %g0, 15, %pil
434 sethi %hi(109f), %g7
435 b,pt %xcc, etrap_irq
436109: or %g7, %lo(109b), %g7
437 call __show_regs
438 add %sp, PTREGS_OFF, %o0
439 clr %l6
440 /* Has to be a non-v9 branch due to the large distance. */
441 b rtrap_xcall
442 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
443
444#ifdef DCACHE_ALIASING_POSSIBLE
445 .align 32
446 .globl xcall_flush_dcache_page_cheetah
447xcall_flush_dcache_page_cheetah: /* %g1 == physical page address */
448 sethi %hi(PAGE_SIZE), %g3
4491: subcc %g3, (1 << 5), %g3
450 stxa %g0, [%g1 + %g3] ASI_DCACHE_INVALIDATE
451 membar #Sync
452 bne,pt %icc, 1b
453 nop
454 retry
455 nop
456#endif /* DCACHE_ALIASING_POSSIBLE */
457
458 .globl xcall_flush_dcache_page_spitfire
459xcall_flush_dcache_page_spitfire: /* %g1 == physical page address
460 %g7 == kernel page virtual address
461 %g5 == (page->mapping != NULL) */
462#ifdef DCACHE_ALIASING_POSSIBLE
463 srlx %g1, (13 - 2), %g1 ! Form tag comparitor
464 sethi %hi(L1DCACHE_SIZE), %g3 ! D$ size == 16K
465 sub %g3, (1 << 5), %g3 ! D$ linesize == 32
4661: ldxa [%g3] ASI_DCACHE_TAG, %g2
467 andcc %g2, 0x3, %g0
468 be,pn %xcc, 2f
469 andn %g2, 0x3, %g2
470 cmp %g2, %g1
471
472 bne,pt %xcc, 2f
473 nop
474 stxa %g0, [%g3] ASI_DCACHE_TAG
475 membar #Sync
4762: cmp %g3, 0
477 bne,pt %xcc, 1b
478 sub %g3, (1 << 5), %g3
479
480 brz,pn %g5, 2f
481#endif /* DCACHE_ALIASING_POSSIBLE */
482 sethi %hi(PAGE_SIZE), %g3
483
4841: flush %g7
485 subcc %g3, (1 << 5), %g3
486 bne,pt %icc, 1b
487 add %g7, (1 << 5), %g7
488
4892: retry
490 nop
491 nop
492
493 .globl xcall_promstop
494xcall_promstop:
495 rdpr %pstate, %g2
496 wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
497 rdpr %pil, %g2
498 wrpr %g0, 15, %pil
499 sethi %hi(109f), %g7
500 b,pt %xcc, etrap_irq
501109: or %g7, %lo(109b), %g7
502 flushw
503 call prom_stopself
504 nop
505 /* We should not return, just spin if we do... */
5061: b,a,pt %xcc, 1b
507 nop
508
509 .data
510
511errata32_hwbug:
512 .xword 0
513
514 .text
515
516 /* These two are not performance critical... */
517 .globl xcall_flush_tlb_all_spitfire
518xcall_flush_tlb_all_spitfire:
519 /* Spitfire Errata #32 workaround. */
520 sethi %hi(errata32_hwbug), %g4
521 stx %g0, [%g4 + %lo(errata32_hwbug)]
522
523 clr %g2
524 clr %g3
5251: ldxa [%g3] ASI_DTLB_DATA_ACCESS, %g4
526 and %g4, _PAGE_L, %g5
527 brnz,pn %g5, 2f
528 mov TLB_TAG_ACCESS, %g7
529
530 stxa %g0, [%g7] ASI_DMMU
531 membar #Sync
532 stxa %g0, [%g3] ASI_DTLB_DATA_ACCESS
533 membar #Sync
534
535 /* Spitfire Errata #32 workaround. */
536 sethi %hi(errata32_hwbug), %g4
537 stx %g0, [%g4 + %lo(errata32_hwbug)]
538
5392: ldxa [%g3] ASI_ITLB_DATA_ACCESS, %g4
540 and %g4, _PAGE_L, %g5
541 brnz,pn %g5, 2f
542 mov TLB_TAG_ACCESS, %g7
543
544 stxa %g0, [%g7] ASI_IMMU
545 membar #Sync
546 stxa %g0, [%g3] ASI_ITLB_DATA_ACCESS
547 membar #Sync
548
549 /* Spitfire Errata #32 workaround. */
550 sethi %hi(errata32_hwbug), %g4
551 stx %g0, [%g4 + %lo(errata32_hwbug)]
552
5532: add %g2, 1, %g2
554 cmp %g2, SPITFIRE_HIGHEST_LOCKED_TLBENT
555 ble,pt %icc, 1b
556 sll %g2, 3, %g3
557 flush %g6
558 retry
559
560 .globl xcall_flush_tlb_all_cheetah
561xcall_flush_tlb_all_cheetah:
562 mov 0x80, %g2
563 stxa %g0, [%g2] ASI_DMMU_DEMAP
564 stxa %g0, [%g2] ASI_IMMU_DEMAP
565 retry
566
567 /* These just get rescheduled to PIL vectors. */
568 .globl xcall_call_function
569xcall_call_function:
570 wr %g0, (1 << PIL_SMP_CALL_FUNC), %set_softint
571 retry
572
573 .globl xcall_receive_signal
574xcall_receive_signal:
575 wr %g0, (1 << PIL_SMP_RECEIVE_SIGNAL), %set_softint
576 retry
577
578 .globl xcall_capture
579xcall_capture:
580 wr %g0, (1 << PIL_SMP_CAPTURE), %set_softint
581 retry
582
583#endif /* CONFIG_SMP */
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