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authorAnton Altaparmakov <aia21@hera.kernel.org>2006-03-23 09:39:08 -0500
committerAnton Altaparmakov <aia21@hera.kernel.org>2006-03-23 09:39:08 -0500
commit74293759002aa7db0179158c20676a034614577b (patch)
tree030ef62361042d1a034087ad9a726db3b57bba72 /arch/sparc64/mm/init.c
parentbb8047d3540affd6b8c2adac3fe792e07143be0f (diff)
parent2e6e33bab6e1996a5dec9108fb467b52b841e7a8 (diff)
Merge branch 'master' of /home/aia21/ntfs-2.6/
Diffstat (limited to 'arch/sparc64/mm/init.c')
-rw-r--r--arch/sparc64/mm/init.c1452
1 files changed, 808 insertions, 644 deletions
diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
index 1e44ee26cee8..ded63ee9c4fd 100644
--- a/arch/sparc64/mm/init.c
+++ b/arch/sparc64/mm/init.c
@@ -6,6 +6,7 @@
6 */ 6 */
7 7
8#include <linux/config.h> 8#include <linux/config.h>
9#include <linux/module.h>
9#include <linux/kernel.h> 10#include <linux/kernel.h>
10#include <linux/sched.h> 11#include <linux/sched.h>
11#include <linux/string.h> 12#include <linux/string.h>
@@ -39,9 +40,27 @@
39#include <asm/tlb.h> 40#include <asm/tlb.h>
40#include <asm/spitfire.h> 41#include <asm/spitfire.h>
41#include <asm/sections.h> 42#include <asm/sections.h>
43#include <asm/tsb.h>
44#include <asm/hypervisor.h>
42 45
43extern void device_scan(void); 46extern void device_scan(void);
44 47
48#define MAX_PHYS_ADDRESS (1UL << 42UL)
49#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
50#define KPTE_BITMAP_BYTES \
51 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
52
53unsigned long kern_linear_pte_xor[2] __read_mostly;
54
55/* A bitmap, one bit for every 256MB of physical memory. If the bit
56 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
57 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
58 */
59unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
60
61/* A special kernel TSB for 4MB and 256MB linear mappings. */
62struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
63
45#define MAX_BANKS 32 64#define MAX_BANKS 32
46 65
47static struct linux_prom64_registers pavail[MAX_BANKS] __initdata; 66static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
@@ -111,11 +130,9 @@ static void __init read_obp_memory(const char *property,
111 130
112unsigned long *sparc64_valid_addr_bitmap __read_mostly; 131unsigned long *sparc64_valid_addr_bitmap __read_mostly;
113 132
114/* Ugly, but necessary... -DaveM */ 133/* Kernel physical address base and size in bytes. */
115unsigned long phys_base __read_mostly;
116unsigned long kern_base __read_mostly; 134unsigned long kern_base __read_mostly;
117unsigned long kern_size __read_mostly; 135unsigned long kern_size __read_mostly;
118unsigned long pfn_base __read_mostly;
119 136
120/* get_new_mmu_context() uses "cache + 1". */ 137/* get_new_mmu_context() uses "cache + 1". */
121DEFINE_SPINLOCK(ctx_alloc_lock); 138DEFINE_SPINLOCK(ctx_alloc_lock);
@@ -141,24 +158,28 @@ unsigned long sparc64_kern_sec_context __read_mostly;
141 158
142int bigkernel = 0; 159int bigkernel = 0;
143 160
144/* XXX Tune this... */ 161kmem_cache_t *pgtable_cache __read_mostly;
145#define PGT_CACHE_LOW 25 162
146#define PGT_CACHE_HIGH 50 163static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
164{
165 clear_page(addr);
166}
167
168extern void tsb_cache_init(void);
147 169
148void check_pgt_cache(void) 170void pgtable_cache_init(void)
149{ 171{
150 preempt_disable(); 172 pgtable_cache = kmem_cache_create("pgtable_cache",
151 if (pgtable_cache_size > PGT_CACHE_HIGH) { 173 PAGE_SIZE, PAGE_SIZE,
152 do { 174 SLAB_HWCACHE_ALIGN |
153 if (pgd_quicklist) 175 SLAB_MUST_HWCACHE_ALIGN,
154 free_pgd_slow(get_pgd_fast()); 176 zero_ctor,
155 if (pte_quicklist[0]) 177 NULL);
156 free_pte_slow(pte_alloc_one_fast(NULL, 0)); 178 if (!pgtable_cache) {
157 if (pte_quicklist[1]) 179 prom_printf("Could not create pgtable_cache\n");
158 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10))); 180 prom_halt();
159 } while (pgtable_cache_size > PGT_CACHE_LOW);
160 } 181 }
161 preempt_enable(); 182 tsb_cache_init();
162} 183}
163 184
164#ifdef CONFIG_DEBUG_DCFLUSH 185#ifdef CONFIG_DEBUG_DCFLUSH
@@ -168,8 +189,9 @@ atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
168#endif 189#endif
169#endif 190#endif
170 191
171__inline__ void flush_dcache_page_impl(struct page *page) 192inline void flush_dcache_page_impl(struct page *page)
172{ 193{
194 BUG_ON(tlb_type == hypervisor);
173#ifdef CONFIG_DEBUG_DCFLUSH 195#ifdef CONFIG_DEBUG_DCFLUSH
174 atomic_inc(&dcpage_flushes); 196 atomic_inc(&dcpage_flushes);
175#endif 197#endif
@@ -186,8 +208,8 @@ __inline__ void flush_dcache_page_impl(struct page *page)
186} 208}
187 209
188#define PG_dcache_dirty PG_arch_1 210#define PG_dcache_dirty PG_arch_1
189#define PG_dcache_cpu_shift 24 211#define PG_dcache_cpu_shift 24UL
190#define PG_dcache_cpu_mask (256 - 1) 212#define PG_dcache_cpu_mask (256UL - 1UL)
191 213
192#if NR_CPUS > 256 214#if NR_CPUS > 256
193#error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus 215#error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
@@ -243,32 +265,78 @@ static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long c
243 : "g1", "g7"); 265 : "g1", "g7");
244} 266}
245 267
268static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
269{
270 unsigned long tsb_addr = (unsigned long) ent;
271
272 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
273 tsb_addr = __pa(tsb_addr);
274
275 __tsb_insert(tsb_addr, tag, pte);
276}
277
278unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
279unsigned long _PAGE_SZBITS __read_mostly;
280
246void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) 281void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
247{ 282{
248 struct page *page; 283 struct mm_struct *mm;
249 unsigned long pfn; 284 struct tsb *tsb;
250 unsigned long pg_flags; 285 unsigned long tag, flags;
251 286 unsigned long tsb_index, tsb_hash_shift;
252 pfn = pte_pfn(pte); 287
253 if (pfn_valid(pfn) && 288 if (tlb_type != hypervisor) {
254 (page = pfn_to_page(pfn), page_mapping(page)) && 289 unsigned long pfn = pte_pfn(pte);
255 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) { 290 unsigned long pg_flags;
256 int cpu = ((pg_flags >> PG_dcache_cpu_shift) & 291 struct page *page;
257 PG_dcache_cpu_mask); 292
258 int this_cpu = get_cpu(); 293 if (pfn_valid(pfn) &&
259 294 (page = pfn_to_page(pfn), page_mapping(page)) &&
260 /* This is just to optimize away some function calls 295 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
261 * in the SMP case. 296 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
262 */ 297 PG_dcache_cpu_mask);
263 if (cpu == this_cpu) 298 int this_cpu = get_cpu();
264 flush_dcache_page_impl(page); 299
265 else 300 /* This is just to optimize away some function calls
266 smp_flush_dcache_page_impl(page, cpu); 301 * in the SMP case.
302 */
303 if (cpu == this_cpu)
304 flush_dcache_page_impl(page);
305 else
306 smp_flush_dcache_page_impl(page, cpu);
307
308 clear_dcache_dirty_cpu(page, cpu);
267 309
268 clear_dcache_dirty_cpu(page, cpu); 310 put_cpu();
311 }
312 }
269 313
270 put_cpu(); 314 mm = vma->vm_mm;
315
316 tsb_index = MM_TSB_BASE;
317 tsb_hash_shift = PAGE_SHIFT;
318
319 spin_lock_irqsave(&mm->context.lock, flags);
320
321#ifdef CONFIG_HUGETLB_PAGE
322 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
323 if ((tlb_type == hypervisor &&
324 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
325 (tlb_type != hypervisor &&
326 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
327 tsb_index = MM_TSB_HUGE;
328 tsb_hash_shift = HPAGE_SHIFT;
329 }
271 } 330 }
331#endif
332
333 tsb = mm->context.tsb_block[tsb_index].tsb;
334 tsb += ((address >> tsb_hash_shift) &
335 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
336 tag = (address >> 22UL);
337 tsb_insert(tsb, tag, pte_val(pte));
338
339 spin_unlock_irqrestore(&mm->context.lock, flags);
272} 340}
273 341
274void flush_dcache_page(struct page *page) 342void flush_dcache_page(struct page *page)
@@ -276,6 +344,9 @@ void flush_dcache_page(struct page *page)
276 struct address_space *mapping; 344 struct address_space *mapping;
277 int this_cpu; 345 int this_cpu;
278 346
347 if (tlb_type == hypervisor)
348 return;
349
279 /* Do not bother with the expensive D-cache flush if it 350 /* Do not bother with the expensive D-cache flush if it
280 * is merely the zero page. The 'bigcore' testcase in GDB 351 * is merely the zero page. The 'bigcore' testcase in GDB
281 * causes this case to run millions of times. 352 * causes this case to run millions of times.
@@ -311,7 +382,7 @@ out:
311 382
312void __kprobes flush_icache_range(unsigned long start, unsigned long end) 383void __kprobes flush_icache_range(unsigned long start, unsigned long end)
313{ 384{
314 /* Cheetah has coherent I-cache. */ 385 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
315 if (tlb_type == spitfire) { 386 if (tlb_type == spitfire) {
316 unsigned long kaddr; 387 unsigned long kaddr;
317 388
@@ -320,16 +391,6 @@ void __kprobes flush_icache_range(unsigned long start, unsigned long end)
320 } 391 }
321} 392}
322 393
323unsigned long page_to_pfn(struct page *page)
324{
325 return (unsigned long) ((page - mem_map) + pfn_base);
326}
327
328struct page *pfn_to_page(unsigned long pfn)
329{
330 return (mem_map + (pfn - pfn_base));
331}
332
333void show_mem(void) 394void show_mem(void)
334{ 395{
335 printk("Mem-info:\n"); 396 printk("Mem-info:\n");
@@ -338,7 +399,6 @@ void show_mem(void)
338 nr_swap_pages << (PAGE_SHIFT-10)); 399 nr_swap_pages << (PAGE_SHIFT-10));
339 printk("%ld pages of RAM\n", num_physpages); 400 printk("%ld pages of RAM\n", num_physpages);
340 printk("%d free pages\n", nr_free_pages()); 401 printk("%d free pages\n", nr_free_pages());
341 printk("%d pages in page table cache\n",pgtable_cache_size);
342} 402}
343 403
344void mmu_info(struct seq_file *m) 404void mmu_info(struct seq_file *m)
@@ -349,6 +409,8 @@ void mmu_info(struct seq_file *m)
349 seq_printf(m, "MMU Type\t: Cheetah+\n"); 409 seq_printf(m, "MMU Type\t: Cheetah+\n");
350 else if (tlb_type == spitfire) 410 else if (tlb_type == spitfire)
351 seq_printf(m, "MMU Type\t: Spitfire\n"); 411 seq_printf(m, "MMU Type\t: Spitfire\n");
412 else if (tlb_type == hypervisor)
413 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
352 else 414 else
353 seq_printf(m, "MMU Type\t: ???\n"); 415 seq_printf(m, "MMU Type\t: ???\n");
354 416
@@ -371,45 +433,13 @@ struct linux_prom_translation {
371/* Exported for kernel TLB miss handling in ktlb.S */ 433/* Exported for kernel TLB miss handling in ktlb.S */
372struct linux_prom_translation prom_trans[512] __read_mostly; 434struct linux_prom_translation prom_trans[512] __read_mostly;
373unsigned int prom_trans_ents __read_mostly; 435unsigned int prom_trans_ents __read_mostly;
374unsigned int swapper_pgd_zero __read_mostly;
375
376extern unsigned long prom_boot_page;
377extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
378extern int prom_get_mmu_ihandle(void);
379extern void register_prom_callbacks(void);
380 436
381/* Exported for SMP bootup purposes. */ 437/* Exported for SMP bootup purposes. */
382unsigned long kern_locked_tte_data; 438unsigned long kern_locked_tte_data;
383 439
384/*
385 * Translate PROM's mapping we capture at boot time into physical address.
386 * The second parameter is only set from prom_callback() invocations.
387 */
388unsigned long prom_virt_to_phys(unsigned long promva, int *error)
389{
390 int i;
391
392 for (i = 0; i < prom_trans_ents; i++) {
393 struct linux_prom_translation *p = &prom_trans[i];
394
395 if (promva >= p->virt &&
396 promva < (p->virt + p->size)) {
397 unsigned long base = p->data & _PAGE_PADDR;
398
399 if (error)
400 *error = 0;
401 return base + (promva & (8192 - 1));
402 }
403 }
404 if (error)
405 *error = 1;
406 return 0UL;
407}
408
409/* The obp translations are saved based on 8k pagesize, since obp can 440/* The obp translations are saved based on 8k pagesize, since obp can
410 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS -> 441 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
411 * HI_OBP_ADDRESS range are handled in ktlb.S and do not use the vpte 442 * HI_OBP_ADDRESS range are handled in ktlb.S.
412 * scheme (also, see rant in inherit_locked_prom_mappings()).
413 */ 443 */
414static inline int in_obp_range(unsigned long vaddr) 444static inline int in_obp_range(unsigned long vaddr)
415{ 445{
@@ -490,6 +520,36 @@ static void __init read_obp_translations(void)
490 } 520 }
491} 521}
492 522
523static void __init hypervisor_tlb_lock(unsigned long vaddr,
524 unsigned long pte,
525 unsigned long mmu)
526{
527 register unsigned long func asm("%o5");
528 register unsigned long arg0 asm("%o0");
529 register unsigned long arg1 asm("%o1");
530 register unsigned long arg2 asm("%o2");
531 register unsigned long arg3 asm("%o3");
532
533 func = HV_FAST_MMU_MAP_PERM_ADDR;
534 arg0 = vaddr;
535 arg1 = 0;
536 arg2 = pte;
537 arg3 = mmu;
538 __asm__ __volatile__("ta 0x80"
539 : "=&r" (func), "=&r" (arg0),
540 "=&r" (arg1), "=&r" (arg2),
541 "=&r" (arg3)
542 : "0" (func), "1" (arg0), "2" (arg1),
543 "3" (arg2), "4" (arg3));
544 if (arg0 != 0) {
545 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
546 "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
547 prom_halt();
548 }
549}
550
551static unsigned long kern_large_tte(unsigned long paddr);
552
493static void __init remap_kernel(void) 553static void __init remap_kernel(void)
494{ 554{
495 unsigned long phys_page, tte_vaddr, tte_data; 555 unsigned long phys_page, tte_vaddr, tte_data;
@@ -497,25 +557,34 @@ static void __init remap_kernel(void)
497 557
498 tte_vaddr = (unsigned long) KERNBASE; 558 tte_vaddr = (unsigned long) KERNBASE;
499 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL; 559 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
500 tte_data = (phys_page | (_PAGE_VALID | _PAGE_SZ4MB | 560 tte_data = kern_large_tte(phys_page);
501 _PAGE_CP | _PAGE_CV | _PAGE_P |
502 _PAGE_L | _PAGE_W));
503 561
504 kern_locked_tte_data = tte_data; 562 kern_locked_tte_data = tte_data;
505 563
506 /* Now lock us into the TLBs via OBP. */ 564 /* Now lock us into the TLBs via Hypervisor or OBP. */
507 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr); 565 if (tlb_type == hypervisor) {
508 prom_itlb_load(tlb_ent, tte_data, tte_vaddr); 566 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
509 if (bigkernel) { 567 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
510 tlb_ent -= 1; 568 if (bigkernel) {
511 prom_dtlb_load(tlb_ent, 569 tte_vaddr += 0x400000;
512 tte_data + 0x400000, 570 tte_data += 0x400000;
513 tte_vaddr + 0x400000); 571 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
514 prom_itlb_load(tlb_ent, 572 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
515 tte_data + 0x400000, 573 }
516 tte_vaddr + 0x400000); 574 } else {
575 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
576 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
577 if (bigkernel) {
578 tlb_ent -= 1;
579 prom_dtlb_load(tlb_ent,
580 tte_data + 0x400000,
581 tte_vaddr + 0x400000);
582 prom_itlb_load(tlb_ent,
583 tte_data + 0x400000,
584 tte_vaddr + 0x400000);
585 }
586 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
517 } 587 }
518 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
519 if (tlb_type == cheetah_plus) { 588 if (tlb_type == cheetah_plus) {
520 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 | 589 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
521 CTX_CHEETAH_PLUS_NUC); 590 CTX_CHEETAH_PLUS_NUC);
@@ -533,372 +602,14 @@ static void __init inherit_prom_mappings(void)
533 prom_printf("Remapping the kernel... "); 602 prom_printf("Remapping the kernel... ");
534 remap_kernel(); 603 remap_kernel();
535 prom_printf("done.\n"); 604 prom_printf("done.\n");
536
537 prom_printf("Registering callbacks... ");
538 register_prom_callbacks();
539 prom_printf("done.\n");
540} 605}
541 606
542/* The OBP specifications for sun4u mark 0xfffffffc00000000 and
543 * upwards as reserved for use by the firmware (I wonder if this
544 * will be the same on Cheetah...). We use this virtual address
545 * range for the VPTE table mappings of the nucleus so we need
546 * to zap them when we enter the PROM. -DaveM
547 */
548static void __flush_nucleus_vptes(void)
549{
550 unsigned long prom_reserved_base = 0xfffffffc00000000UL;
551 int i;
552
553 /* Only DTLB must be checked for VPTE entries. */
554 if (tlb_type == spitfire) {
555 for (i = 0; i < 63; i++) {
556 unsigned long tag;
557
558 /* Spitfire Errata #32 workaround */
559 /* NOTE: Always runs on spitfire, so no cheetah+
560 * page size encodings.
561 */
562 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
563 "flush %%g6"
564 : /* No outputs */
565 : "r" (0),
566 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
567
568 tag = spitfire_get_dtlb_tag(i);
569 if (((tag & ~(PAGE_MASK)) == 0) &&
570 ((tag & (PAGE_MASK)) >= prom_reserved_base)) {
571 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
572 "membar #Sync"
573 : /* no outputs */
574 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
575 spitfire_put_dtlb_data(i, 0x0UL);
576 }
577 }
578 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
579 for (i = 0; i < 512; i++) {
580 unsigned long tag = cheetah_get_dtlb_tag(i, 2);
581
582 if ((tag & ~PAGE_MASK) == 0 &&
583 (tag & PAGE_MASK) >= prom_reserved_base) {
584 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
585 "membar #Sync"
586 : /* no outputs */
587 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
588 cheetah_put_dtlb_data(i, 0x0UL, 2);
589 }
590
591 if (tlb_type != cheetah_plus)
592 continue;
593
594 tag = cheetah_get_dtlb_tag(i, 3);
595
596 if ((tag & ~PAGE_MASK) == 0 &&
597 (tag & PAGE_MASK) >= prom_reserved_base) {
598 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
599 "membar #Sync"
600 : /* no outputs */
601 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
602 cheetah_put_dtlb_data(i, 0x0UL, 3);
603 }
604 }
605 } else {
606 /* Implement me :-) */
607 BUG();
608 }
609}
610
611static int prom_ditlb_set;
612struct prom_tlb_entry {
613 int tlb_ent;
614 unsigned long tlb_tag;
615 unsigned long tlb_data;
616};
617struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
618
619void prom_world(int enter) 607void prom_world(int enter)
620{ 608{
621 unsigned long pstate;
622 int i;
623
624 if (!enter) 609 if (!enter)
625 set_fs((mm_segment_t) { get_thread_current_ds() }); 610 set_fs((mm_segment_t) { get_thread_current_ds() });
626 611
627 if (!prom_ditlb_set) 612 __asm__ __volatile__("flushw");
628 return;
629
630 /* Make sure the following runs atomically. */
631 __asm__ __volatile__("flushw\n\t"
632 "rdpr %%pstate, %0\n\t"
633 "wrpr %0, %1, %%pstate"
634 : "=r" (pstate)
635 : "i" (PSTATE_IE));
636
637 if (enter) {
638 /* Kick out nucleus VPTEs. */
639 __flush_nucleus_vptes();
640
641 /* Install PROM world. */
642 for (i = 0; i < 16; i++) {
643 if (prom_dtlb[i].tlb_ent != -1) {
644 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
645 "membar #Sync"
646 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
647 "i" (ASI_DMMU));
648 if (tlb_type == spitfire)
649 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
650 prom_dtlb[i].tlb_data);
651 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
652 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
653 prom_dtlb[i].tlb_data);
654 }
655 if (prom_itlb[i].tlb_ent != -1) {
656 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
657 "membar #Sync"
658 : : "r" (prom_itlb[i].tlb_tag),
659 "r" (TLB_TAG_ACCESS),
660 "i" (ASI_IMMU));
661 if (tlb_type == spitfire)
662 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
663 prom_itlb[i].tlb_data);
664 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
665 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
666 prom_itlb[i].tlb_data);
667 }
668 }
669 } else {
670 for (i = 0; i < 16; i++) {
671 if (prom_dtlb[i].tlb_ent != -1) {
672 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
673 "membar #Sync"
674 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
675 if (tlb_type == spitfire)
676 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
677 else
678 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
679 }
680 if (prom_itlb[i].tlb_ent != -1) {
681 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
682 "membar #Sync"
683 : : "r" (TLB_TAG_ACCESS),
684 "i" (ASI_IMMU));
685 if (tlb_type == spitfire)
686 spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
687 else
688 cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
689 }
690 }
691 }
692 __asm__ __volatile__("wrpr %0, 0, %%pstate"
693 : : "r" (pstate));
694}
695
696void inherit_locked_prom_mappings(int save_p)
697{
698 int i;
699 int dtlb_seen = 0;
700 int itlb_seen = 0;
701
702 /* Fucking losing PROM has more mappings in the TLB, but
703 * it (conveniently) fails to mention any of these in the
704 * translations property. The only ones that matter are
705 * the locked PROM tlb entries, so we impose the following
706 * irrecovable rule on the PROM, it is allowed 8 locked
707 * entries in the ITLB and 8 in the DTLB.
708 *
709 * Supposedly the upper 16GB of the address space is
710 * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
711 * SOMEWHERE!!!!!!!!!!!!!!!!! Furthermore the entire interface
712 * used between the client program and the firmware on sun5
713 * systems to coordinate mmu mappings is also COMPLETELY
714 * UNDOCUMENTED!!!!!! Thanks S(t)un!
715 */
716 if (save_p) {
717 for (i = 0; i < 16; i++) {
718 prom_itlb[i].tlb_ent = -1;
719 prom_dtlb[i].tlb_ent = -1;
720 }
721 }
722 if (tlb_type == spitfire) {
723 int high = sparc64_highest_unlocked_tlb_ent;
724 for (i = 0; i <= high; i++) {
725 unsigned long data;
726
727 /* Spitfire Errata #32 workaround */
728 /* NOTE: Always runs on spitfire, so no cheetah+
729 * page size encodings.
730 */
731 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
732 "flush %%g6"
733 : /* No outputs */
734 : "r" (0),
735 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
736
737 data = spitfire_get_dtlb_data(i);
738 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
739 unsigned long tag;
740
741 /* Spitfire Errata #32 workaround */
742 /* NOTE: Always runs on spitfire, so no
743 * cheetah+ page size encodings.
744 */
745 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
746 "flush %%g6"
747 : /* No outputs */
748 : "r" (0),
749 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
750
751 tag = spitfire_get_dtlb_tag(i);
752 if (save_p) {
753 prom_dtlb[dtlb_seen].tlb_ent = i;
754 prom_dtlb[dtlb_seen].tlb_tag = tag;
755 prom_dtlb[dtlb_seen].tlb_data = data;
756 }
757 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
758 "membar #Sync"
759 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
760 spitfire_put_dtlb_data(i, 0x0UL);
761
762 dtlb_seen++;
763 if (dtlb_seen > 15)
764 break;
765 }
766 }
767
768 for (i = 0; i < high; i++) {
769 unsigned long data;
770
771 /* Spitfire Errata #32 workaround */
772 /* NOTE: Always runs on spitfire, so no
773 * cheetah+ page size encodings.
774 */
775 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
776 "flush %%g6"
777 : /* No outputs */
778 : "r" (0),
779 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
780
781 data = spitfire_get_itlb_data(i);
782 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
783 unsigned long tag;
784
785 /* Spitfire Errata #32 workaround */
786 /* NOTE: Always runs on spitfire, so no
787 * cheetah+ page size encodings.
788 */
789 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
790 "flush %%g6"
791 : /* No outputs */
792 : "r" (0),
793 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
794
795 tag = spitfire_get_itlb_tag(i);
796 if (save_p) {
797 prom_itlb[itlb_seen].tlb_ent = i;
798 prom_itlb[itlb_seen].tlb_tag = tag;
799 prom_itlb[itlb_seen].tlb_data = data;
800 }
801 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
802 "membar #Sync"
803 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
804 spitfire_put_itlb_data(i, 0x0UL);
805
806 itlb_seen++;
807 if (itlb_seen > 15)
808 break;
809 }
810 }
811 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
812 int high = sparc64_highest_unlocked_tlb_ent;
813
814 for (i = 0; i <= high; i++) {
815 unsigned long data;
816
817 data = cheetah_get_ldtlb_data(i);
818 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
819 unsigned long tag;
820
821 tag = cheetah_get_ldtlb_tag(i);
822 if (save_p) {
823 prom_dtlb[dtlb_seen].tlb_ent = i;
824 prom_dtlb[dtlb_seen].tlb_tag = tag;
825 prom_dtlb[dtlb_seen].tlb_data = data;
826 }
827 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
828 "membar #Sync"
829 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
830 cheetah_put_ldtlb_data(i, 0x0UL);
831
832 dtlb_seen++;
833 if (dtlb_seen > 15)
834 break;
835 }
836 }
837
838 for (i = 0; i < high; i++) {
839 unsigned long data;
840
841 data = cheetah_get_litlb_data(i);
842 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
843 unsigned long tag;
844
845 tag = cheetah_get_litlb_tag(i);
846 if (save_p) {
847 prom_itlb[itlb_seen].tlb_ent = i;
848 prom_itlb[itlb_seen].tlb_tag = tag;
849 prom_itlb[itlb_seen].tlb_data = data;
850 }
851 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
852 "membar #Sync"
853 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
854 cheetah_put_litlb_data(i, 0x0UL);
855
856 itlb_seen++;
857 if (itlb_seen > 15)
858 break;
859 }
860 }
861 } else {
862 /* Implement me :-) */
863 BUG();
864 }
865 if (save_p)
866 prom_ditlb_set = 1;
867}
868
869/* Give PROM back his world, done during reboots... */
870void prom_reload_locked(void)
871{
872 int i;
873
874 for (i = 0; i < 16; i++) {
875 if (prom_dtlb[i].tlb_ent != -1) {
876 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
877 "membar #Sync"
878 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
879 "i" (ASI_DMMU));
880 if (tlb_type == spitfire)
881 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
882 prom_dtlb[i].tlb_data);
883 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
884 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
885 prom_dtlb[i].tlb_data);
886 }
887
888 if (prom_itlb[i].tlb_ent != -1) {
889 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
890 "membar #Sync"
891 : : "r" (prom_itlb[i].tlb_tag),
892 "r" (TLB_TAG_ACCESS),
893 "i" (ASI_IMMU));
894 if (tlb_type == spitfire)
895 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
896 prom_itlb[i].tlb_data);
897 else
898 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
899 prom_itlb[i].tlb_data);
900 }
901 }
902} 613}
903 614
904#ifdef DCACHE_ALIASING_POSSIBLE 615#ifdef DCACHE_ALIASING_POSSIBLE
@@ -914,7 +625,7 @@ void __flush_dcache_range(unsigned long start, unsigned long end)
914 if (++n >= 512) 625 if (++n >= 512)
915 break; 626 break;
916 } 627 }
917 } else { 628 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
918 start = __pa(start); 629 start = __pa(start);
919 end = __pa(end); 630 end = __pa(end);
920 for (va = start; va < end; va += 32) 631 for (va = start; va < end; va += 32)
@@ -927,63 +638,6 @@ void __flush_dcache_range(unsigned long start, unsigned long end)
927} 638}
928#endif /* DCACHE_ALIASING_POSSIBLE */ 639#endif /* DCACHE_ALIASING_POSSIBLE */
929 640
930/* If not locked, zap it. */
931void __flush_tlb_all(void)
932{
933 unsigned long pstate;
934 int i;
935
936 __asm__ __volatile__("flushw\n\t"
937 "rdpr %%pstate, %0\n\t"
938 "wrpr %0, %1, %%pstate"
939 : "=r" (pstate)
940 : "i" (PSTATE_IE));
941 if (tlb_type == spitfire) {
942 for (i = 0; i < 64; i++) {
943 /* Spitfire Errata #32 workaround */
944 /* NOTE: Always runs on spitfire, so no
945 * cheetah+ page size encodings.
946 */
947 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
948 "flush %%g6"
949 : /* No outputs */
950 : "r" (0),
951 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
952
953 if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
954 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
955 "membar #Sync"
956 : /* no outputs */
957 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
958 spitfire_put_dtlb_data(i, 0x0UL);
959 }
960
961 /* Spitfire Errata #32 workaround */
962 /* NOTE: Always runs on spitfire, so no
963 * cheetah+ page size encodings.
964 */
965 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
966 "flush %%g6"
967 : /* No outputs */
968 : "r" (0),
969 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
970
971 if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
972 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
973 "membar #Sync"
974 : /* no outputs */
975 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
976 spitfire_put_itlb_data(i, 0x0UL);
977 }
978 }
979 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
980 cheetah_flush_dtlb_all();
981 cheetah_flush_itlb_all();
982 }
983 __asm__ __volatile__("wrpr %0, 0, %%pstate"
984 : : "r" (pstate));
985}
986
987/* Caller does TLB context flushing on local CPU if necessary. 641/* Caller does TLB context flushing on local CPU if necessary.
988 * The caller also ensures that CTX_VALID(mm->context) is false. 642 * The caller also ensures that CTX_VALID(mm->context) is false.
989 * 643 *
@@ -991,17 +645,21 @@ void __flush_tlb_all(void)
991 * let the user have CTX 0 (nucleus) or we ever use a CTX 645 * let the user have CTX 0 (nucleus) or we ever use a CTX
992 * version of zero (and thus NO_CONTEXT would not be caught 646 * version of zero (and thus NO_CONTEXT would not be caught
993 * by version mis-match tests in mmu_context.h). 647 * by version mis-match tests in mmu_context.h).
648 *
649 * Always invoked with interrupts disabled.
994 */ 650 */
995void get_new_mmu_context(struct mm_struct *mm) 651void get_new_mmu_context(struct mm_struct *mm)
996{ 652{
997 unsigned long ctx, new_ctx; 653 unsigned long ctx, new_ctx;
998 unsigned long orig_pgsz_bits; 654 unsigned long orig_pgsz_bits;
999 655 unsigned long flags;
656 int new_version;
1000 657
1001 spin_lock(&ctx_alloc_lock); 658 spin_lock_irqsave(&ctx_alloc_lock, flags);
1002 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); 659 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
1003 ctx = (tlb_context_cache + 1) & CTX_NR_MASK; 660 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
1004 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); 661 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
662 new_version = 0;
1005 if (new_ctx >= (1 << CTX_NR_BITS)) { 663 if (new_ctx >= (1 << CTX_NR_BITS)) {
1006 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); 664 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
1007 if (new_ctx >= ctx) { 665 if (new_ctx >= ctx) {
@@ -1024,6 +682,7 @@ void get_new_mmu_context(struct mm_struct *mm)
1024 mmu_context_bmap[i + 2] = 0; 682 mmu_context_bmap[i + 2] = 0;
1025 mmu_context_bmap[i + 3] = 0; 683 mmu_context_bmap[i + 3] = 0;
1026 } 684 }
685 new_version = 1;
1027 goto out; 686 goto out;
1028 } 687 }
1029 } 688 }
@@ -1032,79 +691,10 @@ void get_new_mmu_context(struct mm_struct *mm)
1032out: 691out:
1033 tlb_context_cache = new_ctx; 692 tlb_context_cache = new_ctx;
1034 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; 693 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
1035 spin_unlock(&ctx_alloc_lock); 694 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
1036}
1037
1038#ifndef CONFIG_SMP
1039struct pgtable_cache_struct pgt_quicklists;
1040#endif
1041 695
1042/* OK, we have to color these pages. The page tables are accessed 696 if (unlikely(new_version))
1043 * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S 697 smp_new_mmu_context_version();
1044 * code, as well as by PAGE_OFFSET range direct-mapped addresses by
1045 * other parts of the kernel. By coloring, we make sure that the tlbmiss
1046 * fast handlers do not get data from old/garbage dcache lines that
1047 * correspond to an old/stale virtual address (user/kernel) that
1048 * previously mapped the pagetable page while accessing vpte range
1049 * addresses. The idea is that if the vpte color and PAGE_OFFSET range
1050 * color is the same, then when the kernel initializes the pagetable
1051 * using the later address range, accesses with the first address
1052 * range will see the newly initialized data rather than the garbage.
1053 */
1054#ifdef DCACHE_ALIASING_POSSIBLE
1055#define DC_ALIAS_SHIFT 1
1056#else
1057#define DC_ALIAS_SHIFT 0
1058#endif
1059pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
1060{
1061 struct page *page;
1062 unsigned long color;
1063
1064 {
1065 pte_t *ptep = pte_alloc_one_fast(mm, address);
1066
1067 if (ptep)
1068 return ptep;
1069 }
1070
1071 color = VPTE_COLOR(address);
1072 page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
1073 if (page) {
1074 unsigned long *to_free;
1075 unsigned long paddr;
1076 pte_t *pte;
1077
1078#ifdef DCACHE_ALIASING_POSSIBLE
1079 set_page_count(page, 1);
1080 ClearPageCompound(page);
1081
1082 set_page_count((page + 1), 1);
1083 ClearPageCompound(page + 1);
1084#endif
1085 paddr = (unsigned long) page_address(page);
1086 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1087
1088 if (!color) {
1089 pte = (pte_t *) paddr;
1090 to_free = (unsigned long *) (paddr + PAGE_SIZE);
1091 } else {
1092 pte = (pte_t *) (paddr + PAGE_SIZE);
1093 to_free = (unsigned long *) paddr;
1094 }
1095
1096#ifdef DCACHE_ALIASING_POSSIBLE
1097 /* Now free the other one up, adjust cache size. */
1098 preempt_disable();
1099 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1100 pte_quicklist[color ^ 0x1] = to_free;
1101 pgtable_cache_size++;
1102 preempt_enable();
1103#endif
1104
1105 return pte;
1106 }
1107 return NULL;
1108} 698}
1109 699
1110void sparc_ultra_dump_itlb(void) 700void sparc_ultra_dump_itlb(void)
@@ -1196,9 +786,78 @@ void sparc_ultra_dump_dtlb(void)
1196 786
1197extern unsigned long cmdline_memory_size; 787extern unsigned long cmdline_memory_size;
1198 788
1199unsigned long __init bootmem_init(unsigned long *pages_avail) 789/* Find a free area for the bootmem map, avoiding the kernel image
790 * and the initial ramdisk.
791 */
792static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
793 unsigned long end_pfn)
1200{ 794{
1201 unsigned long bootmap_size, start_pfn, end_pfn; 795 unsigned long avoid_start, avoid_end, bootmap_size;
796 int i;
797
798 bootmap_size = ((end_pfn - start_pfn) + 7) / 8;
799 bootmap_size = ALIGN(bootmap_size, sizeof(long));
800
801 avoid_start = avoid_end = 0;
802#ifdef CONFIG_BLK_DEV_INITRD
803 avoid_start = initrd_start;
804 avoid_end = PAGE_ALIGN(initrd_end);
805#endif
806
807#ifdef CONFIG_DEBUG_BOOTMEM
808 prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n",
809 kern_base, PAGE_ALIGN(kern_base + kern_size),
810 avoid_start, avoid_end);
811#endif
812 for (i = 0; i < pavail_ents; i++) {
813 unsigned long start, end;
814
815 start = pavail[i].phys_addr;
816 end = start + pavail[i].reg_size;
817
818 while (start < end) {
819 if (start >= kern_base &&
820 start < PAGE_ALIGN(kern_base + kern_size)) {
821 start = PAGE_ALIGN(kern_base + kern_size);
822 continue;
823 }
824 if (start >= avoid_start && start < avoid_end) {
825 start = avoid_end;
826 continue;
827 }
828
829 if ((end - start) < bootmap_size)
830 break;
831
832 if (start < kern_base &&
833 (start + bootmap_size) > kern_base) {
834 start = PAGE_ALIGN(kern_base + kern_size);
835 continue;
836 }
837
838 if (start < avoid_start &&
839 (start + bootmap_size) > avoid_start) {
840 start = avoid_end;
841 continue;
842 }
843
844 /* OK, it doesn't overlap anything, use it. */
845#ifdef CONFIG_DEBUG_BOOTMEM
846 prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n",
847 start >> PAGE_SHIFT, start);
848#endif
849 return start >> PAGE_SHIFT;
850 }
851 }
852
853 prom_printf("Cannot find free area for bootmap, aborting.\n");
854 prom_halt();
855}
856
857static unsigned long __init bootmem_init(unsigned long *pages_avail,
858 unsigned long phys_base)
859{
860 unsigned long bootmap_size, end_pfn;
1202 unsigned long end_of_phys_memory = 0UL; 861 unsigned long end_of_phys_memory = 0UL;
1203 unsigned long bootmap_pfn, bytes_avail, size; 862 unsigned long bootmap_pfn, bytes_avail, size;
1204 int i; 863 int i;
@@ -1236,14 +895,6 @@ unsigned long __init bootmem_init(unsigned long *pages_avail)
1236 895
1237 *pages_avail = bytes_avail >> PAGE_SHIFT; 896 *pages_avail = bytes_avail >> PAGE_SHIFT;
1238 897
1239 /* Start with page aligned address of last symbol in kernel
1240 * image. The kernel is hard mapped below PAGE_OFFSET in a
1241 * 4MB locked TLB translation.
1242 */
1243 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1244
1245 bootmap_pfn = start_pfn;
1246
1247 end_pfn = end_of_phys_memory >> PAGE_SHIFT; 898 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1248 899
1249#ifdef CONFIG_BLK_DEV_INITRD 900#ifdef CONFIG_BLK_DEV_INITRD
@@ -1260,23 +911,22 @@ unsigned long __init bootmem_init(unsigned long *pages_avail)
1260 "(0x%016lx > 0x%016lx)\ndisabling initrd\n", 911 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1261 initrd_end, end_of_phys_memory); 912 initrd_end, end_of_phys_memory);
1262 initrd_start = 0; 913 initrd_start = 0;
1263 } 914 initrd_end = 0;
1264 if (initrd_start) {
1265 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1266 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1267 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1268 } 915 }
1269 } 916 }
1270#endif 917#endif
1271 /* Initialize the boot-time allocator. */ 918 /* Initialize the boot-time allocator. */
1272 max_pfn = max_low_pfn = end_pfn; 919 max_pfn = max_low_pfn = end_pfn;
1273 min_low_pfn = pfn_base; 920 min_low_pfn = (phys_base >> PAGE_SHIFT);
921
922 bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
1274 923
1275#ifdef CONFIG_DEBUG_BOOTMEM 924#ifdef CONFIG_DEBUG_BOOTMEM
1276 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n", 925 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1277 min_low_pfn, bootmap_pfn, max_low_pfn); 926 min_low_pfn, bootmap_pfn, max_low_pfn);
1278#endif 927#endif
1279 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn); 928 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
929 min_low_pfn, end_pfn);
1280 930
1281 /* Now register the available physical memory with the 931 /* Now register the available physical memory with the
1282 * allocator. 932 * allocator.
@@ -1324,9 +974,26 @@ unsigned long __init bootmem_init(unsigned long *pages_avail)
1324 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size); 974 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1325 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT; 975 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1326 976
977 for (i = 0; i < pavail_ents; i++) {
978 unsigned long start_pfn, end_pfn;
979
980 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
981 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
982#ifdef CONFIG_DEBUG_BOOTMEM
983 prom_printf("memory_present(0, %lx, %lx)\n",
984 start_pfn, end_pfn);
985#endif
986 memory_present(0, start_pfn, end_pfn);
987 }
988
989 sparse_init();
990
1327 return end_pfn; 991 return end_pfn;
1328} 992}
1329 993
994static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
995static int pall_ents __initdata;
996
1330#ifdef CONFIG_DEBUG_PAGEALLOC 997#ifdef CONFIG_DEBUG_PAGEALLOC
1331static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot) 998static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1332{ 999{
@@ -1382,14 +1049,44 @@ static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend,
1382 return alloc_bytes; 1049 return alloc_bytes;
1383} 1050}
1384 1051
1385static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1386static int pall_ents __initdata;
1387
1388extern unsigned int kvmap_linear_patch[1]; 1052extern unsigned int kvmap_linear_patch[1];
1053#endif /* CONFIG_DEBUG_PAGEALLOC */
1054
1055static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1056{
1057 const unsigned long shift_256MB = 28;
1058 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1059 const unsigned long size_256MB = (1UL << shift_256MB);
1060
1061 while (start < end) {
1062 long remains;
1063
1064 remains = end - start;
1065 if (remains < size_256MB)
1066 break;
1067
1068 if (start & mask_256MB) {
1069 start = (start + size_256MB) & ~mask_256MB;
1070 continue;
1071 }
1072
1073 while (remains >= size_256MB) {
1074 unsigned long index = start >> shift_256MB;
1075
1076 __set_bit(index, kpte_linear_bitmap);
1077
1078 start += size_256MB;
1079 remains -= size_256MB;
1080 }
1081 }
1082}
1389 1083
1390static void __init kernel_physical_mapping_init(void) 1084static void __init kernel_physical_mapping_init(void)
1391{ 1085{
1392 unsigned long i, mem_alloced = 0UL; 1086 unsigned long i;
1087#ifdef CONFIG_DEBUG_PAGEALLOC
1088 unsigned long mem_alloced = 0UL;
1089#endif
1393 1090
1394 read_obp_memory("reg", &pall[0], &pall_ents); 1091 read_obp_memory("reg", &pall[0], &pall_ents);
1395 1092
@@ -1398,10 +1095,16 @@ static void __init kernel_physical_mapping_init(void)
1398 1095
1399 phys_start = pall[i].phys_addr; 1096 phys_start = pall[i].phys_addr;
1400 phys_end = phys_start + pall[i].reg_size; 1097 phys_end = phys_start + pall[i].reg_size;
1098
1099 mark_kpte_bitmap(phys_start, phys_end);
1100
1101#ifdef CONFIG_DEBUG_PAGEALLOC
1401 mem_alloced += kernel_map_range(phys_start, phys_end, 1102 mem_alloced += kernel_map_range(phys_start, phys_end,
1402 PAGE_KERNEL); 1103 PAGE_KERNEL);
1104#endif
1403 } 1105 }
1404 1106
1107#ifdef CONFIG_DEBUG_PAGEALLOC
1405 printk("Allocated %ld bytes for kernel page tables.\n", 1108 printk("Allocated %ld bytes for kernel page tables.\n",
1406 mem_alloced); 1109 mem_alloced);
1407 1110
@@ -1409,8 +1112,10 @@ static void __init kernel_physical_mapping_init(void)
1409 flushi(&kvmap_linear_patch[0]); 1112 flushi(&kvmap_linear_patch[0]);
1410 1113
1411 __flush_tlb_all(); 1114 __flush_tlb_all();
1115#endif
1412} 1116}
1413 1117
1118#ifdef CONFIG_DEBUG_PAGEALLOC
1414void kernel_map_pages(struct page *page, int numpages, int enable) 1119void kernel_map_pages(struct page *page, int numpages, int enable)
1415{ 1120{
1416 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT; 1121 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
@@ -1419,6 +1124,9 @@ void kernel_map_pages(struct page *page, int numpages, int enable)
1419 kernel_map_range(phys_start, phys_end, 1124 kernel_map_range(phys_start, phys_end,
1420 (enable ? PAGE_KERNEL : __pgprot(0))); 1125 (enable ? PAGE_KERNEL : __pgprot(0)));
1421 1126
1127 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1128 PAGE_OFFSET + phys_end);
1129
1422 /* we should perform an IPI and flush all tlbs, 1130 /* we should perform an IPI and flush all tlbs,
1423 * but that can deadlock->flush only current cpu. 1131 * but that can deadlock->flush only current cpu.
1424 */ 1132 */
@@ -1439,18 +1147,150 @@ unsigned long __init find_ecache_flush_span(unsigned long size)
1439 return ~0UL; 1147 return ~0UL;
1440} 1148}
1441 1149
1150static void __init tsb_phys_patch(void)
1151{
1152 struct tsb_ldquad_phys_patch_entry *pquad;
1153 struct tsb_phys_patch_entry *p;
1154
1155 pquad = &__tsb_ldquad_phys_patch;
1156 while (pquad < &__tsb_ldquad_phys_patch_end) {
1157 unsigned long addr = pquad->addr;
1158
1159 if (tlb_type == hypervisor)
1160 *(unsigned int *) addr = pquad->sun4v_insn;
1161 else
1162 *(unsigned int *) addr = pquad->sun4u_insn;
1163 wmb();
1164 __asm__ __volatile__("flush %0"
1165 : /* no outputs */
1166 : "r" (addr));
1167
1168 pquad++;
1169 }
1170
1171 p = &__tsb_phys_patch;
1172 while (p < &__tsb_phys_patch_end) {
1173 unsigned long addr = p->addr;
1174
1175 *(unsigned int *) addr = p->insn;
1176 wmb();
1177 __asm__ __volatile__("flush %0"
1178 : /* no outputs */
1179 : "r" (addr));
1180
1181 p++;
1182 }
1183}
1184
1185/* Don't mark as init, we give this to the Hypervisor. */
1186static struct hv_tsb_descr ktsb_descr[2];
1187extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1188
1189static void __init sun4v_ktsb_init(void)
1190{
1191 unsigned long ktsb_pa;
1192
1193 /* First KTSB for PAGE_SIZE mappings. */
1194 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1195
1196 switch (PAGE_SIZE) {
1197 case 8 * 1024:
1198 default:
1199 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1200 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1201 break;
1202
1203 case 64 * 1024:
1204 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1205 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1206 break;
1207
1208 case 512 * 1024:
1209 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1210 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1211 break;
1212
1213 case 4 * 1024 * 1024:
1214 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1215 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1216 break;
1217 };
1218
1219 ktsb_descr[0].assoc = 1;
1220 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1221 ktsb_descr[0].ctx_idx = 0;
1222 ktsb_descr[0].tsb_base = ktsb_pa;
1223 ktsb_descr[0].resv = 0;
1224
1225 /* Second KTSB for 4MB/256MB mappings. */
1226 ktsb_pa = (kern_base +
1227 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1228
1229 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1230 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1231 HV_PGSZ_MASK_256MB);
1232 ktsb_descr[1].assoc = 1;
1233 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1234 ktsb_descr[1].ctx_idx = 0;
1235 ktsb_descr[1].tsb_base = ktsb_pa;
1236 ktsb_descr[1].resv = 0;
1237}
1238
1239void __cpuinit sun4v_ktsb_register(void)
1240{
1241 register unsigned long func asm("%o5");
1242 register unsigned long arg0 asm("%o0");
1243 register unsigned long arg1 asm("%o1");
1244 unsigned long pa;
1245
1246 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1247
1248 func = HV_FAST_MMU_TSB_CTX0;
1249 arg0 = 2;
1250 arg1 = pa;
1251 __asm__ __volatile__("ta %6"
1252 : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1253 : "0" (func), "1" (arg0), "2" (arg1),
1254 "i" (HV_FAST_TRAP));
1255}
1256
1442/* paging_init() sets up the page tables */ 1257/* paging_init() sets up the page tables */
1443 1258
1444extern void cheetah_ecache_flush_init(void); 1259extern void cheetah_ecache_flush_init(void);
1260extern void sun4v_patch_tlb_handlers(void);
1445 1261
1446static unsigned long last_valid_pfn; 1262static unsigned long last_valid_pfn;
1447pgd_t swapper_pg_dir[2048]; 1263pgd_t swapper_pg_dir[2048];
1448 1264
1265static void sun4u_pgprot_init(void);
1266static void sun4v_pgprot_init(void);
1267
1449void __init paging_init(void) 1268void __init paging_init(void)
1450{ 1269{
1451 unsigned long end_pfn, pages_avail, shift; 1270 unsigned long end_pfn, pages_avail, shift, phys_base;
1452 unsigned long real_end, i; 1271 unsigned long real_end, i;
1453 1272
1273 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1274 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1275
1276 /* Invalidate both kernel TSBs. */
1277 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1278 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1279
1280 if (tlb_type == hypervisor)
1281 sun4v_pgprot_init();
1282 else
1283 sun4u_pgprot_init();
1284
1285 if (tlb_type == cheetah_plus ||
1286 tlb_type == hypervisor)
1287 tsb_phys_patch();
1288
1289 if (tlb_type == hypervisor) {
1290 sun4v_patch_tlb_handlers();
1291 sun4v_ktsb_init();
1292 }
1293
1454 /* Find available physical memory... */ 1294 /* Find available physical memory... */
1455 read_obp_memory("available", &pavail[0], &pavail_ents); 1295 read_obp_memory("available", &pavail[0], &pavail_ents);
1456 1296
@@ -1458,11 +1298,6 @@ void __init paging_init(void)
1458 for (i = 0; i < pavail_ents; i++) 1298 for (i = 0; i < pavail_ents; i++)
1459 phys_base = min(phys_base, pavail[i].phys_addr); 1299 phys_base = min(phys_base, pavail[i].phys_addr);
1460 1300
1461 pfn_base = phys_base >> PAGE_SHIFT;
1462
1463 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1464 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1465
1466 set_bit(0, mmu_context_bmap); 1301 set_bit(0, mmu_context_bmap);
1467 1302
1468 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE); 1303 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
@@ -1486,47 +1321,38 @@ void __init paging_init(void)
1486 pud_set(pud_offset(&swapper_pg_dir[0], 0), 1321 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1487 swapper_low_pmd_dir + (shift / sizeof(pgd_t))); 1322 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1488 1323
1489 swapper_pgd_zero = pgd_val(swapper_pg_dir[0]);
1490
1491 inherit_prom_mappings(); 1324 inherit_prom_mappings();
1492 1325
1493 /* Ok, we can use our TLB miss and window trap handlers safely. 1326 /* Ok, we can use our TLB miss and window trap handlers safely. */
1494 * We need to do a quick peek here to see if we are on StarFire 1327 setup_tba();
1495 * or not, so setup_tba can setup the IRQ globals correctly (it
1496 * needs to get the hard smp processor id correctly).
1497 */
1498 {
1499 extern void setup_tba(int);
1500 setup_tba(this_is_starfire);
1501 }
1502
1503 inherit_locked_prom_mappings(1);
1504 1328
1505 __flush_tlb_all(); 1329 __flush_tlb_all();
1506 1330
1331 if (tlb_type == hypervisor)
1332 sun4v_ktsb_register();
1333
1507 /* Setup bootmem... */ 1334 /* Setup bootmem... */
1508 pages_avail = 0; 1335 pages_avail = 0;
1509 last_valid_pfn = end_pfn = bootmem_init(&pages_avail); 1336 last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1337
1338 max_mapnr = last_valid_pfn;
1510 1339
1511#ifdef CONFIG_DEBUG_PAGEALLOC
1512 kernel_physical_mapping_init(); 1340 kernel_physical_mapping_init();
1513#endif
1514 1341
1515 { 1342 {
1516 unsigned long zones_size[MAX_NR_ZONES]; 1343 unsigned long zones_size[MAX_NR_ZONES];
1517 unsigned long zholes_size[MAX_NR_ZONES]; 1344 unsigned long zholes_size[MAX_NR_ZONES];
1518 unsigned long npages;
1519 int znum; 1345 int znum;
1520 1346
1521 for (znum = 0; znum < MAX_NR_ZONES; znum++) 1347 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1522 zones_size[znum] = zholes_size[znum] = 0; 1348 zones_size[znum] = zholes_size[znum] = 0;
1523 1349
1524 npages = end_pfn - pfn_base; 1350 zones_size[ZONE_DMA] = end_pfn;
1525 zones_size[ZONE_DMA] = npages; 1351 zholes_size[ZONE_DMA] = end_pfn - pages_avail;
1526 zholes_size[ZONE_DMA] = npages - pages_avail;
1527 1352
1528 free_area_init_node(0, &contig_page_data, zones_size, 1353 free_area_init_node(0, &contig_page_data, zones_size,
1529 phys_base >> PAGE_SHIFT, zholes_size); 1354 __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1355 zholes_size);
1530 } 1356 }
1531 1357
1532 device_scan(); 1358 device_scan();
@@ -1596,7 +1422,6 @@ void __init mem_init(void)
1596 1422
1597 taint_real_pages(); 1423 taint_real_pages();
1598 1424
1599 max_mapnr = last_valid_pfn - pfn_base;
1600 high_memory = __va(last_valid_pfn << PAGE_SHIFT); 1425 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1601 1426
1602#ifdef CONFIG_DEBUG_BOOTMEM 1427#ifdef CONFIG_DEBUG_BOOTMEM
@@ -1653,7 +1478,7 @@ void free_initmem(void)
1653 p = virt_to_page(page); 1478 p = virt_to_page(page);
1654 1479
1655 ClearPageReserved(p); 1480 ClearPageReserved(p);
1656 set_page_count(p, 1); 1481 init_page_count(p);
1657 __free_page(p); 1482 __free_page(p);
1658 num_physpages++; 1483 num_physpages++;
1659 totalram_pages++; 1484 totalram_pages++;
@@ -1669,10 +1494,349 @@ void free_initrd_mem(unsigned long start, unsigned long end)
1669 struct page *p = virt_to_page(start); 1494 struct page *p = virt_to_page(start);
1670 1495
1671 ClearPageReserved(p); 1496 ClearPageReserved(p);
1672 set_page_count(p, 1); 1497 init_page_count(p);
1673 __free_page(p); 1498 __free_page(p);
1674 num_physpages++; 1499 num_physpages++;
1675 totalram_pages++; 1500 totalram_pages++;
1676 } 1501 }
1677} 1502}
1678#endif 1503#endif
1504
1505#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1506#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1507#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1508#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1509#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1510#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1511
1512pgprot_t PAGE_KERNEL __read_mostly;
1513EXPORT_SYMBOL(PAGE_KERNEL);
1514
1515pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1516pgprot_t PAGE_COPY __read_mostly;
1517
1518pgprot_t PAGE_SHARED __read_mostly;
1519EXPORT_SYMBOL(PAGE_SHARED);
1520
1521pgprot_t PAGE_EXEC __read_mostly;
1522unsigned long pg_iobits __read_mostly;
1523
1524unsigned long _PAGE_IE __read_mostly;
1525
1526unsigned long _PAGE_E __read_mostly;
1527EXPORT_SYMBOL(_PAGE_E);
1528
1529unsigned long _PAGE_CACHE __read_mostly;
1530EXPORT_SYMBOL(_PAGE_CACHE);
1531
1532static void prot_init_common(unsigned long page_none,
1533 unsigned long page_shared,
1534 unsigned long page_copy,
1535 unsigned long page_readonly,
1536 unsigned long page_exec_bit)
1537{
1538 PAGE_COPY = __pgprot(page_copy);
1539 PAGE_SHARED = __pgprot(page_shared);
1540
1541 protection_map[0x0] = __pgprot(page_none);
1542 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1543 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1544 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1545 protection_map[0x4] = __pgprot(page_readonly);
1546 protection_map[0x5] = __pgprot(page_readonly);
1547 protection_map[0x6] = __pgprot(page_copy);
1548 protection_map[0x7] = __pgprot(page_copy);
1549 protection_map[0x8] = __pgprot(page_none);
1550 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1551 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1552 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1553 protection_map[0xc] = __pgprot(page_readonly);
1554 protection_map[0xd] = __pgprot(page_readonly);
1555 protection_map[0xe] = __pgprot(page_shared);
1556 protection_map[0xf] = __pgprot(page_shared);
1557}
1558
1559static void __init sun4u_pgprot_init(void)
1560{
1561 unsigned long page_none, page_shared, page_copy, page_readonly;
1562 unsigned long page_exec_bit;
1563
1564 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1565 _PAGE_CACHE_4U | _PAGE_P_4U |
1566 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1567 _PAGE_EXEC_4U);
1568 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1569 _PAGE_CACHE_4U | _PAGE_P_4U |
1570 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1571 _PAGE_EXEC_4U | _PAGE_L_4U);
1572 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1573
1574 _PAGE_IE = _PAGE_IE_4U;
1575 _PAGE_E = _PAGE_E_4U;
1576 _PAGE_CACHE = _PAGE_CACHE_4U;
1577
1578 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1579 __ACCESS_BITS_4U | _PAGE_E_4U);
1580
1581 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1582 0xfffff80000000000;
1583 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1584 _PAGE_P_4U | _PAGE_W_4U);
1585
1586 /* XXX Should use 256MB on Panther. XXX */
1587 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1588
1589 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1590 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1591 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1592 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1593
1594
1595 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1596 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1597 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1598 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1599 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1600 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1601 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1602
1603 page_exec_bit = _PAGE_EXEC_4U;
1604
1605 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1606 page_exec_bit);
1607}
1608
1609static void __init sun4v_pgprot_init(void)
1610{
1611 unsigned long page_none, page_shared, page_copy, page_readonly;
1612 unsigned long page_exec_bit;
1613
1614 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1615 _PAGE_CACHE_4V | _PAGE_P_4V |
1616 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1617 _PAGE_EXEC_4V);
1618 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1619 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1620
1621 _PAGE_IE = _PAGE_IE_4V;
1622 _PAGE_E = _PAGE_E_4V;
1623 _PAGE_CACHE = _PAGE_CACHE_4V;
1624
1625 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1626 0xfffff80000000000;
1627 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1628 _PAGE_P_4V | _PAGE_W_4V);
1629
1630 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1631 0xfffff80000000000;
1632 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1633 _PAGE_P_4V | _PAGE_W_4V);
1634
1635 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1636 __ACCESS_BITS_4V | _PAGE_E_4V);
1637
1638 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1639 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1640 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1641 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1642 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1643
1644 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1645 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1646 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1647 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1648 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1649 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1650 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1651
1652 page_exec_bit = _PAGE_EXEC_4V;
1653
1654 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1655 page_exec_bit);
1656}
1657
1658unsigned long pte_sz_bits(unsigned long sz)
1659{
1660 if (tlb_type == hypervisor) {
1661 switch (sz) {
1662 case 8 * 1024:
1663 default:
1664 return _PAGE_SZ8K_4V;
1665 case 64 * 1024:
1666 return _PAGE_SZ64K_4V;
1667 case 512 * 1024:
1668 return _PAGE_SZ512K_4V;
1669 case 4 * 1024 * 1024:
1670 return _PAGE_SZ4MB_4V;
1671 };
1672 } else {
1673 switch (sz) {
1674 case 8 * 1024:
1675 default:
1676 return _PAGE_SZ8K_4U;
1677 case 64 * 1024:
1678 return _PAGE_SZ64K_4U;
1679 case 512 * 1024:
1680 return _PAGE_SZ512K_4U;
1681 case 4 * 1024 * 1024:
1682 return _PAGE_SZ4MB_4U;
1683 };
1684 }
1685}
1686
1687pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1688{
1689 pte_t pte;
1690
1691 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
1692 pte_val(pte) |= (((unsigned long)space) << 32);
1693 pte_val(pte) |= pte_sz_bits(page_size);
1694
1695 return pte;
1696}
1697
1698static unsigned long kern_large_tte(unsigned long paddr)
1699{
1700 unsigned long val;
1701
1702 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1703 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1704 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1705 if (tlb_type == hypervisor)
1706 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1707 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1708 _PAGE_EXEC_4V | _PAGE_W_4V);
1709
1710 return val | paddr;
1711}
1712
1713/*
1714 * Translate PROM's mapping we capture at boot time into physical address.
1715 * The second parameter is only set from prom_callback() invocations.
1716 */
1717unsigned long prom_virt_to_phys(unsigned long promva, int *error)
1718{
1719 unsigned long mask;
1720 int i;
1721
1722 mask = _PAGE_PADDR_4U;
1723 if (tlb_type == hypervisor)
1724 mask = _PAGE_PADDR_4V;
1725
1726 for (i = 0; i < prom_trans_ents; i++) {
1727 struct linux_prom_translation *p = &prom_trans[i];
1728
1729 if (promva >= p->virt &&
1730 promva < (p->virt + p->size)) {
1731 unsigned long base = p->data & mask;
1732
1733 if (error)
1734 *error = 0;
1735 return base + (promva & (8192 - 1));
1736 }
1737 }
1738 if (error)
1739 *error = 1;
1740 return 0UL;
1741}
1742
1743/* XXX We should kill off this ugly thing at so me point. XXX */
1744unsigned long sun4u_get_pte(unsigned long addr)
1745{
1746 pgd_t *pgdp;
1747 pud_t *pudp;
1748 pmd_t *pmdp;
1749 pte_t *ptep;
1750 unsigned long mask = _PAGE_PADDR_4U;
1751
1752 if (tlb_type == hypervisor)
1753 mask = _PAGE_PADDR_4V;
1754
1755 if (addr >= PAGE_OFFSET)
1756 return addr & mask;
1757
1758 if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
1759 return prom_virt_to_phys(addr, NULL);
1760
1761 pgdp = pgd_offset_k(addr);
1762 pudp = pud_offset(pgdp, addr);
1763 pmdp = pmd_offset(pudp, addr);
1764 ptep = pte_offset_kernel(pmdp, addr);
1765
1766 return pte_val(*ptep) & mask;
1767}
1768
1769/* If not locked, zap it. */
1770void __flush_tlb_all(void)
1771{
1772 unsigned long pstate;
1773 int i;
1774
1775 __asm__ __volatile__("flushw\n\t"
1776 "rdpr %%pstate, %0\n\t"
1777 "wrpr %0, %1, %%pstate"
1778 : "=r" (pstate)
1779 : "i" (PSTATE_IE));
1780 if (tlb_type == spitfire) {
1781 for (i = 0; i < 64; i++) {
1782 /* Spitfire Errata #32 workaround */
1783 /* NOTE: Always runs on spitfire, so no
1784 * cheetah+ page size encodings.
1785 */
1786 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1787 "flush %%g6"
1788 : /* No outputs */
1789 : "r" (0),
1790 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1791
1792 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1793 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1794 "membar #Sync"
1795 : /* no outputs */
1796 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1797 spitfire_put_dtlb_data(i, 0x0UL);
1798 }
1799
1800 /* Spitfire Errata #32 workaround */
1801 /* NOTE: Always runs on spitfire, so no
1802 * cheetah+ page size encodings.
1803 */
1804 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1805 "flush %%g6"
1806 : /* No outputs */
1807 : "r" (0),
1808 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1809
1810 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1811 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1812 "membar #Sync"
1813 : /* no outputs */
1814 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1815 spitfire_put_itlb_data(i, 0x0UL);
1816 }
1817 }
1818 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1819 cheetah_flush_dtlb_all();
1820 cheetah_flush_itlb_all();
1821 }
1822 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1823 : : "r" (pstate));
1824}
1825
1826#ifdef CONFIG_MEMORY_HOTPLUG
1827
1828void online_page(struct page *page)
1829{
1830 ClearPageReserved(page);
1831 set_page_count(page, 0);
1832 free_cold_page(page);
1833 totalram_pages++;
1834 num_physpages++;
1835}
1836
1837int remove_memory(u64 start, u64 size)
1838{
1839 return -EINVAL;
1840}
1841
1842#endif /* CONFIG_MEMORY_HOTPLUG */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-29 18:37:41 -0400