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authorDavid S. Miller <davem@davemloft.net>2008-11-15 16:33:25 -0500
committerDavid S. Miller <davem@davemloft.net>2008-12-04 12:16:47 -0500
commit293666b7a17cb7a389fc274980439212386a19c4 (patch)
tree075cc7661d2113cf04da7130b3383979d8024206 /arch/sparc64/lib/bitops.S
parent64f2dde3f743c8a1ad8c0a1aa74166c1034afd92 (diff)
sparc64: Stop using memory barriers for atomics and locks.
The kernel always executes in the TSO memory model now, so none of this stuff is necessary any more. With helpful feedback from Nick Piggin. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/lib/bitops.S')
-rw-r--r--arch/sparc64/lib/bitops.S24
1 files changed, 0 insertions, 24 deletions
diff --git a/arch/sparc64/lib/bitops.S b/arch/sparc64/lib/bitops.S
index 6b015a6eefb5..2b7228cb8c22 100644
--- a/arch/sparc64/lib/bitops.S
+++ b/arch/sparc64/lib/bitops.S
@@ -8,29 +8,10 @@
8 8
9 .text 9 .text
10 10
11 /* On SMP we need to use memory barriers to ensure
12 * correct memory operation ordering, nop these out
13 * for uniprocessor.
14 */
15
16#ifdef CONFIG_SMP
17#define BITOP_PRE_BARRIER membar #StoreLoad | #LoadLoad
18#define BITOP_POST_BARRIER \
19 ba,pt %xcc, 80b; \
20 membar #StoreLoad | #StoreStore
21
2280: retl
23 nop
24#else
25#define BITOP_PRE_BARRIER
26#define BITOP_POST_BARRIER
27#endif
28
29 .globl test_and_set_bit 11 .globl test_and_set_bit
30 .type test_and_set_bit,#function 12 .type test_and_set_bit,#function
31test_and_set_bit: /* %o0=nr, %o1=addr */ 13test_and_set_bit: /* %o0=nr, %o1=addr */
32 BACKOFF_SETUP(%o3) 14 BACKOFF_SETUP(%o3)
33 BITOP_PRE_BARRIER
34 srlx %o0, 6, %g1 15 srlx %o0, 6, %g1
35 mov 1, %o2 16 mov 1, %o2
36 sllx %g1, 3, %g3 17 sllx %g1, 3, %g3
@@ -45,7 +26,6 @@ test_and_set_bit: /* %o0=nr, %o1=addr */
45 and %g7, %o2, %g2 26 and %g7, %o2, %g2
46 clr %o0 27 clr %o0
47 movrne %g2, 1, %o0 28 movrne %g2, 1, %o0
48 BITOP_POST_BARRIER
49 retl 29 retl
50 nop 30 nop
512: BACKOFF_SPIN(%o3, %o4, 1b) 312: BACKOFF_SPIN(%o3, %o4, 1b)
@@ -55,7 +35,6 @@ test_and_set_bit: /* %o0=nr, %o1=addr */
55 .type test_and_clear_bit,#function 35 .type test_and_clear_bit,#function
56test_and_clear_bit: /* %o0=nr, %o1=addr */ 36test_and_clear_bit: /* %o0=nr, %o1=addr */
57 BACKOFF_SETUP(%o3) 37 BACKOFF_SETUP(%o3)
58 BITOP_PRE_BARRIER
59 srlx %o0, 6, %g1 38 srlx %o0, 6, %g1
60 mov 1, %o2 39 mov 1, %o2
61 sllx %g1, 3, %g3 40 sllx %g1, 3, %g3
@@ -70,7 +49,6 @@ test_and_clear_bit: /* %o0=nr, %o1=addr */
70 and %g7, %o2, %g2 49 and %g7, %o2, %g2
71 clr %o0 50 clr %o0
72 movrne %g2, 1, %o0 51 movrne %g2, 1, %o0
73 BITOP_POST_BARRIER
74 retl 52 retl
75 nop 53 nop
762: BACKOFF_SPIN(%o3, %o4, 1b) 542: BACKOFF_SPIN(%o3, %o4, 1b)
@@ -80,7 +58,6 @@ test_and_clear_bit: /* %o0=nr, %o1=addr */
80 .type test_and_change_bit,#function 58 .type test_and_change_bit,#function
81test_and_change_bit: /* %o0=nr, %o1=addr */ 59test_and_change_bit: /* %o0=nr, %o1=addr */
82 BACKOFF_SETUP(%o3) 60 BACKOFF_SETUP(%o3)
83 BITOP_PRE_BARRIER
84 srlx %o0, 6, %g1 61 srlx %o0, 6, %g1
85 mov 1, %o2 62 mov 1, %o2
86 sllx %g1, 3, %g3 63 sllx %g1, 3, %g3
@@ -95,7 +72,6 @@ test_and_change_bit: /* %o0=nr, %o1=addr */
95 and %g7, %o2, %g2 72 and %g7, %o2, %g2
96 clr %o0 73 clr %o0
97 movrne %g2, 1, %o0 74 movrne %g2, 1, %o0
98 BITOP_POST_BARRIER
99 retl 75 retl
100 nop 76 nop
1012: BACKOFF_SPIN(%o3, %o4, 1b) 772: BACKOFF_SPIN(%o3, %o4, 1b)