diff options
| author | Jeff Garzik <jgarzik@pobox.com> | 2005-10-11 01:48:37 -0400 |
|---|---|---|
| committer | Jeff Garzik <jgarzik@pobox.com> | 2005-10-11 01:48:37 -0400 |
| commit | 1a04392bd6439876b1552793389cbb5be356ea54 (patch) | |
| tree | 12af7b77e3b0848127f2d2871778c9c1f315578a /arch/sparc64/lib/VISsave.S | |
| parent | 68399bb5080c1d96f2110b0a040b39d3ccd7a18a (diff) | |
| parent | 3c92c2ba33cd7d666c5f83cc32aa590e794e91b0 (diff) | |
Merge branch 'master'
Diffstat (limited to 'arch/sparc64/lib/VISsave.S')
| -rw-r--r-- | arch/sparc64/lib/VISsave.S | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/sparc64/lib/VISsave.S b/arch/sparc64/lib/VISsave.S index 4e18989bd602..a0ded5c5aa5c 100644 --- a/arch/sparc64/lib/VISsave.S +++ b/arch/sparc64/lib/VISsave.S | |||
| @@ -59,15 +59,17 @@ vis1: ldub [%g6 + TI_FPSAVED], %g3 | |||
| 59 | be,pn %icc, 9b | 59 | be,pn %icc, 9b |
| 60 | add %g6, TI_FPREGS, %g2 | 60 | add %g6, TI_FPREGS, %g2 |
| 61 | andcc %o5, FPRS_DL, %g0 | 61 | andcc %o5, FPRS_DL, %g0 |
| 62 | membar #StoreStore | #LoadStore | ||
| 63 | 62 | ||
| 64 | be,pn %icc, 4f | 63 | be,pn %icc, 4f |
| 65 | add %g6, TI_FPREGS+0x40, %g3 | 64 | add %g6, TI_FPREGS+0x40, %g3 |
| 65 | membar #Sync | ||
| 66 | stda %f0, [%g2 + %g1] ASI_BLK_P | 66 | stda %f0, [%g2 + %g1] ASI_BLK_P |
| 67 | stda %f16, [%g3 + %g1] ASI_BLK_P | 67 | stda %f16, [%g3 + %g1] ASI_BLK_P |
| 68 | membar #Sync | ||
| 68 | andcc %o5, FPRS_DU, %g0 | 69 | andcc %o5, FPRS_DU, %g0 |
| 69 | be,pn %icc, 5f | 70 | be,pn %icc, 5f |
| 70 | 4: add %g1, 128, %g1 | 71 | 4: add %g1, 128, %g1 |
| 72 | membar #Sync | ||
| 71 | stda %f32, [%g2 + %g1] ASI_BLK_P | 73 | stda %f32, [%g2 + %g1] ASI_BLK_P |
| 72 | 74 | ||
| 73 | stda %f48, [%g3 + %g1] ASI_BLK_P | 75 | stda %f48, [%g3 + %g1] ASI_BLK_P |
| @@ -87,7 +89,7 @@ vis1: ldub [%g6 + TI_FPSAVED], %g3 | |||
| 87 | sll %g1, 5, %g1 | 89 | sll %g1, 5, %g1 |
| 88 | add %g6, TI_FPREGS+0xc0, %g3 | 90 | add %g6, TI_FPREGS+0xc0, %g3 |
| 89 | wr %g0, FPRS_FEF, %fprs | 91 | wr %g0, FPRS_FEF, %fprs |
| 90 | membar #StoreStore | #LoadStore | 92 | membar #Sync |
| 91 | stda %f32, [%g2 + %g1] ASI_BLK_P | 93 | stda %f32, [%g2 + %g1] ASI_BLK_P |
| 92 | stda %f48, [%g3 + %g1] ASI_BLK_P | 94 | stda %f48, [%g3 + %g1] ASI_BLK_P |
| 93 | membar #Sync | 95 | membar #Sync |
| @@ -128,8 +130,8 @@ VISenterhalf: | |||
| 128 | be,pn %icc, 4f | 130 | be,pn %icc, 4f |
| 129 | add %g6, TI_FPREGS, %g2 | 131 | add %g6, TI_FPREGS, %g2 |
| 130 | 132 | ||
| 131 | membar #StoreStore | #LoadStore | ||
| 132 | add %g6, TI_FPREGS+0x40, %g3 | 133 | add %g6, TI_FPREGS+0x40, %g3 |
| 134 | membar #Sync | ||
| 133 | stda %f0, [%g2 + %g1] ASI_BLK_P | 135 | stda %f0, [%g2 + %g1] ASI_BLK_P |
| 134 | stda %f16, [%g3 + %g1] ASI_BLK_P | 136 | stda %f16, [%g3 + %g1] ASI_BLK_P |
| 135 | membar #Sync | 137 | membar #Sync |