[SPARC64]: Avoid membar instructions in delay slots.

In particular, avoid membar instructions in the delay
slot of a jmpl instruction.

UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51

The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.

If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.

We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 13 insertions, 2 deletions

diff --git a/arch/sparc64/lib/VISsave.S b/arch/sparc64/lib/VISsave.S
index 65e328d600a8..4e18989bd602 100644
--- a/arch/sparc64/lib/VISsave.S
+++ b/arch/sparc64/lib/VISsave.S
@@ -72,7 +72,11 @@ vis1:	ldub		[%g6 + TI_FPSAVED], %g3
 
         stda            %f48, [%g3 + %g1] ASI_BLK_P
 5:      membar          #Sync
-        jmpl            %g7 + %g0, %g0
+        ba,pt           %xcc, 80f
+         nop
+
+        .align          32
+80:     jmpl            %g7 + %g0, %g0
          nop
 
 6:      ldub            [%g3 + TI_FPSAVED], %o5
@@ -87,8 +91,11 @@ vis1:	ldub		[%g6 + TI_FPSAVED], %g3
         stda            %f32, [%g2 + %g1] ASI_BLK_P
         stda            %f48, [%g3 + %g1] ASI_BLK_P
         membar          #Sync
-        jmpl            %g7 + %g0, %g0
+        ba,pt           %xcc, 80f
+         nop
 
+        .align          32
+80:     jmpl            %g7 + %g0, %g0
          nop
 
         .align          32
@@ -126,6 +133,10 @@ VISenterhalf:
         stda            %f0, [%g2 + %g1] ASI_BLK_P
         stda            %f16, [%g3 + %g1] ASI_BLK_P
         membar          #Sync
+        ba,pt           %xcc, 4f
+         nop
+
+        .align          32
 4:      and             %o5, FPRS_DU, %o5
         jmpl            %g7 + %g0, %g0
          wr             %o5, FPRS_FEF, %fprs