[SPARC64]: Niagara copy/clear page.

Happily we have no D-cache aliasing issues on these chips, so the implementation is very straightforward. Add a stub in bootup which will be where the patching calls will be made for niagara/sun4v/hypervisor. Signed-off-by: David S. Miller <davem@davemloft.net>
author: David S. Miller <davem@sunset.davemloft.net> 2006-02-07 19:09:12 -0500
committer: David S. Miller <davem@sunset.davemloft.net> 2006-03-20 04:11:54 -0500
commit: 8591e3027235d6d11b958e43379f2ee7b7114841 (patch)
tree: ce3f036ac64e20f7d75bae04e5362c97bc9228e6 /arch/sparc64/lib/NGpage.S
parent: df7d6aec96ab98cb182dd5138a85bdc363a9bf0d (diff)
1 files changed, 95 insertions, 0 deletions
diff --git a/arch/sparc64/lib/NGpage.S b/arch/sparc64/lib/NGpage.S
new file mode 100644
index 000000000000..0e6152c28b01
--- /dev/null
+++ b/arch/sparc64/lib/NGpage.S
@@ -0,0 +1,95 @@
+/* NGpage.S: Niagara optimize clear and copy page.
+ *
+ * Copyright (C) 2006 (davem@davemloft.net)
+ */
+#include <asm/asi.h>
+#include <asm/page.h>
+        .text
+        .align  32
+        /* This is heavily simplified from the sun4u variants
+         * because Niagara does not have any D-cache aliasing issues
+         * and also we don't need to use the FPU in order to implement
+         * an optimal page copy/clear.
+         */
+NGcopy_user_page:       /* %o0=dest, %o1=src, %o2=vaddr */
+        prefetch        [%o1 + 0x00], #one_read
+        mov             8, %g1
+        mov             16, %g2
+        mov             24, %g3
+        set             PAGE_SIZE, %g7
+1:      ldda            [%o1 + %g0] ASI_BLK_INIT_QUAD_LDD_P, %o2
+        ldda            [%o1 + %g2] ASI_BLK_INIT_QUAD_LDD_P, %o4
+        prefetch        [%o1 + 0x40], #one_read
+        add             %o1, 32, %o1
+        stxa            %o2, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
+        stxa            %o3, [%o0 + %g1] ASI_BLK_INIT_QUAD_LDD_P
+        ldda            [%o1 + %g0] ASI_BLK_INIT_QUAD_LDD_P, %o2
+        stxa            %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
+        stxa            %o5, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P
+        ldda            [%o1 + %g2] ASI_BLK_INIT_QUAD_LDD_P, %o4
+        add             %o1, 32, %o1
+        add             %o0, 32, %o0
+        stxa            %o2, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
+        stxa            %o3, [%o0 + %g1] ASI_BLK_INIT_QUAD_LDD_P
+        stxa            %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
+        stxa            %o5, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P
+        subcc           %g7, 64, %g7
+        bne,pt          %xcc, 1b
+         add            %o0, 32, %o0
+        retl
+         nop
+NGclear_page:           /* %o0=dest */
+NGclear_user_page:      /* %o0=dest, %o1=vaddr */
+        mov             8, %g1
+        mov             16, %g2
+        mov             24, %g3
+        set             PAGE_SIZE, %g7
+1:      stxa            %g0, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
+        stxa            %g0, [%o0 + %g1] ASI_BLK_INIT_QUAD_LDD_P
+        stxa            %g0, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
+        stxa            %g0, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P
+        add             %o0, 32, %o0
+        stxa            %g0, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
+        stxa            %g0, [%o0 + %g1] ASI_BLK_INIT_QUAD_LDD_P
+        stxa            %g0, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
+        stxa            %g0, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P
+        subcc           %g7, 64, %g7
+        bne,pt          %xcc, 1b
+         add            %o0, 32, %o0
+        retl
+         nop
+#define BRANCH_ALWAYS   0x10680000
+#define NOP             0x01000000
+#define NG_DO_PATCH(OLD, NEW)   \
+        sethi   %hi(NEW), %g1; \
+        or      %g1, %lo(NEW), %g1; \
+        sethi   %hi(OLD), %g2; \
+        or      %g2, %lo(OLD), %g2; \
+        sub     %g1, %g2, %g1; \
+        sethi   %hi(BRANCH_ALWAYS), %g3; \
+        srl     %g1, 2, %g1; \
+        or      %g3, %lo(BRANCH_ALWAYS), %g3; \
+        or      %g3, %g1, %g3; \
+        stw     %g3, [%g2]; \
+        sethi   %hi(NOP), %g3; \
+        or      %g3, %lo(NOP), %g3; \
+        stw     %g3, [%g2 + 0x4]; \
+        flush   %g2;
+        .globl  niagara_patch_pageops
+        .type   niagara_patch_pageops,#function
+niagara_patch_pageops:
+        NG_DO_PATCH(copy_user_page, NGcopy_user_page)
+        NG_DO_PATCH(_clear_page, NGclear_page)
+        NG_DO_PATCH(clear_user_page, NGclear_user_page)
+        retl
+         nop
+        .size   niagara_patch_pageops,.-niagara_patch_pageops
author	David S. Miller <davem@sunset.davemloft.net>	2006-02-07 19:09:12 -0500
committer	David S. Miller <davem@sunset.davemloft.net>	2006-03-20 04:11:54 -0500
commit	8591e3027235d6d11b958e43379f2ee7b7114841 (patch)
tree	ce3f036ac64e20f7d75bae04e5362c97bc9228e6 /arch/sparc64/lib/NGpage.S
parent	df7d6aec96ab98cb182dd5138a85bdc363a9bf0d (diff)

diff --git a/arch/sparc64/lib/NGpage.S b/arch/sparc64/lib/NGpage.S new file mode 100644 index 000000000000..0e6152c28b01 --- /dev/null +++ b/arch/sparc64/lib/NGpage.S
@@ -0,0 +1,95 @@
	1	/* NGpage.S: Niagara optimize clear and copy page.
	2	*
	3	* Copyright (C) 2006 (davem@davemloft.net)
	4	*/
	5
	6	#include <asm/asi.h>
	7	#include <asm/page.h>
	8
	9	.text
	10	.align 32
	11
	12	/* This is heavily simplified from the sun4u variants
	13	* because Niagara does not have any D-cache aliasing issues
	14	* and also we don't need to use the FPU in order to implement
	15	* an optimal page copy/clear.
	16	*/
	17
	18	NGcopy_user_page: /* %o0=dest, %o1=src, %o2=vaddr */
	19	prefetch [%o1 + 0x00], #one_read
	20	mov 8, %g1
	21	mov 16, %g2
	22	mov 24, %g3
	23	set PAGE_SIZE, %g7
	24
	25	1: ldda [%o1 + %g0] ASI_BLK_INIT_QUAD_LDD_P, %o2
	26	ldda [%o1 + %g2] ASI_BLK_INIT_QUAD_LDD_P, %o4
	27	prefetch [%o1 + 0x40], #one_read
	28	add %o1, 32, %o1
	29	stxa %o2, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
	30	stxa %o3, [%o0 + %g1] ASI_BLK_INIT_QUAD_LDD_P
	31	ldda [%o1 + %g0] ASI_BLK_INIT_QUAD_LDD_P, %o2
	32	stxa %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
	33	stxa %o5, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P
	34	ldda [%o1 + %g2] ASI_BLK_INIT_QUAD_LDD_P, %o4
	35	add %o1, 32, %o1
	36	add %o0, 32, %o0
	37	stxa %o2, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
	38	stxa %o3, [%o0 + %g1] ASI_BLK_INIT_QUAD_LDD_P
	39	stxa %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
	40	stxa %o5, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P
	41	subcc %g7, 64, %g7
	42	bne,pt %xcc, 1b
	43	add %o0, 32, %o0
	44	retl
	45	nop
	46
	47	NGclear_page: /* %o0=dest */
	48	NGclear_user_page: /* %o0=dest, %o1=vaddr */
	49	mov 8, %g1
	50	mov 16, %g2
	51	mov 24, %g3
	52	set PAGE_SIZE, %g7
	53
	54	1: stxa %g0, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
	55	stxa %g0, [%o0 + %g1] ASI_BLK_INIT_QUAD_LDD_P
	56	stxa %g0, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
	57	stxa %g0, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P
	58	add %o0, 32, %o0
	59	stxa %g0, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
	60	stxa %g0, [%o0 + %g1] ASI_BLK_INIT_QUAD_LDD_P
	61	stxa %g0, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
	62	stxa %g0, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P
	63	subcc %g7, 64, %g7
	64	bne,pt %xcc, 1b
	65	add %o0, 32, %o0
	66	retl
	67	nop
	68
	69	#define BRANCH_ALWAYS 0x10680000
	70	#define NOP 0x01000000
	71	#define NG_DO_PATCH(OLD, NEW) \
	72	sethi %hi(NEW), %g1; \
	73	or %g1, %lo(NEW), %g1; \
	74	sethi %hi(OLD), %g2; \
	75	or %g2, %lo(OLD), %g2; \
	76	sub %g1, %g2, %g1; \
	77	sethi %hi(BRANCH_ALWAYS), %g3; \
	78	srl %g1, 2, %g1; \
	79	or %g3, %lo(BRANCH_ALWAYS), %g3; \
	80	or %g3, %g1, %g3; \
	81	stw %g3, [%g2]; \
	82	sethi %hi(NOP), %g3; \
	83	or %g3, %lo(NOP), %g3; \
	84	stw %g3, [%g2 + 0x4]; \
	85	flush %g2;
	86
	87	.globl niagara_patch_pageops
	88	.type niagara_patch_pageops,#function
	89	niagara_patch_pageops:
	90	NG_DO_PATCH(copy_user_page, NGcopy_user_page)
	91	NG_DO_PATCH(_clear_page, NGclear_page)
	92	NG_DO_PATCH(clear_user_page, NGclear_user_page)
	93	retl
	94	nop
	95	.size niagara_patch_pageops,.-niagara_patch_pageops