[SPARC64]: Avoid membar instructions in delay slots.

In particular, avoid membar instructions in the delay
slot of a jmpl instruction.

UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51

The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.

If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.

We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.

Signed-off-by: David S. Miller <davem@davemloft.net>

3 files changed, 14 insertions, 7 deletions

diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S
index a47f2d0b1a29..ffe717ab7f83 100644
--- a/arch/sparc64/kernel/entry.S
+++ b/arch/sparc64/kernel/entry.S
@@ -271,8 +271,9 @@ cplus_fptrap_insn_1:
         fmuld           %f0, %f2, %f26
         faddd           %f0, %f2, %f28
         fmuld           %f0, %f2, %f30
+        membar          #Sync
         b,pt            %xcc, fpdis_exit
-         membar         #Sync
+         nop
 2:      andcc           %g5, FPRS_DU, %g0
         bne,pt          %icc, 3f
          fzero          %f32
@@ -301,8 +302,9 @@ cplus_fptrap_insn_2:
         fmuld           %f32, %f34, %f58
         faddd           %f32, %f34, %f60
         fmuld           %f32, %f34, %f62
+        membar          #Sync
         ba,pt           %xcc, fpdis_exit
-         membar         #Sync
+         nop
 3:      mov             SECONDARY_CONTEXT, %g3
         add             %g6, TI_FPREGS, %g1
         ldxa            [%g3] ASI_DMMU, %g5
diff --git a/arch/sparc64/kernel/semaphore.c b/arch/sparc64/kernel/semaphore.c
index 63496c43fe17..a809e63f03ef 100644
--- a/arch/sparc64/kernel/semaphore.c
+++ b/arch/sparc64/kernel/semaphore.c
@@ -32,8 +32,9 @@ static __inline__ int __sem_update_count(struct semaphore *sem, int incr)
 "       add     %1, %4, %1\n"
 "       cas     [%3], %0, %1\n"
 "       cmp     %0, %1\n"
+"       membar  #StoreLoad | #StoreStore\n"
 "       bne,pn  %%icc, 1b\n"
-"        membar #StoreLoad | #StoreStore\n"
+"        nop\n"
         : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count)
         : "r" (&sem->count), "r" (incr), "m" (sem->count)
         : "cc");
@@ -71,8 +72,9 @@ void up(struct semaphore *sem)
 "       cmp     %%g1, %%g7\n"
 "       bne,pn  %%icc, 1b\n"
 "        addcc  %%g7, 1, %%g0\n"
+"       membar  #StoreLoad | #StoreStore\n"
 "       ble,pn  %%icc, 3f\n"
-"        membar #StoreLoad | #StoreStore\n"
+"        nop\n"
 "2:\n"
 "       .subsection 2\n"
 "3:     mov     %0, %%g1\n"
@@ -128,8 +130,9 @@ void __sched down(struct semaphore *sem)
 "       cmp     %%g1, %%g7\n"
 "       bne,pn  %%icc, 1b\n"
 "        cmp    %%g7, 1\n"
+"       membar  #StoreLoad | #StoreStore\n"
 "       bl,pn   %%icc, 3f\n"
-"        membar #StoreLoad | #StoreStore\n"
+"        nop\n"
 "2:\n"
 "       .subsection 2\n"
 "3:     mov     %0, %%g1\n"
@@ -233,8 +236,9 @@ int __sched down_interruptible(struct semaphore *sem)
 "       cmp     %%g1, %%g7\n"
 "       bne,pn  %%icc, 1b\n"
 "        cmp    %%g7, 1\n"
+"       membar  #StoreLoad | #StoreStore\n"
 "       bl,pn   %%icc, 3f\n"
-"        membar #StoreLoad | #StoreStore\n"
+"        nop\n"
 "2:\n"
 "       .subsection 2\n"
 "3:     mov     %2, %%g1\n"
diff --git a/arch/sparc64/kernel/trampoline.S b/arch/sparc64/kernel/trampoline.S
index 2c8f9344b4ee..3a145fc39cf2 100644
--- a/arch/sparc64/kernel/trampoline.S
+++ b/arch/sparc64/kernel/trampoline.S
@@ -98,8 +98,9 @@ startup_continue:
 
         sethi           %hi(prom_entry_lock), %g2
 1:      ldstub          [%g2 + %lo(prom_entry_lock)], %g1
+        membar          #StoreLoad | #StoreStore
         brnz,pn         %g1, 1b
-         membar         #StoreLoad | #StoreStore
+         nop
 
         sethi           %hi(p1275buf), %g2
         or              %g2, %lo(p1275buf), %g2