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authorJiri Kosina <jkosina@suse.cz>2008-05-06 10:57:55 -0400
committerJiri Kosina <jkosina@suse.cz>2008-05-06 10:57:55 -0400
commit7022b15e2a9f878fd5184586064c63352c3dd225 (patch)
tree5365c2f5bc82ae1946636ee8d5cd5d3b7e804f1b /arch/sparc64/kernel
parentaaad2b0c757f3e6e02552cb0bdcd91a5ec0d6305 (diff)
parenta15306365a16380f3bafee9e181ba01231d4acd7 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'arch/sparc64/kernel')
-rw-r--r--arch/sparc64/kernel/Makefile7
-rw-r--r--arch/sparc64/kernel/audit.c6
-rw-r--r--arch/sparc64/kernel/cherrs.S579
-rw-r--r--arch/sparc64/kernel/ebus.c1
-rw-r--r--arch/sparc64/kernel/entry.S2576
-rw-r--r--arch/sparc64/kernel/entry.h1
-rw-r--r--arch/sparc64/kernel/etrap.S4
-rw-r--r--arch/sparc64/kernel/fpu_traps.S384
-rw-r--r--arch/sparc64/kernel/getsetcc.S24
-rw-r--r--arch/sparc64/kernel/head.S15
-rw-r--r--arch/sparc64/kernel/helpers.S63
-rw-r--r--arch/sparc64/kernel/hvcalls.S886
-rw-r--r--arch/sparc64/kernel/iommu.c33
-rw-r--r--arch/sparc64/kernel/irq.c3
-rw-r--r--arch/sparc64/kernel/isa.c190
-rw-r--r--arch/sparc64/kernel/ivec.S51
-rw-r--r--arch/sparc64/kernel/kgdb.c186
-rw-r--r--arch/sparc64/kernel/mdesc.c28
-rw-r--r--arch/sparc64/kernel/misctrap.S97
-rw-r--r--arch/sparc64/kernel/of_device.c18
-rw-r--r--arch/sparc64/kernel/pci.c144
-rw-r--r--arch/sparc64/kernel/pci_common.c6
-rw-r--r--arch/sparc64/kernel/pci_fire.c5
-rw-r--r--arch/sparc64/kernel/pci_impl.h13
-rw-r--r--arch/sparc64/kernel/pci_msi.c8
-rw-r--r--arch/sparc64/kernel/pci_psycho.c5
-rw-r--r--arch/sparc64/kernel/pci_sabre.c4
-rw-r--r--arch/sparc64/kernel/pci_schizo.c5
-rw-r--r--arch/sparc64/kernel/pci_sun4v.c13
-rw-r--r--arch/sparc64/kernel/process.c6
-rw-r--r--arch/sparc64/kernel/prom.c14
-rw-r--r--arch/sparc64/kernel/rtrap.S21
-rw-r--r--arch/sparc64/kernel/sbus.c3
-rw-r--r--arch/sparc64/kernel/setup.c3
-rw-r--r--arch/sparc64/kernel/signal.c37
-rw-r--r--arch/sparc64/kernel/signal32.c298
-rw-r--r--arch/sparc64/kernel/smp.c49
-rw-r--r--arch/sparc64/kernel/sparc64_ksyms.c4
-rw-r--r--arch/sparc64/kernel/spiterrs.S245
-rw-r--r--arch/sparc64/kernel/stacktrace.c16
-rw-r--r--arch/sparc64/kernel/sun4v_tlb_miss.S16
-rw-r--r--arch/sparc64/kernel/sys_sparc.c4
-rw-r--r--arch/sparc64/kernel/sys_sparc32.c11
-rw-r--r--arch/sparc64/kernel/syscalls.S279
-rw-r--r--arch/sparc64/kernel/sysfs.c12
-rw-r--r--arch/sparc64/kernel/traps.c19
-rw-r--r--arch/sparc64/kernel/tsb.S2
-rw-r--r--arch/sparc64/kernel/ttable.S2
-rw-r--r--arch/sparc64/kernel/utrap.S29
-rw-r--r--arch/sparc64/kernel/winfixup.S12
50 files changed, 3148 insertions, 3289 deletions
diff --git a/arch/sparc64/kernel/Makefile b/arch/sparc64/kernel/Makefile
index 63c6ae0dd273..ec4f5ebb1ca6 100644
--- a/arch/sparc64/kernel/Makefile
+++ b/arch/sparc64/kernel/Makefile
@@ -15,17 +15,18 @@ obj-y := process.o setup.o cpu.o idprom.o \
15 visemul.o prom.o of_device.o hvapi.o sstate.o mdesc.o 15 visemul.o prom.o of_device.o hvapi.o sstate.o mdesc.o
16 16
17obj-$(CONFIG_STACKTRACE) += stacktrace.o 17obj-$(CONFIG_STACKTRACE) += stacktrace.o
18obj-$(CONFIG_PCI) += ebus.o isa.o pci_common.o \ 18obj-$(CONFIG_PCI) += ebus.o pci_common.o \
19 pci_psycho.o pci_sabre.o pci_schizo.o \ 19 pci_psycho.o pci_sabre.o pci_schizo.o \
20 pci_sun4v.o pci_sun4v_asm.o pci_fire.o 20 pci_sun4v.o pci_sun4v_asm.o pci_fire.o
21obj-$(CONFIG_PCI_MSI) += pci_msi.o 21obj-$(CONFIG_PCI_MSI) += pci_msi.o
22obj-$(CONFIG_SMP) += smp.o trampoline.o hvtramp.o 22obj-$(CONFIG_SMP) += smp.o trampoline.o hvtramp.o
23obj-$(CONFIG_SPARC32_COMPAT) += sys32.o sys_sparc32.o signal32.o 23obj-$(CONFIG_COMPAT) += sys32.o sys_sparc32.o signal32.o
24obj-$(CONFIG_MODULES) += module.o 24obj-$(CONFIG_MODULES) += module.o
25obj-$(CONFIG_US3_FREQ) += us3_cpufreq.o 25obj-$(CONFIG_US3_FREQ) += us3_cpufreq.o
26obj-$(CONFIG_US2E_FREQ) += us2e_cpufreq.o 26obj-$(CONFIG_US2E_FREQ) += us2e_cpufreq.o
27obj-$(CONFIG_KPROBES) += kprobes.o 27obj-$(CONFIG_KPROBES) += kprobes.o
28obj-$(CONFIG_SUN_LDOMS) += ldc.o vio.o viohs.o ds.o 28obj-$(CONFIG_SUN_LDOMS) += ldc.o vio.o viohs.o ds.o
29obj-$(CONFIG_AUDIT) += audit.o 29obj-$(CONFIG_AUDIT) += audit.o
30obj-$(CONFIG_AUDIT)$(CONFIG_SPARC32_COMPAT) += compat_audit.o 30obj-$(CONFIG_AUDIT)$(CONFIG_COMPAT) += compat_audit.o
31obj-y += $(obj-yy) 31obj-y += $(obj-yy)
32obj-$(CONFIG_KGDB) += kgdb.o
diff --git a/arch/sparc64/kernel/audit.c b/arch/sparc64/kernel/audit.c
index 24d7f4b4178a..8fff0ac63d56 100644
--- a/arch/sparc64/kernel/audit.c
+++ b/arch/sparc64/kernel/audit.c
@@ -30,7 +30,7 @@ static unsigned signal_class[] = {
30 30
31int audit_classify_arch(int arch) 31int audit_classify_arch(int arch)
32{ 32{
33#ifdef CONFIG_SPARC32_COMPAT 33#ifdef CONFIG_COMPAT
34 if (arch == AUDIT_ARCH_SPARC) 34 if (arch == AUDIT_ARCH_SPARC)
35 return 1; 35 return 1;
36#endif 36#endif
@@ -39,7 +39,7 @@ int audit_classify_arch(int arch)
39 39
40int audit_classify_syscall(int abi, unsigned syscall) 40int audit_classify_syscall(int abi, unsigned syscall)
41{ 41{
42#ifdef CONFIG_SPARC32_COMPAT 42#ifdef CONFIG_COMPAT
43 extern int sparc32_classify_syscall(unsigned); 43 extern int sparc32_classify_syscall(unsigned);
44 if (abi == AUDIT_ARCH_SPARC) 44 if (abi == AUDIT_ARCH_SPARC)
45 return sparc32_classify_syscall(syscall); 45 return sparc32_classify_syscall(syscall);
@@ -60,7 +60,7 @@ int audit_classify_syscall(int abi, unsigned syscall)
60 60
61static int __init audit_classes_init(void) 61static int __init audit_classes_init(void)
62{ 62{
63#ifdef CONFIG_SPARC32_COMPAT 63#ifdef CONFIG_COMPAT
64 extern __u32 sparc32_dir_class[]; 64 extern __u32 sparc32_dir_class[];
65 extern __u32 sparc32_write_class[]; 65 extern __u32 sparc32_write_class[];
66 extern __u32 sparc32_read_class[]; 66 extern __u32 sparc32_read_class[];
diff --git a/arch/sparc64/kernel/cherrs.S b/arch/sparc64/kernel/cherrs.S
new file mode 100644
index 000000000000..89afebd7eca0
--- /dev/null
+++ b/arch/sparc64/kernel/cherrs.S
@@ -0,0 +1,579 @@
1 /* These get patched into the trap table at boot time
2 * once we know we have a cheetah processor.
3 */
4 .globl cheetah_fecc_trap_vector
5 .type cheetah_fecc_trap_vector,#function
6cheetah_fecc_trap_vector:
7 membar #Sync
8 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
9 andn %g1, DCU_DC | DCU_IC, %g1
10 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
11 membar #Sync
12 sethi %hi(cheetah_fast_ecc), %g2
13 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
14 mov 0, %g1
15 .size cheetah_fecc_trap_vector,.-cheetah_fecc_trap_vector
16
17 .globl cheetah_fecc_trap_vector_tl1
18 .type cheetah_fecc_trap_vector_tl1,#function
19cheetah_fecc_trap_vector_tl1:
20 membar #Sync
21 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
22 andn %g1, DCU_DC | DCU_IC, %g1
23 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
24 membar #Sync
25 sethi %hi(cheetah_fast_ecc), %g2
26 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
27 mov 1, %g1
28 .size cheetah_fecc_trap_vector_tl1,.-cheetah_fecc_trap_vector_tl1
29
30 .globl cheetah_cee_trap_vector
31 .type cheetah_cee_trap_vector,#function
32cheetah_cee_trap_vector:
33 membar #Sync
34 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
35 andn %g1, DCU_IC, %g1
36 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
37 membar #Sync
38 sethi %hi(cheetah_cee), %g2
39 jmpl %g2 + %lo(cheetah_cee), %g0
40 mov 0, %g1
41 .size cheetah_cee_trap_vector,.-cheetah_cee_trap_vector
42
43 .globl cheetah_cee_trap_vector_tl1
44 .type cheetah_cee_trap_vector_tl1,#function
45cheetah_cee_trap_vector_tl1:
46 membar #Sync
47 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
48 andn %g1, DCU_IC, %g1
49 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
50 membar #Sync
51 sethi %hi(cheetah_cee), %g2
52 jmpl %g2 + %lo(cheetah_cee), %g0
53 mov 1, %g1
54 .size cheetah_cee_trap_vector_tl1,.-cheetah_cee_trap_vector_tl1
55
56 .globl cheetah_deferred_trap_vector
57 .type cheetah_deferred_trap_vector,#function
58cheetah_deferred_trap_vector:
59 membar #Sync
60 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
61 andn %g1, DCU_DC | DCU_IC, %g1;
62 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
63 membar #Sync;
64 sethi %hi(cheetah_deferred_trap), %g2
65 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
66 mov 0, %g1
67 .size cheetah_deferred_trap_vector,.-cheetah_deferred_trap_vector
68
69 .globl cheetah_deferred_trap_vector_tl1
70 .type cheetah_deferred_trap_vector_tl1,#function
71cheetah_deferred_trap_vector_tl1:
72 membar #Sync;
73 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
74 andn %g1, DCU_DC | DCU_IC, %g1;
75 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
76 membar #Sync;
77 sethi %hi(cheetah_deferred_trap), %g2
78 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
79 mov 1, %g1
80 .size cheetah_deferred_trap_vector_tl1,.-cheetah_deferred_trap_vector_tl1
81
82 /* Cheetah+ specific traps. These are for the new I/D cache parity
83 * error traps. The first argument to cheetah_plus_parity_handler
84 * is encoded as follows:
85 *
86 * Bit0: 0=dcache,1=icache
87 * Bit1: 0=recoverable,1=unrecoverable
88 */
89 .globl cheetah_plus_dcpe_trap_vector
90 .type cheetah_plus_dcpe_trap_vector,#function
91cheetah_plus_dcpe_trap_vector:
92 membar #Sync
93 sethi %hi(do_cheetah_plus_data_parity), %g7
94 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
95 nop
96 nop
97 nop
98 nop
99 nop
100 .size cheetah_plus_dcpe_trap_vector,.-cheetah_plus_dcpe_trap_vector
101
102 .type do_cheetah_plus_data_parity,#function
103do_cheetah_plus_data_parity:
104 rdpr %pil, %g2
105 wrpr %g0, 15, %pil
106 ba,pt %xcc, etrap_irq
107 rd %pc, %g7
108#ifdef CONFIG_TRACE_IRQFLAGS
109 call trace_hardirqs_off
110 nop
111#endif
112 mov 0x0, %o0
113 call cheetah_plus_parity_error
114 add %sp, PTREGS_OFF, %o1
115 ba,a,pt %xcc, rtrap_irq
116 .size do_cheetah_plus_data_parity,.-do_cheetah_plus_data_parity
117
118 .globl cheetah_plus_dcpe_trap_vector_tl1
119 .type cheetah_plus_dcpe_trap_vector_tl1,#function
120cheetah_plus_dcpe_trap_vector_tl1:
121 membar #Sync
122 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
123 sethi %hi(do_dcpe_tl1), %g3
124 jmpl %g3 + %lo(do_dcpe_tl1), %g0
125 nop
126 nop
127 nop
128 nop
129 .size cheetah_plus_dcpe_trap_vector_tl1,.-cheetah_plus_dcpe_trap_vector_tl1
130
131 .globl cheetah_plus_icpe_trap_vector
132 .type cheetah_plus_icpe_trap_vector,#function
133cheetah_plus_icpe_trap_vector:
134 membar #Sync
135 sethi %hi(do_cheetah_plus_insn_parity), %g7
136 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
137 nop
138 nop
139 nop
140 nop
141 nop
142 .size cheetah_plus_icpe_trap_vector,.-cheetah_plus_icpe_trap_vector
143
144 .type do_cheetah_plus_insn_parity,#function
145do_cheetah_plus_insn_parity:
146 rdpr %pil, %g2
147 wrpr %g0, 15, %pil
148 ba,pt %xcc, etrap_irq
149 rd %pc, %g7
150#ifdef CONFIG_TRACE_IRQFLAGS
151 call trace_hardirqs_off
152 nop
153#endif
154 mov 0x1, %o0
155 call cheetah_plus_parity_error
156 add %sp, PTREGS_OFF, %o1
157 ba,a,pt %xcc, rtrap_irq
158 .size do_cheetah_plus_insn_parity,.-do_cheetah_plus_insn_parity
159
160 .globl cheetah_plus_icpe_trap_vector_tl1
161 .type cheetah_plus_icpe_trap_vector_tl1,#function
162cheetah_plus_icpe_trap_vector_tl1:
163 membar #Sync
164 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
165 sethi %hi(do_icpe_tl1), %g3
166 jmpl %g3 + %lo(do_icpe_tl1), %g0
167 nop
168 nop
169 nop
170 nop
171 .size cheetah_plus_icpe_trap_vector_tl1,.-cheetah_plus_icpe_trap_vector_tl1
172
173 /* If we take one of these traps when tl >= 1, then we
174 * jump to interrupt globals. If some trap level above us
175 * was also using interrupt globals, we cannot recover.
176 * We may use all interrupt global registers except %g6.
177 */
178 .globl do_dcpe_tl1
179 .type do_dcpe_tl1,#function
180do_dcpe_tl1:
181 rdpr %tl, %g1 ! Save original trap level
182 mov 1, %g2 ! Setup TSTATE checking loop
183 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
1841: wrpr %g2, %tl ! Set trap level to check
185 rdpr %tstate, %g4 ! Read TSTATE for this level
186 andcc %g4, %g3, %g0 ! Interrupt globals in use?
187 bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
188 wrpr %g1, %tl ! Restore original trap level
189 add %g2, 1, %g2 ! Next trap level
190 cmp %g2, %g1 ! Hit them all yet?
191 ble,pt %icc, 1b ! Not yet
192 nop
193 wrpr %g1, %tl ! Restore original trap level
194do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
195 sethi %hi(dcache_parity_tl1_occurred), %g2
196 lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1
197 add %g1, 1, %g1
198 stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
199 /* Reset D-cache parity */
200 sethi %hi(1 << 16), %g1 ! D-cache size
201 mov (1 << 5), %g2 ! D-cache line size
202 sub %g1, %g2, %g1 ! Move down 1 cacheline
2031: srl %g1, 14, %g3 ! Compute UTAG
204 membar #Sync
205 stxa %g3, [%g1] ASI_DCACHE_UTAG
206 membar #Sync
207 sub %g2, 8, %g3 ! 64-bit data word within line
2082: membar #Sync
209 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
210 membar #Sync
211 subcc %g3, 8, %g3 ! Next 64-bit data word
212 bge,pt %icc, 2b
213 nop
214 subcc %g1, %g2, %g1 ! Next cacheline
215 bge,pt %icc, 1b
216 nop
217 ba,pt %xcc, dcpe_icpe_tl1_common
218 nop
219
220do_dcpe_tl1_fatal:
221 sethi %hi(1f), %g7
222 ba,pt %xcc, etraptl1
2231: or %g7, %lo(1b), %g7
224 mov 0x2, %o0
225 call cheetah_plus_parity_error
226 add %sp, PTREGS_OFF, %o1
227 ba,pt %xcc, rtrap
228 nop
229 .size do_dcpe_tl1,.-do_dcpe_tl1
230
231 .globl do_icpe_tl1
232 .type do_icpe_tl1,#function
233do_icpe_tl1:
234 rdpr %tl, %g1 ! Save original trap level
235 mov 1, %g2 ! Setup TSTATE checking loop
236 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
2371: wrpr %g2, %tl ! Set trap level to check
238 rdpr %tstate, %g4 ! Read TSTATE for this level
239 andcc %g4, %g3, %g0 ! Interrupt globals in use?
240 bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
241 wrpr %g1, %tl ! Restore original trap level
242 add %g2, 1, %g2 ! Next trap level
243 cmp %g2, %g1 ! Hit them all yet?
244 ble,pt %icc, 1b ! Not yet
245 nop
246 wrpr %g1, %tl ! Restore original trap level
247do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
248 sethi %hi(icache_parity_tl1_occurred), %g2
249 lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1
250 add %g1, 1, %g1
251 stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)]
252 /* Flush I-cache */
253 sethi %hi(1 << 15), %g1 ! I-cache size
254 mov (1 << 5), %g2 ! I-cache line size
255 sub %g1, %g2, %g1
2561: or %g1, (2 << 3), %g3
257 stxa %g0, [%g3] ASI_IC_TAG
258 membar #Sync
259 subcc %g1, %g2, %g1
260 bge,pt %icc, 1b
261 nop
262 ba,pt %xcc, dcpe_icpe_tl1_common
263 nop
264
265do_icpe_tl1_fatal:
266 sethi %hi(1f), %g7
267 ba,pt %xcc, etraptl1
2681: or %g7, %lo(1b), %g7
269 mov 0x3, %o0
270 call cheetah_plus_parity_error
271 add %sp, PTREGS_OFF, %o1
272 ba,pt %xcc, rtrap
273 nop
274 .size do_icpe_tl1,.-do_icpe_tl1
275
276 .type dcpe_icpe_tl1_common,#function
277dcpe_icpe_tl1_common:
278 /* Flush D-cache, re-enable D/I caches in DCU and finally
279 * retry the trapping instruction.
280 */
281 sethi %hi(1 << 16), %g1 ! D-cache size
282 mov (1 << 5), %g2 ! D-cache line size
283 sub %g1, %g2, %g1
2841: stxa %g0, [%g1] ASI_DCACHE_TAG
285 membar #Sync
286 subcc %g1, %g2, %g1
287 bge,pt %icc, 1b
288 nop
289 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
290 or %g1, (DCU_DC | DCU_IC), %g1
291 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
292 membar #Sync
293 retry
294 .size dcpe_icpe_tl1_common,.-dcpe_icpe_tl1_common
295
296 /* Capture I/D/E-cache state into per-cpu error scoreboard.
297 *
298 * %g1: (TL>=0) ? 1 : 0
299 * %g2: scratch
300 * %g3: scratch
301 * %g4: AFSR
302 * %g5: AFAR
303 * %g6: unused, will have current thread ptr after etrap
304 * %g7: scratch
305 */
306 .type __cheetah_log_error,#function
307__cheetah_log_error:
308 /* Put "TL1" software bit into AFSR. */
309 and %g1, 0x1, %g1
310 sllx %g1, 63, %g2
311 or %g4, %g2, %g4
312
313 /* Get log entry pointer for this cpu at this trap level. */
314 BRANCH_IF_JALAPENO(g2,g3,50f)
315 ldxa [%g0] ASI_SAFARI_CONFIG, %g2
316 srlx %g2, 17, %g2
317 ba,pt %xcc, 60f
318 and %g2, 0x3ff, %g2
319
32050: ldxa [%g0] ASI_JBUS_CONFIG, %g2
321 srlx %g2, 17, %g2
322 and %g2, 0x1f, %g2
323
32460: sllx %g2, 9, %g2
325 sethi %hi(cheetah_error_log), %g3
326 ldx [%g3 + %lo(cheetah_error_log)], %g3
327 brz,pn %g3, 80f
328 nop
329
330 add %g3, %g2, %g3
331 sllx %g1, 8, %g1
332 add %g3, %g1, %g1
333
334 /* %g1 holds pointer to the top of the logging scoreboard */
335 ldx [%g1 + 0x0], %g7
336 cmp %g7, -1
337 bne,pn %xcc, 80f
338 nop
339
340 stx %g4, [%g1 + 0x0]
341 stx %g5, [%g1 + 0x8]
342 add %g1, 0x10, %g1
343
344 /* %g1 now points to D-cache logging area */
345 set 0x3ff8, %g2 /* DC_addr mask */
346 and %g5, %g2, %g2 /* DC_addr bits of AFAR */
347 srlx %g5, 12, %g3
348 or %g3, 1, %g3 /* PHYS tag + valid */
349
35010: ldxa [%g2] ASI_DCACHE_TAG, %g7
351 cmp %g3, %g7 /* TAG match? */
352 bne,pt %xcc, 13f
353 nop
354
355 /* Yep, what we want, capture state. */
356 stx %g2, [%g1 + 0x20]
357 stx %g7, [%g1 + 0x28]
358
359 /* A membar Sync is required before and after utag access. */
360 membar #Sync
361 ldxa [%g2] ASI_DCACHE_UTAG, %g7
362 membar #Sync
363 stx %g7, [%g1 + 0x30]
364 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7
365 stx %g7, [%g1 + 0x38]
366 clr %g3
367
36812: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7
369 stx %g7, [%g1]
370 add %g3, (1 << 5), %g3
371 cmp %g3, (4 << 5)
372 bl,pt %xcc, 12b
373 add %g1, 0x8, %g1
374
375 ba,pt %xcc, 20f
376 add %g1, 0x20, %g1
377
37813: sethi %hi(1 << 14), %g7
379 add %g2, %g7, %g2
380 srlx %g2, 14, %g7
381 cmp %g7, 4
382 bl,pt %xcc, 10b
383 nop
384
385 add %g1, 0x40, %g1
386
387 /* %g1 now points to I-cache logging area */
38820: set 0x1fe0, %g2 /* IC_addr mask */
389 and %g5, %g2, %g2 /* IC_addr bits of AFAR */
390 sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */
391 srlx %g5, (13 - 8), %g3 /* Make PTAG */
392 andn %g3, 0xff, %g3 /* Mask off undefined bits */
393
39421: ldxa [%g2] ASI_IC_TAG, %g7
395 andn %g7, 0xff, %g7
396 cmp %g3, %g7
397 bne,pt %xcc, 23f
398 nop
399
400 /* Yep, what we want, capture state. */
401 stx %g2, [%g1 + 0x40]
402 stx %g7, [%g1 + 0x48]
403 add %g2, (1 << 3), %g2
404 ldxa [%g2] ASI_IC_TAG, %g7
405 add %g2, (1 << 3), %g2
406 stx %g7, [%g1 + 0x50]
407 ldxa [%g2] ASI_IC_TAG, %g7
408 add %g2, (1 << 3), %g2
409 stx %g7, [%g1 + 0x60]
410 ldxa [%g2] ASI_IC_TAG, %g7
411 stx %g7, [%g1 + 0x68]
412 sub %g2, (3 << 3), %g2
413 ldxa [%g2] ASI_IC_STAG, %g7
414 stx %g7, [%g1 + 0x58]
415 clr %g3
416 srlx %g2, 2, %g2
417
41822: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7
419 stx %g7, [%g1]
420 add %g3, (1 << 3), %g3
421 cmp %g3, (8 << 3)
422 bl,pt %xcc, 22b
423 add %g1, 0x8, %g1
424
425 ba,pt %xcc, 30f
426 add %g1, 0x30, %g1
427
42823: sethi %hi(1 << 14), %g7
429 add %g2, %g7, %g2
430 srlx %g2, 14, %g7
431 cmp %g7, 4
432 bl,pt %xcc, 21b
433 nop
434
435 add %g1, 0x70, %g1
436
437 /* %g1 now points to E-cache logging area */
43830: andn %g5, (32 - 1), %g2
439 stx %g2, [%g1 + 0x20]
440 ldxa [%g2] ASI_EC_TAG_DATA, %g7
441 stx %g7, [%g1 + 0x28]
442 ldxa [%g2] ASI_EC_R, %g0
443 clr %g3
444
44531: ldxa [%g3] ASI_EC_DATA, %g7
446 stx %g7, [%g1 + %g3]
447 add %g3, 0x8, %g3
448 cmp %g3, 0x20
449
450 bl,pt %xcc, 31b
451 nop
45280:
453 rdpr %tt, %g2
454 cmp %g2, 0x70
455 be c_fast_ecc
456 cmp %g2, 0x63
457 be c_cee
458 nop
459 ba,pt %xcc, c_deferred
460 .size __cheetah_log_error,.-__cheetah_log_error
461
462 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
463 * in the trap table. That code has done a memory barrier
464 * and has disabled both the I-cache and D-cache in the DCU
465 * control register. The I-cache is disabled so that we may
466 * capture the corrupted cache line, and the D-cache is disabled
467 * because corrupt data may have been placed there and we don't
468 * want to reference it.
469 *
470 * %g1 is one if this trap occurred at %tl >= 1.
471 *
472 * Next, we turn off error reporting so that we don't recurse.
473 */
474 .globl cheetah_fast_ecc
475 .type cheetah_fast_ecc,#function
476cheetah_fast_ecc:
477 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
478 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
479 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
480 membar #Sync
481
482 /* Fetch and clear AFSR/AFAR */
483 ldxa [%g0] ASI_AFSR, %g4
484 ldxa [%g0] ASI_AFAR, %g5
485 stxa %g4, [%g0] ASI_AFSR
486 membar #Sync
487
488 ba,pt %xcc, __cheetah_log_error
489 nop
490 .size cheetah_fast_ecc,.-cheetah_fast_ecc
491
492 .type c_fast_ecc,#function
493c_fast_ecc:
494 rdpr %pil, %g2
495 wrpr %g0, 15, %pil
496 ba,pt %xcc, etrap_irq
497 rd %pc, %g7
498#ifdef CONFIG_TRACE_IRQFLAGS
499 call trace_hardirqs_off
500 nop
501#endif
502 mov %l4, %o1
503 mov %l5, %o2
504 call cheetah_fecc_handler
505 add %sp, PTREGS_OFF, %o0
506 ba,a,pt %xcc, rtrap_irq
507 .size c_fast_ecc,.-c_fast_ecc
508
509 /* Our caller has disabled I-cache and performed membar Sync. */
510 .globl cheetah_cee
511 .type cheetah_cee,#function
512cheetah_cee:
513 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
514 andn %g2, ESTATE_ERROR_CEEN, %g2
515 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
516 membar #Sync
517
518 /* Fetch and clear AFSR/AFAR */
519 ldxa [%g0] ASI_AFSR, %g4
520 ldxa [%g0] ASI_AFAR, %g5
521 stxa %g4, [%g0] ASI_AFSR
522 membar #Sync
523
524 ba,pt %xcc, __cheetah_log_error
525 nop
526 .size cheetah_cee,.-cheetah_cee
527
528 .type c_cee,#function
529c_cee:
530 rdpr %pil, %g2
531 wrpr %g0, 15, %pil
532 ba,pt %xcc, etrap_irq
533 rd %pc, %g7
534#ifdef CONFIG_TRACE_IRQFLAGS
535 call trace_hardirqs_off
536 nop
537#endif
538 mov %l4, %o1
539 mov %l5, %o2
540 call cheetah_cee_handler
541 add %sp, PTREGS_OFF, %o0
542 ba,a,pt %xcc, rtrap_irq
543 .size c_cee,.-c_cee
544
545 /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
546 .globl cheetah_deferred_trap
547 .type cheetah_deferred_trap,#function
548cheetah_deferred_trap:
549 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
550 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
551 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
552 membar #Sync
553
554 /* Fetch and clear AFSR/AFAR */
555 ldxa [%g0] ASI_AFSR, %g4
556 ldxa [%g0] ASI_AFAR, %g5
557 stxa %g4, [%g0] ASI_AFSR
558 membar #Sync
559
560 ba,pt %xcc, __cheetah_log_error
561 nop
562 .size cheetah_deferred_trap,.-cheetah_deferred_trap
563
564 .type c_deferred,#function
565c_deferred:
566 rdpr %pil, %g2
567 wrpr %g0, 15, %pil
568 ba,pt %xcc, etrap_irq
569 rd %pc, %g7
570#ifdef CONFIG_TRACE_IRQFLAGS
571 call trace_hardirqs_off
572 nop
573#endif
574 mov %l4, %o1
575 mov %l5, %o2
576 call cheetah_deferred_handler
577 add %sp, PTREGS_OFF, %o0
578 ba,a,pt %xcc, rtrap_irq
579 .size c_deferred,.-c_deferred
diff --git a/arch/sparc64/kernel/ebus.c b/arch/sparc64/kernel/ebus.c
index 04ab81cb4f48..bc2632274840 100644
--- a/arch/sparc64/kernel/ebus.c
+++ b/arch/sparc64/kernel/ebus.c
@@ -396,6 +396,7 @@ static void __init fill_ebus_device(struct device_node *dp, struct linux_ebus_de
396 sd->op = &dev->ofdev; 396 sd->op = &dev->ofdev;
397 sd->iommu = dev->bus->ofdev.dev.parent->archdata.iommu; 397 sd->iommu = dev->bus->ofdev.dev.parent->archdata.iommu;
398 sd->stc = dev->bus->ofdev.dev.parent->archdata.stc; 398 sd->stc = dev->bus->ofdev.dev.parent->archdata.stc;
399 sd->numa_node = dev->bus->ofdev.dev.parent->archdata.numa_node;
399 400
400 dev->ofdev.node = dp; 401 dev->ofdev.node = dp;
401 dev->ofdev.dev.parent = &dev->bus->ofdev.dev; 402 dev->ofdev.dev.parent = &dev->bus->ofdev.dev;
diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S
deleted file mode 100644
index fb43c76bdc26..000000000000
--- a/arch/sparc64/kernel/entry.S
+++ /dev/null
@@ -1,2576 +0,0 @@
1/* $Id: entry.S,v 1.144 2002/02/09 19:49:30 davem Exp $
2 * arch/sparc64/kernel/entry.S: Sparc64 trap low-level entry points.
3 *
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 */
9
10#include <linux/errno.h>
11
12#include <asm/head.h>
13#include <asm/asi.h>
14#include <asm/smp.h>
15#include <asm/ptrace.h>
16#include <asm/page.h>
17#include <asm/signal.h>
18#include <asm/pgtable.h>
19#include <asm/processor.h>
20#include <asm/visasm.h>
21#include <asm/estate.h>
22#include <asm/auxio.h>
23#include <asm/sfafsr.h>
24#include <asm/pil.h>
25#include <asm/unistd.h>
26
27#define curptr g6
28
29 .text
30 .align 32
31
32 /* This is trivial with the new code... */
33 .globl do_fpdis
34do_fpdis:
35 sethi %hi(TSTATE_PEF), %g4
36 rdpr %tstate, %g5
37 andcc %g5, %g4, %g0
38 be,pt %xcc, 1f
39 nop
40 rd %fprs, %g5
41 andcc %g5, FPRS_FEF, %g0
42 be,pt %xcc, 1f
43 nop
44
45 /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */
46 sethi %hi(109f), %g7
47 ba,pt %xcc, etrap
48109: or %g7, %lo(109b), %g7
49 add %g0, %g0, %g0
50 ba,a,pt %xcc, rtrap_clr_l6
51
521: TRAP_LOAD_THREAD_REG(%g6, %g1)
53 ldub [%g6 + TI_FPSAVED], %g5
54 wr %g0, FPRS_FEF, %fprs
55 andcc %g5, FPRS_FEF, %g0
56 be,a,pt %icc, 1f
57 clr %g7
58 ldx [%g6 + TI_GSR], %g7
591: andcc %g5, FPRS_DL, %g0
60 bne,pn %icc, 2f
61 fzero %f0
62 andcc %g5, FPRS_DU, %g0
63 bne,pn %icc, 1f
64 fzero %f2
65 faddd %f0, %f2, %f4
66 fmuld %f0, %f2, %f6
67 faddd %f0, %f2, %f8
68 fmuld %f0, %f2, %f10
69 faddd %f0, %f2, %f12
70 fmuld %f0, %f2, %f14
71 faddd %f0, %f2, %f16
72 fmuld %f0, %f2, %f18
73 faddd %f0, %f2, %f20
74 fmuld %f0, %f2, %f22
75 faddd %f0, %f2, %f24
76 fmuld %f0, %f2, %f26
77 faddd %f0, %f2, %f28
78 fmuld %f0, %f2, %f30
79 faddd %f0, %f2, %f32
80 fmuld %f0, %f2, %f34
81 faddd %f0, %f2, %f36
82 fmuld %f0, %f2, %f38
83 faddd %f0, %f2, %f40
84 fmuld %f0, %f2, %f42
85 faddd %f0, %f2, %f44
86 fmuld %f0, %f2, %f46
87 faddd %f0, %f2, %f48
88 fmuld %f0, %f2, %f50
89 faddd %f0, %f2, %f52
90 fmuld %f0, %f2, %f54
91 faddd %f0, %f2, %f56
92 fmuld %f0, %f2, %f58
93 b,pt %xcc, fpdis_exit2
94 faddd %f0, %f2, %f60
951: mov SECONDARY_CONTEXT, %g3
96 add %g6, TI_FPREGS + 0x80, %g1
97 faddd %f0, %f2, %f4
98 fmuld %f0, %f2, %f6
99
100661: ldxa [%g3] ASI_DMMU, %g5
101 .section .sun4v_1insn_patch, "ax"
102 .word 661b
103 ldxa [%g3] ASI_MMU, %g5
104 .previous
105
106 sethi %hi(sparc64_kern_sec_context), %g2
107 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
108
109661: stxa %g2, [%g3] ASI_DMMU
110 .section .sun4v_1insn_patch, "ax"
111 .word 661b
112 stxa %g2, [%g3] ASI_MMU
113 .previous
114
115 membar #Sync
116 add %g6, TI_FPREGS + 0xc0, %g2
117 faddd %f0, %f2, %f8
118 fmuld %f0, %f2, %f10
119 membar #Sync
120 ldda [%g1] ASI_BLK_S, %f32
121 ldda [%g2] ASI_BLK_S, %f48
122 membar #Sync
123 faddd %f0, %f2, %f12
124 fmuld %f0, %f2, %f14
125 faddd %f0, %f2, %f16
126 fmuld %f0, %f2, %f18
127 faddd %f0, %f2, %f20
128 fmuld %f0, %f2, %f22
129 faddd %f0, %f2, %f24
130 fmuld %f0, %f2, %f26
131 faddd %f0, %f2, %f28
132 fmuld %f0, %f2, %f30
133 b,pt %xcc, fpdis_exit
134 nop
1352: andcc %g5, FPRS_DU, %g0
136 bne,pt %icc, 3f
137 fzero %f32
138 mov SECONDARY_CONTEXT, %g3
139 fzero %f34
140
141661: ldxa [%g3] ASI_DMMU, %g5
142 .section .sun4v_1insn_patch, "ax"
143 .word 661b
144 ldxa [%g3] ASI_MMU, %g5
145 .previous
146
147 add %g6, TI_FPREGS, %g1
148 sethi %hi(sparc64_kern_sec_context), %g2
149 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
150
151661: stxa %g2, [%g3] ASI_DMMU
152 .section .sun4v_1insn_patch, "ax"
153 .word 661b
154 stxa %g2, [%g3] ASI_MMU
155 .previous
156
157 membar #Sync
158 add %g6, TI_FPREGS + 0x40, %g2
159 faddd %f32, %f34, %f36
160 fmuld %f32, %f34, %f38
161 membar #Sync
162 ldda [%g1] ASI_BLK_S, %f0
163 ldda [%g2] ASI_BLK_S, %f16
164 membar #Sync
165 faddd %f32, %f34, %f40
166 fmuld %f32, %f34, %f42
167 faddd %f32, %f34, %f44
168 fmuld %f32, %f34, %f46
169 faddd %f32, %f34, %f48
170 fmuld %f32, %f34, %f50
171 faddd %f32, %f34, %f52
172 fmuld %f32, %f34, %f54
173 faddd %f32, %f34, %f56
174 fmuld %f32, %f34, %f58
175 faddd %f32, %f34, %f60
176 fmuld %f32, %f34, %f62
177 ba,pt %xcc, fpdis_exit
178 nop
1793: mov SECONDARY_CONTEXT, %g3
180 add %g6, TI_FPREGS, %g1
181
182661: ldxa [%g3] ASI_DMMU, %g5
183 .section .sun4v_1insn_patch, "ax"
184 .word 661b
185 ldxa [%g3] ASI_MMU, %g5
186 .previous
187
188 sethi %hi(sparc64_kern_sec_context), %g2
189 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
190
191661: stxa %g2, [%g3] ASI_DMMU
192 .section .sun4v_1insn_patch, "ax"
193 .word 661b
194 stxa %g2, [%g3] ASI_MMU
195 .previous
196
197 membar #Sync
198 mov 0x40, %g2
199 membar #Sync
200 ldda [%g1] ASI_BLK_S, %f0
201 ldda [%g1 + %g2] ASI_BLK_S, %f16
202 add %g1, 0x80, %g1
203 ldda [%g1] ASI_BLK_S, %f32
204 ldda [%g1 + %g2] ASI_BLK_S, %f48
205 membar #Sync
206fpdis_exit:
207
208661: stxa %g5, [%g3] ASI_DMMU
209 .section .sun4v_1insn_patch, "ax"
210 .word 661b
211 stxa %g5, [%g3] ASI_MMU
212 .previous
213
214 membar #Sync
215fpdis_exit2:
216 wr %g7, 0, %gsr
217 ldx [%g6 + TI_XFSR], %fsr
218 rdpr %tstate, %g3
219 or %g3, %g4, %g3 ! anal...
220 wrpr %g3, %tstate
221 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
222 retry
223
224 .align 32
225fp_other_bounce:
226 call do_fpother
227 add %sp, PTREGS_OFF, %o0
228 ba,pt %xcc, rtrap
229 clr %l6
230
231 .globl do_fpother_check_fitos
232 .align 32
233do_fpother_check_fitos:
234 TRAP_LOAD_THREAD_REG(%g6, %g1)
235 sethi %hi(fp_other_bounce - 4), %g7
236 or %g7, %lo(fp_other_bounce - 4), %g7
237
238 /* NOTE: Need to preserve %g7 until we fully commit
239 * to the fitos fixup.
240 */
241 stx %fsr, [%g6 + TI_XFSR]
242 rdpr %tstate, %g3
243 andcc %g3, TSTATE_PRIV, %g0
244 bne,pn %xcc, do_fptrap_after_fsr
245 nop
246 ldx [%g6 + TI_XFSR], %g3
247 srlx %g3, 14, %g1
248 and %g1, 7, %g1
249 cmp %g1, 2 ! Unfinished FP-OP
250 bne,pn %xcc, do_fptrap_after_fsr
251 sethi %hi(1 << 23), %g1 ! Inexact
252 andcc %g3, %g1, %g0
253 bne,pn %xcc, do_fptrap_after_fsr
254 rdpr %tpc, %g1
255 lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail
256#define FITOS_MASK 0xc1f83fe0
257#define FITOS_COMPARE 0x81a01880
258 sethi %hi(FITOS_MASK), %g1
259 or %g1, %lo(FITOS_MASK), %g1
260 and %g3, %g1, %g1
261 sethi %hi(FITOS_COMPARE), %g2
262 or %g2, %lo(FITOS_COMPARE), %g2
263 cmp %g1, %g2
264 bne,pn %xcc, do_fptrap_after_fsr
265 nop
266 std %f62, [%g6 + TI_FPREGS + (62 * 4)]
267 sethi %hi(fitos_table_1), %g1
268 and %g3, 0x1f, %g2
269 or %g1, %lo(fitos_table_1), %g1
270 sllx %g2, 2, %g2
271 jmpl %g1 + %g2, %g0
272 ba,pt %xcc, fitos_emul_continue
273
274fitos_table_1:
275 fitod %f0, %f62
276 fitod %f1, %f62
277 fitod %f2, %f62
278 fitod %f3, %f62
279 fitod %f4, %f62
280 fitod %f5, %f62
281 fitod %f6, %f62
282 fitod %f7, %f62
283 fitod %f8, %f62
284 fitod %f9, %f62
285 fitod %f10, %f62
286 fitod %f11, %f62
287 fitod %f12, %f62
288 fitod %f13, %f62
289 fitod %f14, %f62
290 fitod %f15, %f62
291 fitod %f16, %f62
292 fitod %f17, %f62
293 fitod %f18, %f62
294 fitod %f19, %f62
295 fitod %f20, %f62
296 fitod %f21, %f62
297 fitod %f22, %f62
298 fitod %f23, %f62
299 fitod %f24, %f62
300 fitod %f25, %f62
301 fitod %f26, %f62
302 fitod %f27, %f62
303 fitod %f28, %f62
304 fitod %f29, %f62
305 fitod %f30, %f62
306 fitod %f31, %f62
307
308fitos_emul_continue:
309 sethi %hi(fitos_table_2), %g1
310 srl %g3, 25, %g2
311 or %g1, %lo(fitos_table_2), %g1
312 and %g2, 0x1f, %g2
313 sllx %g2, 2, %g2
314 jmpl %g1 + %g2, %g0
315 ba,pt %xcc, fitos_emul_fini
316
317fitos_table_2:
318 fdtos %f62, %f0
319 fdtos %f62, %f1
320 fdtos %f62, %f2
321 fdtos %f62, %f3
322 fdtos %f62, %f4
323 fdtos %f62, %f5
324 fdtos %f62, %f6
325 fdtos %f62, %f7
326 fdtos %f62, %f8
327 fdtos %f62, %f9
328 fdtos %f62, %f10
329 fdtos %f62, %f11
330 fdtos %f62, %f12
331 fdtos %f62, %f13
332 fdtos %f62, %f14
333 fdtos %f62, %f15
334 fdtos %f62, %f16
335 fdtos %f62, %f17
336 fdtos %f62, %f18
337 fdtos %f62, %f19
338 fdtos %f62, %f20
339 fdtos %f62, %f21
340 fdtos %f62, %f22
341 fdtos %f62, %f23
342 fdtos %f62, %f24
343 fdtos %f62, %f25
344 fdtos %f62, %f26
345 fdtos %f62, %f27
346 fdtos %f62, %f28
347 fdtos %f62, %f29
348 fdtos %f62, %f30
349 fdtos %f62, %f31
350
351fitos_emul_fini:
352 ldd [%g6 + TI_FPREGS + (62 * 4)], %f62
353 done
354
355 .globl do_fptrap
356 .align 32
357do_fptrap:
358 TRAP_LOAD_THREAD_REG(%g6, %g1)
359 stx %fsr, [%g6 + TI_XFSR]
360do_fptrap_after_fsr:
361 ldub [%g6 + TI_FPSAVED], %g3
362 rd %fprs, %g1
363 or %g3, %g1, %g3
364 stb %g3, [%g6 + TI_FPSAVED]
365 rd %gsr, %g3
366 stx %g3, [%g6 + TI_GSR]
367 mov SECONDARY_CONTEXT, %g3
368
369661: ldxa [%g3] ASI_DMMU, %g5
370 .section .sun4v_1insn_patch, "ax"
371 .word 661b
372 ldxa [%g3] ASI_MMU, %g5
373 .previous
374
375 sethi %hi(sparc64_kern_sec_context), %g2
376 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
377
378661: stxa %g2, [%g3] ASI_DMMU
379 .section .sun4v_1insn_patch, "ax"
380 .word 661b
381 stxa %g2, [%g3] ASI_MMU
382 .previous
383
384 membar #Sync
385 add %g6, TI_FPREGS, %g2
386 andcc %g1, FPRS_DL, %g0
387 be,pn %icc, 4f
388 mov 0x40, %g3
389 stda %f0, [%g2] ASI_BLK_S
390 stda %f16, [%g2 + %g3] ASI_BLK_S
391 andcc %g1, FPRS_DU, %g0
392 be,pn %icc, 5f
3934: add %g2, 128, %g2
394 stda %f32, [%g2] ASI_BLK_S
395 stda %f48, [%g2 + %g3] ASI_BLK_S
3965: mov SECONDARY_CONTEXT, %g1
397 membar #Sync
398
399661: stxa %g5, [%g1] ASI_DMMU
400 .section .sun4v_1insn_patch, "ax"
401 .word 661b
402 stxa %g5, [%g1] ASI_MMU
403 .previous
404
405 membar #Sync
406 ba,pt %xcc, etrap
407 wr %g0, 0, %fprs
408
409 /* The registers for cross calls will be:
410 *
411 * DATA 0: [low 32-bits] Address of function to call, jmp to this
412 * [high 32-bits] MMU Context Argument 0, place in %g5
413 * DATA 1: Address Argument 1, place in %g1
414 * DATA 2: Address Argument 2, place in %g7
415 *
416 * With this method we can do most of the cross-call tlb/cache
417 * flushing very quickly.
418 */
419 .text
420 .align 32
421 .globl do_ivec
422do_ivec:
423 mov 0x40, %g3
424 ldxa [%g3 + %g0] ASI_INTR_R, %g3
425 sethi %hi(KERNBASE), %g4
426 cmp %g3, %g4
427 bgeu,pn %xcc, do_ivec_xcall
428 srlx %g3, 32, %g5
429 stxa %g0, [%g0] ASI_INTR_RECEIVE
430 membar #Sync
431
432 sethi %hi(ivector_table_pa), %g2
433 ldx [%g2 + %lo(ivector_table_pa)], %g2
434 sllx %g3, 4, %g3
435 add %g2, %g3, %g3
436
437 TRAP_LOAD_IRQ_WORK_PA(%g6, %g1)
438
439 ldx [%g6], %g5
440 stxa %g5, [%g3] ASI_PHYS_USE_EC
441 stx %g3, [%g6]
442 wr %g0, 1 << PIL_DEVICE_IRQ, %set_softint
443 retry
444do_ivec_xcall:
445 mov 0x50, %g1
446 ldxa [%g1 + %g0] ASI_INTR_R, %g1
447 srl %g3, 0, %g3
448
449 mov 0x60, %g7
450 ldxa [%g7 + %g0] ASI_INTR_R, %g7
451 stxa %g0, [%g0] ASI_INTR_RECEIVE
452 membar #Sync
453 ba,pt %xcc, 1f
454 nop
455
456 .align 32
4571: jmpl %g3, %g0
458 nop
459
460 .globl getcc, setcc
461getcc:
462 ldx [%o0 + PT_V9_TSTATE], %o1
463 srlx %o1, 32, %o1
464 and %o1, 0xf, %o1
465 retl
466 stx %o1, [%o0 + PT_V9_G1]
467setcc:
468 ldx [%o0 + PT_V9_TSTATE], %o1
469 ldx [%o0 + PT_V9_G1], %o2
470 or %g0, %ulo(TSTATE_ICC), %o3
471 sllx %o3, 32, %o3
472 andn %o1, %o3, %o1
473 sllx %o2, 32, %o2
474 and %o2, %o3, %o2
475 or %o1, %o2, %o1
476 retl
477 stx %o1, [%o0 + PT_V9_TSTATE]
478
479 .globl utrap_trap
480utrap_trap: /* %g3=handler,%g4=level */
481 TRAP_LOAD_THREAD_REG(%g6, %g1)
482 ldx [%g6 + TI_UTRAPS], %g1
483 brnz,pt %g1, invoke_utrap
484 nop
485
486 ba,pt %xcc, etrap
487 rd %pc, %g7
488 mov %l4, %o1
489 call bad_trap
490 add %sp, PTREGS_OFF, %o0
491 ba,pt %xcc, rtrap
492 clr %l6
493
494invoke_utrap:
495 sllx %g3, 3, %g3
496 ldx [%g1 + %g3], %g1
497 save %sp, -128, %sp
498 rdpr %tstate, %l6
499 rdpr %cwp, %l7
500 andn %l6, TSTATE_CWP, %l6
501 wrpr %l6, %l7, %tstate
502 rdpr %tpc, %l6
503 rdpr %tnpc, %l7
504 wrpr %g1, 0, %tnpc
505 done
506
507 /* We need to carefully read the error status, ACK
508 * the errors, prevent recursive traps, and pass the
509 * information on to C code for logging.
510 *
511 * We pass the AFAR in as-is, and we encode the status
512 * information as described in asm-sparc64/sfafsr.h
513 */
514 .globl __spitfire_access_error
515__spitfire_access_error:
516 /* Disable ESTATE error reporting so that we do not
517 * take recursive traps and RED state the processor.
518 */
519 stxa %g0, [%g0] ASI_ESTATE_ERROR_EN
520 membar #Sync
521
522 mov UDBE_UE, %g1
523 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
524
525 /* __spitfire_cee_trap branches here with AFSR in %g4 and
526 * UDBE_CE in %g1. It only clears ESTATE_ERR_CE in the
527 * ESTATE Error Enable register.
528 */
529__spitfire_cee_trap_continue:
530 ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR
531
532 rdpr %tt, %g3
533 and %g3, 0x1ff, %g3 ! Paranoia
534 sllx %g3, SFSTAT_TRAP_TYPE_SHIFT, %g3
535 or %g4, %g3, %g4
536 rdpr %tl, %g3
537 cmp %g3, 1
538 mov 1, %g3
539 bleu %xcc, 1f
540 sllx %g3, SFSTAT_TL_GT_ONE_SHIFT, %g3
541
542 or %g4, %g3, %g4
543
544 /* Read in the UDB error register state, clearing the
545 * sticky error bits as-needed. We only clear them if
546 * the UE bit is set. Likewise, __spitfire_cee_trap
547 * below will only do so if the CE bit is set.
548 *
549 * NOTE: UltraSparc-I/II have high and low UDB error
550 * registers, corresponding to the two UDB units
551 * present on those chips. UltraSparc-IIi only
552 * has a single UDB, called "SDB" in the manual.
553 * For IIi the upper UDB register always reads
554 * as zero so for our purposes things will just
555 * work with the checks below.
556 */
5571: ldxa [%g0] ASI_UDBH_ERROR_R, %g3
558 and %g3, 0x3ff, %g7 ! Paranoia
559 sllx %g7, SFSTAT_UDBH_SHIFT, %g7
560 or %g4, %g7, %g4
561 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
562 be,pn %xcc, 1f
563 nop
564 stxa %g3, [%g0] ASI_UDB_ERROR_W
565 membar #Sync
566
5671: mov 0x18, %g3
568 ldxa [%g3] ASI_UDBL_ERROR_R, %g3
569 and %g3, 0x3ff, %g7 ! Paranoia
570 sllx %g7, SFSTAT_UDBL_SHIFT, %g7
571 or %g4, %g7, %g4
572 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
573 be,pn %xcc, 1f
574 nop
575 mov 0x18, %g7
576 stxa %g3, [%g7] ASI_UDB_ERROR_W
577 membar #Sync
578
5791: /* Ok, now that we've latched the error state,
580 * clear the sticky bits in the AFSR.
581 */
582 stxa %g4, [%g0] ASI_AFSR
583 membar #Sync
584
585 rdpr %tl, %g2
586 cmp %g2, 1
587 rdpr %pil, %g2
588 bleu,pt %xcc, 1f
589 wrpr %g0, 15, %pil
590
591 ba,pt %xcc, etraptl1
592 rd %pc, %g7
593
594 ba,pt %xcc, 2f
595 nop
596
5971: ba,pt %xcc, etrap_irq
598 rd %pc, %g7
599
6002:
601#ifdef CONFIG_TRACE_IRQFLAGS
602 call trace_hardirqs_off
603 nop
604#endif
605 mov %l4, %o1
606 mov %l5, %o2
607 call spitfire_access_error
608 add %sp, PTREGS_OFF, %o0
609 ba,pt %xcc, rtrap
610 clr %l6
611
612 /* This is the trap handler entry point for ECC correctable
613 * errors. They are corrected, but we listen for the trap
614 * so that the event can be logged.
615 *
616 * Disrupting errors are either:
617 * 1) single-bit ECC errors during UDB reads to system
618 * memory
619 * 2) data parity errors during write-back events
620 *
621 * As far as I can make out from the manual, the CEE trap
622 * is only for correctable errors during memory read
623 * accesses by the front-end of the processor.
624 *
625 * The code below is only for trap level 1 CEE events,
626 * as it is the only situation where we can safely record
627 * and log. For trap level >1 we just clear the CE bit
628 * in the AFSR and return.
629 *
630 * This is just like __spiftire_access_error above, but it
631 * specifically handles correctable errors. If an
632 * uncorrectable error is indicated in the AFSR we
633 * will branch directly above to __spitfire_access_error
634 * to handle it instead. Uncorrectable therefore takes
635 * priority over correctable, and the error logging
636 * C code will notice this case by inspecting the
637 * trap type.
638 */
639 .globl __spitfire_cee_trap
640__spitfire_cee_trap:
641 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
642 mov 1, %g3
643 sllx %g3, SFAFSR_UE_SHIFT, %g3
644 andcc %g4, %g3, %g0 ! Check for UE
645 bne,pn %xcc, __spitfire_access_error
646 nop
647
648 /* Ok, in this case we only have a correctable error.
649 * Indicate we only wish to capture that state in register
650 * %g1, and we only disable CE error reporting unlike UE
651 * handling which disables all errors.
652 */
653 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g3
654 andn %g3, ESTATE_ERR_CE, %g3
655 stxa %g3, [%g0] ASI_ESTATE_ERROR_EN
656 membar #Sync
657
658 /* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */
659 ba,pt %xcc, __spitfire_cee_trap_continue
660 mov UDBE_CE, %g1
661
662 .globl __spitfire_data_access_exception
663 .globl __spitfire_data_access_exception_tl1
664__spitfire_data_access_exception_tl1:
665 rdpr %pstate, %g4
666 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
667 mov TLB_SFSR, %g3
668 mov DMMU_SFAR, %g5
669 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
670 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
671 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
672 membar #Sync
673 rdpr %tt, %g3
674 cmp %g3, 0x80 ! first win spill/fill trap
675 blu,pn %xcc, 1f
676 cmp %g3, 0xff ! last win spill/fill trap
677 bgu,pn %xcc, 1f
678 nop
679 ba,pt %xcc, winfix_dax
680 rdpr %tpc, %g3
6811: sethi %hi(109f), %g7
682 ba,pt %xcc, etraptl1
683109: or %g7, %lo(109b), %g7
684 mov %l4, %o1
685 mov %l5, %o2
686 call spitfire_data_access_exception_tl1
687 add %sp, PTREGS_OFF, %o0
688 ba,pt %xcc, rtrap
689 clr %l6
690
691__spitfire_data_access_exception:
692 rdpr %pstate, %g4
693 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
694 mov TLB_SFSR, %g3
695 mov DMMU_SFAR, %g5
696 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
697 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
698 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
699 membar #Sync
700 sethi %hi(109f), %g7
701 ba,pt %xcc, etrap
702109: or %g7, %lo(109b), %g7
703 mov %l4, %o1
704 mov %l5, %o2
705 call spitfire_data_access_exception
706 add %sp, PTREGS_OFF, %o0
707 ba,pt %xcc, rtrap
708 clr %l6
709
710 .globl __spitfire_insn_access_exception
711 .globl __spitfire_insn_access_exception_tl1
712__spitfire_insn_access_exception_tl1:
713 rdpr %pstate, %g4
714 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
715 mov TLB_SFSR, %g3
716 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
717 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
718 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
719 membar #Sync
720 sethi %hi(109f), %g7
721 ba,pt %xcc, etraptl1
722109: or %g7, %lo(109b), %g7
723 mov %l4, %o1
724 mov %l5, %o2
725 call spitfire_insn_access_exception_tl1
726 add %sp, PTREGS_OFF, %o0
727 ba,pt %xcc, rtrap
728 clr %l6
729
730__spitfire_insn_access_exception:
731 rdpr %pstate, %g4
732 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
733 mov TLB_SFSR, %g3
734 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
735 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
736 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
737 membar #Sync
738 sethi %hi(109f), %g7
739 ba,pt %xcc, etrap
740109: or %g7, %lo(109b), %g7
741 mov %l4, %o1
742 mov %l5, %o2
743 call spitfire_insn_access_exception
744 add %sp, PTREGS_OFF, %o0
745 ba,pt %xcc, rtrap
746 clr %l6
747
748 /* These get patched into the trap table at boot time
749 * once we know we have a cheetah processor.
750 */
751 .globl cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1
752cheetah_fecc_trap_vector:
753 membar #Sync
754 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
755 andn %g1, DCU_DC | DCU_IC, %g1
756 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
757 membar #Sync
758 sethi %hi(cheetah_fast_ecc), %g2
759 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
760 mov 0, %g1
761cheetah_fecc_trap_vector_tl1:
762 membar #Sync
763 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
764 andn %g1, DCU_DC | DCU_IC, %g1
765 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
766 membar #Sync
767 sethi %hi(cheetah_fast_ecc), %g2
768 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
769 mov 1, %g1
770 .globl cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1
771cheetah_cee_trap_vector:
772 membar #Sync
773 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
774 andn %g1, DCU_IC, %g1
775 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
776 membar #Sync
777 sethi %hi(cheetah_cee), %g2
778 jmpl %g2 + %lo(cheetah_cee), %g0
779 mov 0, %g1
780cheetah_cee_trap_vector_tl1:
781 membar #Sync
782 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
783 andn %g1, DCU_IC, %g1
784 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
785 membar #Sync
786 sethi %hi(cheetah_cee), %g2
787 jmpl %g2 + %lo(cheetah_cee), %g0
788 mov 1, %g1
789 .globl cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1
790cheetah_deferred_trap_vector:
791 membar #Sync
792 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
793 andn %g1, DCU_DC | DCU_IC, %g1;
794 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
795 membar #Sync;
796 sethi %hi(cheetah_deferred_trap), %g2
797 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
798 mov 0, %g1
799cheetah_deferred_trap_vector_tl1:
800 membar #Sync;
801 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
802 andn %g1, DCU_DC | DCU_IC, %g1;
803 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
804 membar #Sync;
805 sethi %hi(cheetah_deferred_trap), %g2
806 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
807 mov 1, %g1
808
809 /* Cheetah+ specific traps. These are for the new I/D cache parity
810 * error traps. The first argument to cheetah_plus_parity_handler
811 * is encoded as follows:
812 *
813 * Bit0: 0=dcache,1=icache
814 * Bit1: 0=recoverable,1=unrecoverable
815 */
816 .globl cheetah_plus_dcpe_trap_vector, cheetah_plus_dcpe_trap_vector_tl1
817cheetah_plus_dcpe_trap_vector:
818 membar #Sync
819 sethi %hi(do_cheetah_plus_data_parity), %g7
820 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
821 nop
822 nop
823 nop
824 nop
825 nop
826
827do_cheetah_plus_data_parity:
828 rdpr %pil, %g2
829 wrpr %g0, 15, %pil
830 ba,pt %xcc, etrap_irq
831 rd %pc, %g7
832#ifdef CONFIG_TRACE_IRQFLAGS
833 call trace_hardirqs_off
834 nop
835#endif
836 mov 0x0, %o0
837 call cheetah_plus_parity_error
838 add %sp, PTREGS_OFF, %o1
839 ba,a,pt %xcc, rtrap_irq
840
841cheetah_plus_dcpe_trap_vector_tl1:
842 membar #Sync
843 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
844 sethi %hi(do_dcpe_tl1), %g3
845 jmpl %g3 + %lo(do_dcpe_tl1), %g0
846 nop
847 nop
848 nop
849 nop
850
851 .globl cheetah_plus_icpe_trap_vector, cheetah_plus_icpe_trap_vector_tl1
852cheetah_plus_icpe_trap_vector:
853 membar #Sync
854 sethi %hi(do_cheetah_plus_insn_parity), %g7
855 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
856 nop
857 nop
858 nop
859 nop
860 nop
861
862do_cheetah_plus_insn_parity:
863 rdpr %pil, %g2
864 wrpr %g0, 15, %pil
865 ba,pt %xcc, etrap_irq
866 rd %pc, %g7
867#ifdef CONFIG_TRACE_IRQFLAGS
868 call trace_hardirqs_off
869 nop
870#endif
871 mov 0x1, %o0
872 call cheetah_plus_parity_error
873 add %sp, PTREGS_OFF, %o1
874 ba,a,pt %xcc, rtrap_irq
875
876cheetah_plus_icpe_trap_vector_tl1:
877 membar #Sync
878 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
879 sethi %hi(do_icpe_tl1), %g3
880 jmpl %g3 + %lo(do_icpe_tl1), %g0
881 nop
882 nop
883 nop
884 nop
885
886 /* If we take one of these traps when tl >= 1, then we
887 * jump to interrupt globals. If some trap level above us
888 * was also using interrupt globals, we cannot recover.
889 * We may use all interrupt global registers except %g6.
890 */
891 .globl do_dcpe_tl1, do_icpe_tl1
892do_dcpe_tl1:
893 rdpr %tl, %g1 ! Save original trap level
894 mov 1, %g2 ! Setup TSTATE checking loop
895 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
8961: wrpr %g2, %tl ! Set trap level to check
897 rdpr %tstate, %g4 ! Read TSTATE for this level
898 andcc %g4, %g3, %g0 ! Interrupt globals in use?
899 bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
900 wrpr %g1, %tl ! Restore original trap level
901 add %g2, 1, %g2 ! Next trap level
902 cmp %g2, %g1 ! Hit them all yet?
903 ble,pt %icc, 1b ! Not yet
904 nop
905 wrpr %g1, %tl ! Restore original trap level
906do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
907 sethi %hi(dcache_parity_tl1_occurred), %g2
908 lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1
909 add %g1, 1, %g1
910 stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
911 /* Reset D-cache parity */
912 sethi %hi(1 << 16), %g1 ! D-cache size
913 mov (1 << 5), %g2 ! D-cache line size
914 sub %g1, %g2, %g1 ! Move down 1 cacheline
9151: srl %g1, 14, %g3 ! Compute UTAG
916 membar #Sync
917 stxa %g3, [%g1] ASI_DCACHE_UTAG
918 membar #Sync
919 sub %g2, 8, %g3 ! 64-bit data word within line
9202: membar #Sync
921 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
922 membar #Sync
923 subcc %g3, 8, %g3 ! Next 64-bit data word
924 bge,pt %icc, 2b
925 nop
926 subcc %g1, %g2, %g1 ! Next cacheline
927 bge,pt %icc, 1b
928 nop
929 ba,pt %xcc, dcpe_icpe_tl1_common
930 nop
931
932do_dcpe_tl1_fatal:
933 sethi %hi(1f), %g7
934 ba,pt %xcc, etraptl1
9351: or %g7, %lo(1b), %g7
936 mov 0x2, %o0
937 call cheetah_plus_parity_error
938 add %sp, PTREGS_OFF, %o1
939 ba,pt %xcc, rtrap
940 clr %l6
941
942do_icpe_tl1:
943 rdpr %tl, %g1 ! Save original trap level
944 mov 1, %g2 ! Setup TSTATE checking loop
945 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
9461: wrpr %g2, %tl ! Set trap level to check
947 rdpr %tstate, %g4 ! Read TSTATE for this level
948 andcc %g4, %g3, %g0 ! Interrupt globals in use?
949 bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
950 wrpr %g1, %tl ! Restore original trap level
951 add %g2, 1, %g2 ! Next trap level
952 cmp %g2, %g1 ! Hit them all yet?
953 ble,pt %icc, 1b ! Not yet
954 nop
955 wrpr %g1, %tl ! Restore original trap level
956do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
957 sethi %hi(icache_parity_tl1_occurred), %g2
958 lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1
959 add %g1, 1, %g1
960 stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)]
961 /* Flush I-cache */
962 sethi %hi(1 << 15), %g1 ! I-cache size
963 mov (1 << 5), %g2 ! I-cache line size
964 sub %g1, %g2, %g1
9651: or %g1, (2 << 3), %g3
966 stxa %g0, [%g3] ASI_IC_TAG
967 membar #Sync
968 subcc %g1, %g2, %g1
969 bge,pt %icc, 1b
970 nop
971 ba,pt %xcc, dcpe_icpe_tl1_common
972 nop
973
974do_icpe_tl1_fatal:
975 sethi %hi(1f), %g7
976 ba,pt %xcc, etraptl1
9771: or %g7, %lo(1b), %g7
978 mov 0x3, %o0
979 call cheetah_plus_parity_error
980 add %sp, PTREGS_OFF, %o1
981 ba,pt %xcc, rtrap
982 clr %l6
983
984dcpe_icpe_tl1_common:
985 /* Flush D-cache, re-enable D/I caches in DCU and finally
986 * retry the trapping instruction.
987 */
988 sethi %hi(1 << 16), %g1 ! D-cache size
989 mov (1 << 5), %g2 ! D-cache line size
990 sub %g1, %g2, %g1
9911: stxa %g0, [%g1] ASI_DCACHE_TAG
992 membar #Sync
993 subcc %g1, %g2, %g1
994 bge,pt %icc, 1b
995 nop
996 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
997 or %g1, (DCU_DC | DCU_IC), %g1
998 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
999 membar #Sync
1000 retry
1001
1002 /* Capture I/D/E-cache state into per-cpu error scoreboard.
1003 *
1004 * %g1: (TL>=0) ? 1 : 0
1005 * %g2: scratch
1006 * %g3: scratch
1007 * %g4: AFSR
1008 * %g5: AFAR
1009 * %g6: unused, will have current thread ptr after etrap
1010 * %g7: scratch
1011 */
1012__cheetah_log_error:
1013 /* Put "TL1" software bit into AFSR. */
1014 and %g1, 0x1, %g1
1015 sllx %g1, 63, %g2
1016 or %g4, %g2, %g4
1017
1018 /* Get log entry pointer for this cpu at this trap level. */
1019 BRANCH_IF_JALAPENO(g2,g3,50f)
1020 ldxa [%g0] ASI_SAFARI_CONFIG, %g2
1021 srlx %g2, 17, %g2
1022 ba,pt %xcc, 60f
1023 and %g2, 0x3ff, %g2
1024
102550: ldxa [%g0] ASI_JBUS_CONFIG, %g2
1026 srlx %g2, 17, %g2
1027 and %g2, 0x1f, %g2
1028
102960: sllx %g2, 9, %g2
1030 sethi %hi(cheetah_error_log), %g3
1031 ldx [%g3 + %lo(cheetah_error_log)], %g3
1032 brz,pn %g3, 80f
1033 nop
1034
1035 add %g3, %g2, %g3
1036 sllx %g1, 8, %g1
1037 add %g3, %g1, %g1
1038
1039 /* %g1 holds pointer to the top of the logging scoreboard */
1040 ldx [%g1 + 0x0], %g7
1041 cmp %g7, -1
1042 bne,pn %xcc, 80f
1043 nop
1044
1045 stx %g4, [%g1 + 0x0]
1046 stx %g5, [%g1 + 0x8]
1047 add %g1, 0x10, %g1
1048
1049 /* %g1 now points to D-cache logging area */
1050 set 0x3ff8, %g2 /* DC_addr mask */
1051 and %g5, %g2, %g2 /* DC_addr bits of AFAR */
1052 srlx %g5, 12, %g3
1053 or %g3, 1, %g3 /* PHYS tag + valid */
1054
105510: ldxa [%g2] ASI_DCACHE_TAG, %g7
1056 cmp %g3, %g7 /* TAG match? */
1057 bne,pt %xcc, 13f
1058 nop
1059
1060 /* Yep, what we want, capture state. */
1061 stx %g2, [%g1 + 0x20]
1062 stx %g7, [%g1 + 0x28]
1063
1064 /* A membar Sync is required before and after utag access. */
1065 membar #Sync
1066 ldxa [%g2] ASI_DCACHE_UTAG, %g7
1067 membar #Sync
1068 stx %g7, [%g1 + 0x30]
1069 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7
1070 stx %g7, [%g1 + 0x38]
1071 clr %g3
1072
107312: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7
1074 stx %g7, [%g1]
1075 add %g3, (1 << 5), %g3
1076 cmp %g3, (4 << 5)
1077 bl,pt %xcc, 12b
1078 add %g1, 0x8, %g1
1079
1080 ba,pt %xcc, 20f
1081 add %g1, 0x20, %g1
1082
108313: sethi %hi(1 << 14), %g7
1084 add %g2, %g7, %g2
1085 srlx %g2, 14, %g7
1086 cmp %g7, 4
1087 bl,pt %xcc, 10b
1088 nop
1089
1090 add %g1, 0x40, %g1
1091
1092 /* %g1 now points to I-cache logging area */
109320: set 0x1fe0, %g2 /* IC_addr mask */
1094 and %g5, %g2, %g2 /* IC_addr bits of AFAR */
1095 sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */
1096 srlx %g5, (13 - 8), %g3 /* Make PTAG */
1097 andn %g3, 0xff, %g3 /* Mask off undefined bits */
1098
109921: ldxa [%g2] ASI_IC_TAG, %g7
1100 andn %g7, 0xff, %g7
1101 cmp %g3, %g7
1102 bne,pt %xcc, 23f
1103 nop
1104
1105 /* Yep, what we want, capture state. */
1106 stx %g2, [%g1 + 0x40]
1107 stx %g7, [%g1 + 0x48]
1108 add %g2, (1 << 3), %g2
1109 ldxa [%g2] ASI_IC_TAG, %g7
1110 add %g2, (1 << 3), %g2
1111 stx %g7, [%g1 + 0x50]
1112 ldxa [%g2] ASI_IC_TAG, %g7
1113 add %g2, (1 << 3), %g2
1114 stx %g7, [%g1 + 0x60]
1115 ldxa [%g2] ASI_IC_TAG, %g7
1116 stx %g7, [%g1 + 0x68]
1117 sub %g2, (3 << 3), %g2
1118 ldxa [%g2] ASI_IC_STAG, %g7
1119 stx %g7, [%g1 + 0x58]
1120 clr %g3
1121 srlx %g2, 2, %g2
1122
112322: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7
1124 stx %g7, [%g1]
1125 add %g3, (1 << 3), %g3
1126 cmp %g3, (8 << 3)
1127 bl,pt %xcc, 22b
1128 add %g1, 0x8, %g1
1129
1130 ba,pt %xcc, 30f
1131 add %g1, 0x30, %g1
1132
113323: sethi %hi(1 << 14), %g7
1134 add %g2, %g7, %g2
1135 srlx %g2, 14, %g7
1136 cmp %g7, 4
1137 bl,pt %xcc, 21b
1138 nop
1139
1140 add %g1, 0x70, %g1
1141
1142 /* %g1 now points to E-cache logging area */
114330: andn %g5, (32 - 1), %g2
1144 stx %g2, [%g1 + 0x20]
1145 ldxa [%g2] ASI_EC_TAG_DATA, %g7
1146 stx %g7, [%g1 + 0x28]
1147 ldxa [%g2] ASI_EC_R, %g0
1148 clr %g3
1149
115031: ldxa [%g3] ASI_EC_DATA, %g7
1151 stx %g7, [%g1 + %g3]
1152 add %g3, 0x8, %g3
1153 cmp %g3, 0x20
1154
1155 bl,pt %xcc, 31b
1156 nop
115780:
1158 rdpr %tt, %g2
1159 cmp %g2, 0x70
1160 be c_fast_ecc
1161 cmp %g2, 0x63
1162 be c_cee
1163 nop
1164 ba,pt %xcc, c_deferred
1165
1166 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
1167 * in the trap table. That code has done a memory barrier
1168 * and has disabled both the I-cache and D-cache in the DCU
1169 * control register. The I-cache is disabled so that we may
1170 * capture the corrupted cache line, and the D-cache is disabled
1171 * because corrupt data may have been placed there and we don't
1172 * want to reference it.
1173 *
1174 * %g1 is one if this trap occurred at %tl >= 1.
1175 *
1176 * Next, we turn off error reporting so that we don't recurse.
1177 */
1178 .globl cheetah_fast_ecc
1179cheetah_fast_ecc:
1180 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1181 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1182 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1183 membar #Sync
1184
1185 /* Fetch and clear AFSR/AFAR */
1186 ldxa [%g0] ASI_AFSR, %g4
1187 ldxa [%g0] ASI_AFAR, %g5
1188 stxa %g4, [%g0] ASI_AFSR
1189 membar #Sync
1190
1191 ba,pt %xcc, __cheetah_log_error
1192 nop
1193
1194c_fast_ecc:
1195 rdpr %pil, %g2
1196 wrpr %g0, 15, %pil
1197 ba,pt %xcc, etrap_irq
1198 rd %pc, %g7
1199#ifdef CONFIG_TRACE_IRQFLAGS
1200 call trace_hardirqs_off
1201 nop
1202#endif
1203 mov %l4, %o1
1204 mov %l5, %o2
1205 call cheetah_fecc_handler
1206 add %sp, PTREGS_OFF, %o0
1207 ba,a,pt %xcc, rtrap_irq
1208
1209 /* Our caller has disabled I-cache and performed membar Sync. */
1210 .globl cheetah_cee
1211cheetah_cee:
1212 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1213 andn %g2, ESTATE_ERROR_CEEN, %g2
1214 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1215 membar #Sync
1216
1217 /* Fetch and clear AFSR/AFAR */
1218 ldxa [%g0] ASI_AFSR, %g4
1219 ldxa [%g0] ASI_AFAR, %g5
1220 stxa %g4, [%g0] ASI_AFSR
1221 membar #Sync
1222
1223 ba,pt %xcc, __cheetah_log_error
1224 nop
1225
1226c_cee:
1227 rdpr %pil, %g2
1228 wrpr %g0, 15, %pil
1229 ba,pt %xcc, etrap_irq
1230 rd %pc, %g7
1231#ifdef CONFIG_TRACE_IRQFLAGS
1232 call trace_hardirqs_off
1233 nop
1234#endif
1235 mov %l4, %o1
1236 mov %l5, %o2
1237 call cheetah_cee_handler
1238 add %sp, PTREGS_OFF, %o0
1239 ba,a,pt %xcc, rtrap_irq
1240
1241 /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
1242 .globl cheetah_deferred_trap
1243cheetah_deferred_trap:
1244 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1245 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1246 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1247 membar #Sync
1248
1249 /* Fetch and clear AFSR/AFAR */
1250 ldxa [%g0] ASI_AFSR, %g4
1251 ldxa [%g0] ASI_AFAR, %g5
1252 stxa %g4, [%g0] ASI_AFSR
1253 membar #Sync
1254
1255 ba,pt %xcc, __cheetah_log_error
1256 nop
1257
1258c_deferred:
1259 rdpr %pil, %g2
1260 wrpr %g0, 15, %pil
1261 ba,pt %xcc, etrap_irq
1262 rd %pc, %g7
1263#ifdef CONFIG_TRACE_IRQFLAGS
1264 call trace_hardirqs_off
1265 nop
1266#endif
1267 mov %l4, %o1
1268 mov %l5, %o2
1269 call cheetah_deferred_handler
1270 add %sp, PTREGS_OFF, %o0
1271 ba,a,pt %xcc, rtrap_irq
1272
1273 .globl __do_privact
1274__do_privact:
1275 mov TLB_SFSR, %g3
1276 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1277 membar #Sync
1278 sethi %hi(109f), %g7
1279 ba,pt %xcc, etrap
1280109: or %g7, %lo(109b), %g7
1281 call do_privact
1282 add %sp, PTREGS_OFF, %o0
1283 ba,pt %xcc, rtrap
1284 clr %l6
1285
1286 .globl do_mna
1287do_mna:
1288 rdpr %tl, %g3
1289 cmp %g3, 1
1290
1291 /* Setup %g4/%g5 now as they are used in the
1292 * winfixup code.
1293 */
1294 mov TLB_SFSR, %g3
1295 mov DMMU_SFAR, %g4
1296 ldxa [%g4] ASI_DMMU, %g4
1297 ldxa [%g3] ASI_DMMU, %g5
1298 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1299 membar #Sync
1300 bgu,pn %icc, winfix_mna
1301 rdpr %tpc, %g3
1302
13031: sethi %hi(109f), %g7
1304 ba,pt %xcc, etrap
1305109: or %g7, %lo(109b), %g7
1306 mov %l4, %o1
1307 mov %l5, %o2
1308 call mem_address_unaligned
1309 add %sp, PTREGS_OFF, %o0
1310 ba,pt %xcc, rtrap
1311 clr %l6
1312
1313 .globl do_lddfmna
1314do_lddfmna:
1315 sethi %hi(109f), %g7
1316 mov TLB_SFSR, %g4
1317 ldxa [%g4] ASI_DMMU, %g5
1318 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1319 membar #Sync
1320 mov DMMU_SFAR, %g4
1321 ldxa [%g4] ASI_DMMU, %g4
1322 ba,pt %xcc, etrap
1323109: or %g7, %lo(109b), %g7
1324 mov %l4, %o1
1325 mov %l5, %o2
1326 call handle_lddfmna
1327 add %sp, PTREGS_OFF, %o0
1328 ba,pt %xcc, rtrap
1329 clr %l6
1330
1331 .globl do_stdfmna
1332do_stdfmna:
1333 sethi %hi(109f), %g7
1334 mov TLB_SFSR, %g4
1335 ldxa [%g4] ASI_DMMU, %g5
1336 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1337 membar #Sync
1338 mov DMMU_SFAR, %g4
1339 ldxa [%g4] ASI_DMMU, %g4
1340 ba,pt %xcc, etrap
1341109: or %g7, %lo(109b), %g7
1342 mov %l4, %o1
1343 mov %l5, %o2
1344 call handle_stdfmna
1345 add %sp, PTREGS_OFF, %o0
1346 ba,pt %xcc, rtrap
1347 clr %l6
1348
1349 .globl breakpoint_trap
1350breakpoint_trap:
1351 call sparc_breakpoint
1352 add %sp, PTREGS_OFF, %o0
1353 ba,pt %xcc, rtrap
1354 nop
1355
1356 /* SunOS's execv() call only specifies the argv argument, the
1357 * environment settings are the same as the calling processes.
1358 */
1359 .globl sunos_execv
1360sys_execve:
1361 sethi %hi(sparc_execve), %g1
1362 ba,pt %xcc, execve_merge
1363 or %g1, %lo(sparc_execve), %g1
1364#ifdef CONFIG_COMPAT
1365 .globl sys_execve
1366sunos_execv:
1367 stx %g0, [%sp + PTREGS_OFF + PT_V9_I2]
1368 .globl sys32_execve
1369sys32_execve:
1370 sethi %hi(sparc32_execve), %g1
1371 or %g1, %lo(sparc32_execve), %g1
1372#endif
1373execve_merge:
1374 flushw
1375 jmpl %g1, %g0
1376 add %sp, PTREGS_OFF, %o0
1377
1378 .globl sys_pipe, sys_sigpause, sys_nis_syscall
1379 .globl sys_rt_sigreturn
1380 .globl sys_ptrace
1381 .globl sys_sigaltstack
1382 .align 32
1383sys_pipe: ba,pt %xcc, sparc_pipe
1384 add %sp, PTREGS_OFF, %o0
1385sys_nis_syscall:ba,pt %xcc, c_sys_nis_syscall
1386 add %sp, PTREGS_OFF, %o0
1387sys_memory_ordering:
1388 ba,pt %xcc, sparc_memory_ordering
1389 add %sp, PTREGS_OFF, %o1
1390sys_sigaltstack:ba,pt %xcc, do_sigaltstack
1391 add %i6, STACK_BIAS, %o2
1392#ifdef CONFIG_COMPAT
1393 .globl sys32_sigstack
1394sys32_sigstack: ba,pt %xcc, do_sys32_sigstack
1395 mov %i6, %o2
1396 .globl sys32_sigaltstack
1397sys32_sigaltstack:
1398 ba,pt %xcc, do_sys32_sigaltstack
1399 mov %i6, %o2
1400#endif
1401 .align 32
1402#ifdef CONFIG_COMPAT
1403 .globl sys32_sigreturn
1404sys32_sigreturn:
1405 add %sp, PTREGS_OFF, %o0
1406 call do_sigreturn32
1407 add %o7, 1f-.-4, %o7
1408 nop
1409#endif
1410sys_rt_sigreturn:
1411 add %sp, PTREGS_OFF, %o0
1412 call do_rt_sigreturn
1413 add %o7, 1f-.-4, %o7
1414 nop
1415#ifdef CONFIG_COMPAT
1416 .globl sys32_rt_sigreturn
1417sys32_rt_sigreturn:
1418 add %sp, PTREGS_OFF, %o0
1419 call do_rt_sigreturn32
1420 add %o7, 1f-.-4, %o7
1421 nop
1422#endif
1423 .align 32
14241: ldx [%curptr + TI_FLAGS], %l5
1425 andcc %l5, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1426 be,pt %icc, rtrap
1427 clr %l6
1428 add %sp, PTREGS_OFF, %o0
1429 call syscall_trace
1430 mov 1, %o1
1431
1432 ba,pt %xcc, rtrap
1433 clr %l6
1434
1435 /* This is how fork() was meant to be done, 8 instruction entry.
1436 *
1437 * I questioned the following code briefly, let me clear things
1438 * up so you must not reason on it like I did.
1439 *
1440 * Know the fork_kpsr etc. we use in the sparc32 port? We don't
1441 * need it here because the only piece of window state we copy to
1442 * the child is the CWP register. Even if the parent sleeps,
1443 * we are safe because we stuck it into pt_regs of the parent
1444 * so it will not change.
1445 *
1446 * XXX This raises the question, whether we can do the same on
1447 * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The
1448 * XXX answer is yes. We stick fork_kpsr in UREG_G0 and
1449 * XXX fork_kwim in UREG_G1 (global registers are considered
1450 * XXX volatile across a system call in the sparc ABI I think
1451 * XXX if it isn't we can use regs->y instead, anyone who depends
1452 * XXX upon the Y register being preserved across a fork deserves
1453 * XXX to lose).
1454 *
1455 * In fact we should take advantage of that fact for other things
1456 * during system calls...
1457 */
1458 .globl sys_fork, sys_vfork, sys_clone, sparc_exit
1459 .globl ret_from_syscall
1460 .align 32
1461sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */
1462 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0
1463 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0
1464 ba,pt %xcc, sys_clone
1465sys_fork: clr %o1
1466 mov SIGCHLD, %o0
1467sys_clone: flushw
1468 movrz %o1, %fp, %o1
1469 mov 0, %o3
1470 ba,pt %xcc, sparc_do_fork
1471 add %sp, PTREGS_OFF, %o2
1472ret_from_syscall:
1473 /* Clear current_thread_info()->new_child, and
1474 * check performance counter stuff too.
1475 */
1476 stb %g0, [%g6 + TI_NEW_CHILD]
1477 ldx [%g6 + TI_FLAGS], %l0
1478 call schedule_tail
1479 mov %g7, %o0
1480 andcc %l0, _TIF_PERFCTR, %g0
1481 be,pt %icc, 1f
1482 nop
1483 ldx [%g6 + TI_PCR], %o7
1484 wr %g0, %o7, %pcr
1485
1486 /* Blackbird errata workaround. See commentary in
1487 * smp.c:smp_percpu_timer_interrupt() for more
1488 * information.
1489 */
1490 ba,pt %xcc, 99f
1491 nop
1492 .align 64
149399: wr %g0, %g0, %pic
1494 rd %pic, %g0
1495
14961: b,pt %xcc, ret_sys_call
1497 ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0
1498sparc_exit: rdpr %pstate, %g2
1499 wrpr %g2, PSTATE_IE, %pstate
1500 rdpr %otherwin, %g1
1501 rdpr %cansave, %g3
1502 add %g3, %g1, %g3
1503 wrpr %g3, 0x0, %cansave
1504 wrpr %g0, 0x0, %otherwin
1505 wrpr %g2, 0x0, %pstate
1506 ba,pt %xcc, sys_exit
1507 stb %g0, [%g6 + TI_WSAVED]
1508
1509linux_sparc_ni_syscall:
1510 sethi %hi(sys_ni_syscall), %l7
1511 b,pt %xcc, 4f
1512 or %l7, %lo(sys_ni_syscall), %l7
1513
1514linux_syscall_trace32:
1515 add %sp, PTREGS_OFF, %o0
1516 call syscall_trace
1517 clr %o1
1518 srl %i0, 0, %o0
1519 srl %i4, 0, %o4
1520 srl %i1, 0, %o1
1521 srl %i2, 0, %o2
1522 b,pt %xcc, 2f
1523 srl %i3, 0, %o3
1524
1525linux_syscall_trace:
1526 add %sp, PTREGS_OFF, %o0
1527 call syscall_trace
1528 clr %o1
1529 mov %i0, %o0
1530 mov %i1, %o1
1531 mov %i2, %o2
1532 mov %i3, %o3
1533 b,pt %xcc, 2f
1534 mov %i4, %o4
1535
1536
1537 /* Linux 32-bit system calls enter here... */
1538 .align 32
1539 .globl linux_sparc_syscall32
1540linux_sparc_syscall32:
1541 /* Direct access to user regs, much faster. */
1542 cmp %g1, NR_SYSCALLS ! IEU1 Group
1543 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1544 srl %i0, 0, %o0 ! IEU0
1545 sll %g1, 2, %l4 ! IEU0 Group
1546 srl %i4, 0, %o4 ! IEU1
1547 lduw [%l7 + %l4], %l7 ! Load
1548 srl %i1, 0, %o1 ! IEU0 Group
1549 ldx [%curptr + TI_FLAGS], %l0 ! Load
1550
1551 srl %i5, 0, %o5 ! IEU1
1552 srl %i2, 0, %o2 ! IEU0 Group
1553 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1554 bne,pn %icc, linux_syscall_trace32 ! CTI
1555 mov %i0, %l5 ! IEU1
1556 call %l7 ! CTI Group brk forced
1557 srl %i3, 0, %o3 ! IEU0
1558 ba,a,pt %xcc, 3f
1559
1560 /* Linux native system calls enter here... */
1561 .align 32
1562 .globl linux_sparc_syscall, ret_sys_call
1563linux_sparc_syscall:
1564 /* Direct access to user regs, much faster. */
1565 cmp %g1, NR_SYSCALLS ! IEU1 Group
1566 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1567 mov %i0, %o0 ! IEU0
1568 sll %g1, 2, %l4 ! IEU0 Group
1569 mov %i1, %o1 ! IEU1
1570 lduw [%l7 + %l4], %l7 ! Load
15714: mov %i2, %o2 ! IEU0 Group
1572 ldx [%curptr + TI_FLAGS], %l0 ! Load
1573
1574 mov %i3, %o3 ! IEU1
1575 mov %i4, %o4 ! IEU0 Group
1576 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1577 bne,pn %icc, linux_syscall_trace ! CTI Group
1578 mov %i0, %l5 ! IEU0
15792: call %l7 ! CTI Group brk forced
1580 mov %i5, %o5 ! IEU0
1581 nop
1582
15833: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1584ret_sys_call:
1585 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
1586 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc
1587 sra %o0, 0, %o0
1588 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
1589 sllx %g2, 32, %g2
1590
1591 /* Check if force_successful_syscall_return()
1592 * was invoked.
1593 */
1594 ldub [%curptr + TI_SYS_NOERROR], %l2
1595 brnz,a,pn %l2, 80f
1596 stb %g0, [%curptr + TI_SYS_NOERROR]
1597
1598 cmp %o0, -ERESTART_RESTARTBLOCK
1599 bgeu,pn %xcc, 1f
1600 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
160180:
1602 /* System call success, clear Carry condition code. */
1603 andn %g3, %g2, %g3
1604 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1605 bne,pn %icc, linux_syscall_trace2
1606 add %l1, 0x4, %l2 ! npc = npc+4
1607 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1608 ba,pt %xcc, rtrap_clr_l6
1609 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1610
16111:
1612 /* System call failure, set Carry condition code.
1613 * Also, get abs(errno) to return to the process.
1614 */
1615 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
1616 sub %g0, %o0, %o0
1617 or %g3, %g2, %g3
1618 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1619 mov 1, %l6
1620 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1621 bne,pn %icc, linux_syscall_trace2
1622 add %l1, 0x4, %l2 ! npc = npc+4
1623 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1624
1625 b,pt %xcc, rtrap
1626 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1627linux_syscall_trace2:
1628 add %sp, PTREGS_OFF, %o0
1629 call syscall_trace
1630 mov 1, %o1
1631 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1632 ba,pt %xcc, rtrap
1633 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1634
1635 .align 32
1636 .globl __flushw_user
1637__flushw_user:
1638 rdpr %otherwin, %g1
1639 brz,pn %g1, 2f
1640 clr %g2
16411: save %sp, -128, %sp
1642 rdpr %otherwin, %g1
1643 brnz,pt %g1, 1b
1644 add %g2, 1, %g2
16451: sub %g2, 1, %g2
1646 brnz,pt %g2, 1b
1647 restore %g0, %g0, %g0
16482: retl
1649 nop
1650
1651 /* Flush %fp and %i7 to the stack for all register
1652 * windows active inside of the cpu. This allows
1653 * show_stack_trace() to avoid using an expensive
1654 * 'flushw'.
1655 */
1656 .globl stack_trace_flush
1657 .type stack_trace_flush,#function
1658stack_trace_flush:
1659 rdpr %pstate, %o0
1660 wrpr %o0, PSTATE_IE, %pstate
1661
1662 rdpr %cwp, %g1
1663 rdpr %canrestore, %g2
1664 sub %g1, 1, %g3
1665
16661: brz,pn %g2, 2f
1667 sub %g2, 1, %g2
1668 wrpr %g3, %cwp
1669 stx %fp, [%sp + STACK_BIAS + RW_V9_I6]
1670 stx %i7, [%sp + STACK_BIAS + RW_V9_I7]
1671 ba,pt %xcc, 1b
1672 sub %g3, 1, %g3
1673
16742: wrpr %g1, %cwp
1675 wrpr %o0, %pstate
1676
1677 retl
1678 nop
1679 .size stack_trace_flush,.-stack_trace_flush
1680
1681#ifdef CONFIG_SMP
1682 .globl hard_smp_processor_id
1683hard_smp_processor_id:
1684#endif
1685 .globl real_hard_smp_processor_id
1686real_hard_smp_processor_id:
1687 __GET_CPUID(%o0)
1688 retl
1689 nop
1690
1691 /* %o0: devhandle
1692 * %o1: devino
1693 *
1694 * returns %o0: sysino
1695 */
1696 .globl sun4v_devino_to_sysino
1697 .type sun4v_devino_to_sysino,#function
1698sun4v_devino_to_sysino:
1699 mov HV_FAST_INTR_DEVINO2SYSINO, %o5
1700 ta HV_FAST_TRAP
1701 retl
1702 mov %o1, %o0
1703 .size sun4v_devino_to_sysino, .-sun4v_devino_to_sysino
1704
1705 /* %o0: sysino
1706 *
1707 * returns %o0: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1708 */
1709 .globl sun4v_intr_getenabled
1710 .type sun4v_intr_getenabled,#function
1711sun4v_intr_getenabled:
1712 mov HV_FAST_INTR_GETENABLED, %o5
1713 ta HV_FAST_TRAP
1714 retl
1715 mov %o1, %o0
1716 .size sun4v_intr_getenabled, .-sun4v_intr_getenabled
1717
1718 /* %o0: sysino
1719 * %o1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1720 */
1721 .globl sun4v_intr_setenabled
1722 .type sun4v_intr_setenabled,#function
1723sun4v_intr_setenabled:
1724 mov HV_FAST_INTR_SETENABLED, %o5
1725 ta HV_FAST_TRAP
1726 retl
1727 nop
1728 .size sun4v_intr_setenabled, .-sun4v_intr_setenabled
1729
1730 /* %o0: sysino
1731 *
1732 * returns %o0: intr_state (HV_INTR_STATE_*)
1733 */
1734 .globl sun4v_intr_getstate
1735 .type sun4v_intr_getstate,#function
1736sun4v_intr_getstate:
1737 mov HV_FAST_INTR_GETSTATE, %o5
1738 ta HV_FAST_TRAP
1739 retl
1740 mov %o1, %o0
1741 .size sun4v_intr_getstate, .-sun4v_intr_getstate
1742
1743 /* %o0: sysino
1744 * %o1: intr_state (HV_INTR_STATE_*)
1745 */
1746 .globl sun4v_intr_setstate
1747 .type sun4v_intr_setstate,#function
1748sun4v_intr_setstate:
1749 mov HV_FAST_INTR_SETSTATE, %o5
1750 ta HV_FAST_TRAP
1751 retl
1752 nop
1753 .size sun4v_intr_setstate, .-sun4v_intr_setstate
1754
1755 /* %o0: sysino
1756 *
1757 * returns %o0: cpuid
1758 */
1759 .globl sun4v_intr_gettarget
1760 .type sun4v_intr_gettarget,#function
1761sun4v_intr_gettarget:
1762 mov HV_FAST_INTR_GETTARGET, %o5
1763 ta HV_FAST_TRAP
1764 retl
1765 mov %o1, %o0
1766 .size sun4v_intr_gettarget, .-sun4v_intr_gettarget
1767
1768 /* %o0: sysino
1769 * %o1: cpuid
1770 */
1771 .globl sun4v_intr_settarget
1772 .type sun4v_intr_settarget,#function
1773sun4v_intr_settarget:
1774 mov HV_FAST_INTR_SETTARGET, %o5
1775 ta HV_FAST_TRAP
1776 retl
1777 nop
1778 .size sun4v_intr_settarget, .-sun4v_intr_settarget
1779
1780 /* %o0: cpuid
1781 * %o1: pc
1782 * %o2: rtba
1783 * %o3: arg0
1784 *
1785 * returns %o0: status
1786 */
1787 .globl sun4v_cpu_start
1788 .type sun4v_cpu_start,#function
1789sun4v_cpu_start:
1790 mov HV_FAST_CPU_START, %o5
1791 ta HV_FAST_TRAP
1792 retl
1793 nop
1794 .size sun4v_cpu_start, .-sun4v_cpu_start
1795
1796 /* %o0: cpuid
1797 *
1798 * returns %o0: status
1799 */
1800 .globl sun4v_cpu_stop
1801 .type sun4v_cpu_stop,#function
1802sun4v_cpu_stop:
1803 mov HV_FAST_CPU_STOP, %o5
1804 ta HV_FAST_TRAP
1805 retl
1806 nop
1807 .size sun4v_cpu_stop, .-sun4v_cpu_stop
1808
1809 /* returns %o0: status */
1810 .globl sun4v_cpu_yield
1811 .type sun4v_cpu_yield, #function
1812sun4v_cpu_yield:
1813 mov HV_FAST_CPU_YIELD, %o5
1814 ta HV_FAST_TRAP
1815 retl
1816 nop
1817 .size sun4v_cpu_yield, .-sun4v_cpu_yield
1818
1819 /* %o0: type
1820 * %o1: queue paddr
1821 * %o2: num queue entries
1822 *
1823 * returns %o0: status
1824 */
1825 .globl sun4v_cpu_qconf
1826 .type sun4v_cpu_qconf,#function
1827sun4v_cpu_qconf:
1828 mov HV_FAST_CPU_QCONF, %o5
1829 ta HV_FAST_TRAP
1830 retl
1831 nop
1832 .size sun4v_cpu_qconf, .-sun4v_cpu_qconf
1833
1834 /* %o0: num cpus in cpu list
1835 * %o1: cpu list paddr
1836 * %o2: mondo block paddr
1837 *
1838 * returns %o0: status
1839 */
1840 .globl sun4v_cpu_mondo_send
1841 .type sun4v_cpu_mondo_send,#function
1842sun4v_cpu_mondo_send:
1843 mov HV_FAST_CPU_MONDO_SEND, %o5
1844 ta HV_FAST_TRAP
1845 retl
1846 nop
1847 .size sun4v_cpu_mondo_send, .-sun4v_cpu_mondo_send
1848
1849 /* %o0: CPU ID
1850 *
1851 * returns %o0: -status if status non-zero, else
1852 * %o0: cpu state as HV_CPU_STATE_*
1853 */
1854 .globl sun4v_cpu_state
1855 .type sun4v_cpu_state,#function
1856sun4v_cpu_state:
1857 mov HV_FAST_CPU_STATE, %o5
1858 ta HV_FAST_TRAP
1859 brnz,pn %o0, 1f
1860 sub %g0, %o0, %o0
1861 mov %o1, %o0
18621: retl
1863 nop
1864 .size sun4v_cpu_state, .-sun4v_cpu_state
1865
1866 /* %o0: virtual address
1867 * %o1: must be zero
1868 * %o2: TTE
1869 * %o3: HV_MMU_* flags
1870 *
1871 * returns %o0: status
1872 */
1873 .globl sun4v_mmu_map_perm_addr
1874 .type sun4v_mmu_map_perm_addr,#function
1875sun4v_mmu_map_perm_addr:
1876 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
1877 ta HV_FAST_TRAP
1878 retl
1879 nop
1880 .size sun4v_mmu_map_perm_addr, .-sun4v_mmu_map_perm_addr
1881
1882 /* %o0: number of TSB descriptions
1883 * %o1: TSB descriptions real address
1884 *
1885 * returns %o0: status
1886 */
1887 .globl sun4v_mmu_tsb_ctx0
1888 .type sun4v_mmu_tsb_ctx0,#function
1889sun4v_mmu_tsb_ctx0:
1890 mov HV_FAST_MMU_TSB_CTX0, %o5
1891 ta HV_FAST_TRAP
1892 retl
1893 nop
1894 .size sun4v_mmu_tsb_ctx0, .-sun4v_mmu_tsb_ctx0
1895
1896 /* %o0: API group number
1897 * %o1: pointer to unsigned long major number storage
1898 * %o2: pointer to unsigned long minor number storage
1899 *
1900 * returns %o0: status
1901 */
1902 .globl sun4v_get_version
1903 .type sun4v_get_version,#function
1904sun4v_get_version:
1905 mov HV_CORE_GET_VER, %o5
1906 mov %o1, %o3
1907 mov %o2, %o4
1908 ta HV_CORE_TRAP
1909 stx %o1, [%o3]
1910 retl
1911 stx %o2, [%o4]
1912 .size sun4v_get_version, .-sun4v_get_version
1913
1914 /* %o0: API group number
1915 * %o1: desired major number
1916 * %o2: desired minor number
1917 * %o3: pointer to unsigned long actual minor number storage
1918 *
1919 * returns %o0: status
1920 */
1921 .globl sun4v_set_version
1922 .type sun4v_set_version,#function
1923sun4v_set_version:
1924 mov HV_CORE_SET_VER, %o5
1925 mov %o3, %o4
1926 ta HV_CORE_TRAP
1927 retl
1928 stx %o1, [%o4]
1929 .size sun4v_set_version, .-sun4v_set_version
1930
1931 /* %o0: pointer to unsigned long time
1932 *
1933 * returns %o0: status
1934 */
1935 .globl sun4v_tod_get
1936 .type sun4v_tod_get,#function
1937sun4v_tod_get:
1938 mov %o0, %o4
1939 mov HV_FAST_TOD_GET, %o5
1940 ta HV_FAST_TRAP
1941 stx %o1, [%o4]
1942 retl
1943 nop
1944 .size sun4v_tod_get, .-sun4v_tod_get
1945
1946 /* %o0: time
1947 *
1948 * returns %o0: status
1949 */
1950 .globl sun4v_tod_set
1951 .type sun4v_tod_set,#function
1952sun4v_tod_set:
1953 mov HV_FAST_TOD_SET, %o5
1954 ta HV_FAST_TRAP
1955 retl
1956 nop
1957 .size sun4v_tod_set, .-sun4v_tod_set
1958
1959 /* %o0: pointer to unsigned long status
1960 *
1961 * returns %o0: signed character
1962 */
1963 .globl sun4v_con_getchar
1964 .type sun4v_con_getchar,#function
1965sun4v_con_getchar:
1966 mov %o0, %o4
1967 mov HV_FAST_CONS_GETCHAR, %o5
1968 clr %o0
1969 clr %o1
1970 ta HV_FAST_TRAP
1971 stx %o0, [%o4]
1972 retl
1973 sra %o1, 0, %o0
1974 .size sun4v_con_getchar, .-sun4v_con_getchar
1975
1976 /* %o0: signed long character
1977 *
1978 * returns %o0: status
1979 */
1980 .globl sun4v_con_putchar
1981 .type sun4v_con_putchar,#function
1982sun4v_con_putchar:
1983 mov HV_FAST_CONS_PUTCHAR, %o5
1984 ta HV_FAST_TRAP
1985 retl
1986 sra %o0, 0, %o0
1987 .size sun4v_con_putchar, .-sun4v_con_putchar
1988
1989 /* %o0: buffer real address
1990 * %o1: buffer size
1991 * %o2: pointer to unsigned long bytes_read
1992 *
1993 * returns %o0: status
1994 */
1995 .globl sun4v_con_read
1996 .type sun4v_con_read,#function
1997sun4v_con_read:
1998 mov %o2, %o4
1999 mov HV_FAST_CONS_READ, %o5
2000 ta HV_FAST_TRAP
2001 brnz %o0, 1f
2002 cmp %o1, -1 /* break */
2003 be,a,pn %icc, 1f
2004 mov %o1, %o0
2005 cmp %o1, -2 /* hup */
2006 be,a,pn %icc, 1f
2007 mov %o1, %o0
2008 stx %o1, [%o4]
20091: retl
2010 nop
2011 .size sun4v_con_read, .-sun4v_con_read
2012
2013 /* %o0: buffer real address
2014 * %o1: buffer size
2015 * %o2: pointer to unsigned long bytes_written
2016 *
2017 * returns %o0: status
2018 */
2019 .globl sun4v_con_write
2020 .type sun4v_con_write,#function
2021sun4v_con_write:
2022 mov %o2, %o4
2023 mov HV_FAST_CONS_WRITE, %o5
2024 ta HV_FAST_TRAP
2025 stx %o1, [%o4]
2026 retl
2027 nop
2028 .size sun4v_con_write, .-sun4v_con_write
2029
2030 /* %o0: soft state
2031 * %o1: address of description string
2032 *
2033 * returns %o0: status
2034 */
2035 .globl sun4v_mach_set_soft_state
2036 .type sun4v_mach_set_soft_state,#function
2037sun4v_mach_set_soft_state:
2038 mov HV_FAST_MACH_SET_SOFT_STATE, %o5
2039 ta HV_FAST_TRAP
2040 retl
2041 nop
2042 .size sun4v_mach_set_soft_state, .-sun4v_mach_set_soft_state
2043
2044 /* %o0: exit code
2045 *
2046 * Does not return.
2047 */
2048 .globl sun4v_mach_exit
2049 .type sun4v_mach_exit,#function
2050sun4v_mach_exit:
2051 mov HV_FAST_MACH_EXIT, %o5
2052 ta HV_FAST_TRAP
2053 retl
2054 nop
2055 .size sun4v_mach_exit, .-sun4v_mach_exit
2056
2057 /* %o0: buffer real address
2058 * %o1: buffer length
2059 * %o2: pointer to unsigned long real_buf_len
2060 *
2061 * returns %o0: status
2062 */
2063 .globl sun4v_mach_desc
2064 .type sun4v_mach_desc,#function
2065sun4v_mach_desc:
2066 mov %o2, %o4
2067 mov HV_FAST_MACH_DESC, %o5
2068 ta HV_FAST_TRAP
2069 stx %o1, [%o4]
2070 retl
2071 nop
2072 .size sun4v_mach_desc, .-sun4v_mach_desc
2073
2074 /* %o0: new timeout in milliseconds
2075 * %o1: pointer to unsigned long orig_timeout
2076 *
2077 * returns %o0: status
2078 */
2079 .globl sun4v_mach_set_watchdog
2080 .type sun4v_mach_set_watchdog,#function
2081sun4v_mach_set_watchdog:
2082 mov %o1, %o4
2083 mov HV_FAST_MACH_SET_WATCHDOG, %o5
2084 ta HV_FAST_TRAP
2085 stx %o1, [%o4]
2086 retl
2087 nop
2088 .size sun4v_mach_set_watchdog, .-sun4v_mach_set_watchdog
2089
2090 /* No inputs and does not return. */
2091 .globl sun4v_mach_sir
2092 .type sun4v_mach_sir,#function
2093sun4v_mach_sir:
2094 mov %o1, %o4
2095 mov HV_FAST_MACH_SIR, %o5
2096 ta HV_FAST_TRAP
2097 stx %o1, [%o4]
2098 retl
2099 nop
2100 .size sun4v_mach_sir, .-sun4v_mach_sir
2101
2102 /* %o0: channel
2103 * %o1: ra
2104 * %o2: num_entries
2105 *
2106 * returns %o0: status
2107 */
2108 .globl sun4v_ldc_tx_qconf
2109 .type sun4v_ldc_tx_qconf,#function
2110sun4v_ldc_tx_qconf:
2111 mov HV_FAST_LDC_TX_QCONF, %o5
2112 ta HV_FAST_TRAP
2113 retl
2114 nop
2115 .size sun4v_ldc_tx_qconf, .-sun4v_ldc_tx_qconf
2116
2117 /* %o0: channel
2118 * %o1: pointer to unsigned long ra
2119 * %o2: pointer to unsigned long num_entries
2120 *
2121 * returns %o0: status
2122 */
2123 .globl sun4v_ldc_tx_qinfo
2124 .type sun4v_ldc_tx_qinfo,#function
2125sun4v_ldc_tx_qinfo:
2126 mov %o1, %g1
2127 mov %o2, %g2
2128 mov HV_FAST_LDC_TX_QINFO, %o5
2129 ta HV_FAST_TRAP
2130 stx %o1, [%g1]
2131 stx %o2, [%g2]
2132 retl
2133 nop
2134 .size sun4v_ldc_tx_qinfo, .-sun4v_ldc_tx_qinfo
2135
2136 /* %o0: channel
2137 * %o1: pointer to unsigned long head_off
2138 * %o2: pointer to unsigned long tail_off
2139 * %o2: pointer to unsigned long chan_state
2140 *
2141 * returns %o0: status
2142 */
2143 .globl sun4v_ldc_tx_get_state
2144 .type sun4v_ldc_tx_get_state,#function
2145sun4v_ldc_tx_get_state:
2146 mov %o1, %g1
2147 mov %o2, %g2
2148 mov %o3, %g3
2149 mov HV_FAST_LDC_TX_GET_STATE, %o5
2150 ta HV_FAST_TRAP
2151 stx %o1, [%g1]
2152 stx %o2, [%g2]
2153 stx %o3, [%g3]
2154 retl
2155 nop
2156 .size sun4v_ldc_tx_get_state, .-sun4v_ldc_tx_get_state
2157
2158 /* %o0: channel
2159 * %o1: tail_off
2160 *
2161 * returns %o0: status
2162 */
2163 .globl sun4v_ldc_tx_set_qtail
2164 .type sun4v_ldc_tx_set_qtail,#function
2165sun4v_ldc_tx_set_qtail:
2166 mov HV_FAST_LDC_TX_SET_QTAIL, %o5
2167 ta HV_FAST_TRAP
2168 retl
2169 nop
2170 .size sun4v_ldc_tx_set_qtail, .-sun4v_ldc_tx_set_qtail
2171
2172 /* %o0: channel
2173 * %o1: ra
2174 * %o2: num_entries
2175 *
2176 * returns %o0: status
2177 */
2178 .globl sun4v_ldc_rx_qconf
2179 .type sun4v_ldc_rx_qconf,#function
2180sun4v_ldc_rx_qconf:
2181 mov HV_FAST_LDC_RX_QCONF, %o5
2182 ta HV_FAST_TRAP
2183 retl
2184 nop
2185 .size sun4v_ldc_rx_qconf, .-sun4v_ldc_rx_qconf
2186
2187 /* %o0: channel
2188 * %o1: pointer to unsigned long ra
2189 * %o2: pointer to unsigned long num_entries
2190 *
2191 * returns %o0: status
2192 */
2193 .globl sun4v_ldc_rx_qinfo
2194 .type sun4v_ldc_rx_qinfo,#function
2195sun4v_ldc_rx_qinfo:
2196 mov %o1, %g1
2197 mov %o2, %g2
2198 mov HV_FAST_LDC_RX_QINFO, %o5
2199 ta HV_FAST_TRAP
2200 stx %o1, [%g1]
2201 stx %o2, [%g2]
2202 retl
2203 nop
2204 .size sun4v_ldc_rx_qinfo, .-sun4v_ldc_rx_qinfo
2205
2206 /* %o0: channel
2207 * %o1: pointer to unsigned long head_off
2208 * %o2: pointer to unsigned long tail_off
2209 * %o2: pointer to unsigned long chan_state
2210 *
2211 * returns %o0: status
2212 */
2213 .globl sun4v_ldc_rx_get_state
2214 .type sun4v_ldc_rx_get_state,#function
2215sun4v_ldc_rx_get_state:
2216 mov %o1, %g1
2217 mov %o2, %g2
2218 mov %o3, %g3
2219 mov HV_FAST_LDC_RX_GET_STATE, %o5
2220 ta HV_FAST_TRAP
2221 stx %o1, [%g1]
2222 stx %o2, [%g2]
2223 stx %o3, [%g3]
2224 retl
2225 nop
2226 .size sun4v_ldc_rx_get_state, .-sun4v_ldc_rx_get_state
2227
2228 /* %o0: channel
2229 * %o1: head_off
2230 *
2231 * returns %o0: status
2232 */
2233 .globl sun4v_ldc_rx_set_qhead
2234 .type sun4v_ldc_rx_set_qhead,#function
2235sun4v_ldc_rx_set_qhead:
2236 mov HV_FAST_LDC_RX_SET_QHEAD, %o5
2237 ta HV_FAST_TRAP
2238 retl
2239 nop
2240 .size sun4v_ldc_rx_set_qhead, .-sun4v_ldc_rx_set_qhead
2241
2242 /* %o0: channel
2243 * %o1: ra
2244 * %o2: num_entries
2245 *
2246 * returns %o0: status
2247 */
2248 .globl sun4v_ldc_set_map_table
2249 .type sun4v_ldc_set_map_table,#function
2250sun4v_ldc_set_map_table:
2251 mov HV_FAST_LDC_SET_MAP_TABLE, %o5
2252 ta HV_FAST_TRAP
2253 retl
2254 nop
2255 .size sun4v_ldc_set_map_table, .-sun4v_ldc_set_map_table
2256
2257 /* %o0: channel
2258 * %o1: pointer to unsigned long ra
2259 * %o2: pointer to unsigned long num_entries
2260 *
2261 * returns %o0: status
2262 */
2263 .globl sun4v_ldc_get_map_table
2264 .type sun4v_ldc_get_map_table,#function
2265sun4v_ldc_get_map_table:
2266 mov %o1, %g1
2267 mov %o2, %g2
2268 mov HV_FAST_LDC_GET_MAP_TABLE, %o5
2269 ta HV_FAST_TRAP
2270 stx %o1, [%g1]
2271 stx %o2, [%g2]
2272 retl
2273 nop
2274 .size sun4v_ldc_get_map_table, .-sun4v_ldc_get_map_table
2275
2276 /* %o0: channel
2277 * %o1: dir_code
2278 * %o2: tgt_raddr
2279 * %o3: lcl_raddr
2280 * %o4: len
2281 * %o5: pointer to unsigned long actual_len
2282 *
2283 * returns %o0: status
2284 */
2285 .globl sun4v_ldc_copy
2286 .type sun4v_ldc_copy,#function
2287sun4v_ldc_copy:
2288 mov %o5, %g1
2289 mov HV_FAST_LDC_COPY, %o5
2290 ta HV_FAST_TRAP
2291 stx %o1, [%g1]
2292 retl
2293 nop
2294 .size sun4v_ldc_copy, .-sun4v_ldc_copy
2295
2296 /* %o0: channel
2297 * %o1: cookie
2298 * %o2: pointer to unsigned long ra
2299 * %o3: pointer to unsigned long perm
2300 *
2301 * returns %o0: status
2302 */
2303 .globl sun4v_ldc_mapin
2304 .type sun4v_ldc_mapin,#function
2305sun4v_ldc_mapin:
2306 mov %o2, %g1
2307 mov %o3, %g2
2308 mov HV_FAST_LDC_MAPIN, %o5
2309 ta HV_FAST_TRAP
2310 stx %o1, [%g1]
2311 stx %o2, [%g2]
2312 retl
2313 nop
2314 .size sun4v_ldc_mapin, .-sun4v_ldc_mapin
2315
2316 /* %o0: ra
2317 *
2318 * returns %o0: status
2319 */
2320 .globl sun4v_ldc_unmap
2321 .type sun4v_ldc_unmap,#function
2322sun4v_ldc_unmap:
2323 mov HV_FAST_LDC_UNMAP, %o5
2324 ta HV_FAST_TRAP
2325 retl
2326 nop
2327 .size sun4v_ldc_unmap, .-sun4v_ldc_unmap
2328
2329 /* %o0: channel
2330 * %o1: cookie
2331 * %o2: mte_cookie
2332 *
2333 * returns %o0: status
2334 */
2335 .globl sun4v_ldc_revoke
2336 .type sun4v_ldc_revoke,#function
2337sun4v_ldc_revoke:
2338 mov HV_FAST_LDC_REVOKE, %o5
2339 ta HV_FAST_TRAP
2340 retl
2341 nop
2342 .size sun4v_ldc_revoke, .-sun4v_ldc_revoke
2343
2344 /* %o0: device handle
2345 * %o1: device INO
2346 * %o2: pointer to unsigned long cookie
2347 *
2348 * returns %o0: status
2349 */
2350 .globl sun4v_vintr_get_cookie
2351 .type sun4v_vintr_get_cookie,#function
2352sun4v_vintr_get_cookie:
2353 mov %o2, %g1
2354 mov HV_FAST_VINTR_GET_COOKIE, %o5
2355 ta HV_FAST_TRAP
2356 stx %o1, [%g1]
2357 retl
2358 nop
2359 .size sun4v_vintr_get_cookie, .-sun4v_vintr_get_cookie
2360
2361 /* %o0: device handle
2362 * %o1: device INO
2363 * %o2: cookie
2364 *
2365 * returns %o0: status
2366 */
2367 .globl sun4v_vintr_set_cookie
2368 .type sun4v_vintr_set_cookie,#function
2369sun4v_vintr_set_cookie:
2370 mov HV_FAST_VINTR_SET_COOKIE, %o5
2371 ta HV_FAST_TRAP
2372 retl
2373 nop
2374 .size sun4v_vintr_set_cookie, .-sun4v_vintr_set_cookie
2375
2376 /* %o0: device handle
2377 * %o1: device INO
2378 * %o2: pointer to unsigned long valid_state
2379 *
2380 * returns %o0: status
2381 */
2382 .globl sun4v_vintr_get_valid
2383 .type sun4v_vintr_get_valid,#function
2384sun4v_vintr_get_valid:
2385 mov %o2, %g1
2386 mov HV_FAST_VINTR_GET_VALID, %o5
2387 ta HV_FAST_TRAP
2388 stx %o1, [%g1]
2389 retl
2390 nop
2391 .size sun4v_vintr_get_valid, .-sun4v_vintr_get_valid
2392
2393 /* %o0: device handle
2394 * %o1: device INO
2395 * %o2: valid_state
2396 *
2397 * returns %o0: status
2398 */
2399 .globl sun4v_vintr_set_valid
2400 .type sun4v_vintr_set_valid,#function
2401sun4v_vintr_set_valid:
2402 mov HV_FAST_VINTR_SET_VALID, %o5
2403 ta HV_FAST_TRAP
2404 retl
2405 nop
2406 .size sun4v_vintr_set_valid, .-sun4v_vintr_set_valid
2407
2408 /* %o0: device handle
2409 * %o1: device INO
2410 * %o2: pointer to unsigned long state
2411 *
2412 * returns %o0: status
2413 */
2414 .globl sun4v_vintr_get_state
2415 .type sun4v_vintr_get_state,#function
2416sun4v_vintr_get_state:
2417 mov %o2, %g1
2418 mov HV_FAST_VINTR_GET_STATE, %o5
2419 ta HV_FAST_TRAP
2420 stx %o1, [%g1]
2421 retl
2422 nop
2423 .size sun4v_vintr_get_state, .-sun4v_vintr_get_state
2424
2425 /* %o0: device handle
2426 * %o1: device INO
2427 * %o2: state
2428 *
2429 * returns %o0: status
2430 */
2431 .globl sun4v_vintr_set_state
2432 .type sun4v_vintr_set_state,#function
2433sun4v_vintr_set_state:
2434 mov HV_FAST_VINTR_SET_STATE, %o5
2435 ta HV_FAST_TRAP
2436 retl
2437 nop
2438 .size sun4v_vintr_set_state, .-sun4v_vintr_set_state
2439
2440 /* %o0: device handle
2441 * %o1: device INO
2442 * %o2: pointer to unsigned long cpuid
2443 *
2444 * returns %o0: status
2445 */
2446 .globl sun4v_vintr_get_target
2447 .type sun4v_vintr_get_target,#function
2448sun4v_vintr_get_target:
2449 mov %o2, %g1
2450 mov HV_FAST_VINTR_GET_TARGET, %o5
2451 ta HV_FAST_TRAP
2452 stx %o1, [%g1]
2453 retl
2454 nop
2455 .size sun4v_vintr_get_target, .-sun4v_vintr_get_target
2456
2457 /* %o0: device handle
2458 * %o1: device INO
2459 * %o2: cpuid
2460 *
2461 * returns %o0: status
2462 */
2463 .globl sun4v_vintr_set_target
2464 .type sun4v_vintr_set_target,#function
2465sun4v_vintr_set_target:
2466 mov HV_FAST_VINTR_SET_TARGET, %o5
2467 ta HV_FAST_TRAP
2468 retl
2469 nop
2470 .size sun4v_vintr_set_target, .-sun4v_vintr_set_target
2471
2472 /* %o0: NCS sub-function
2473 * %o1: sub-function arg real-address
2474 * %o2: sub-function arg size
2475 *
2476 * returns %o0: status
2477 */
2478 .globl sun4v_ncs_request
2479 .type sun4v_ncs_request,#function
2480sun4v_ncs_request:
2481 mov HV_FAST_NCS_REQUEST, %o5
2482 ta HV_FAST_TRAP
2483 retl
2484 nop
2485 .size sun4v_ncs_request, .-sun4v_ncs_request
2486
2487 .globl sun4v_svc_send
2488 .type sun4v_svc_send,#function
2489sun4v_svc_send:
2490 save %sp, -192, %sp
2491 mov %i0, %o0
2492 mov %i1, %o1
2493 mov %i2, %o2
2494 mov HV_FAST_SVC_SEND, %o5
2495 ta HV_FAST_TRAP
2496 stx %o1, [%i3]
2497 ret
2498 restore
2499 .size sun4v_svc_send, .-sun4v_svc_send
2500
2501 .globl sun4v_svc_recv
2502 .type sun4v_svc_recv,#function
2503sun4v_svc_recv:
2504 save %sp, -192, %sp
2505 mov %i0, %o0
2506 mov %i1, %o1
2507 mov %i2, %o2
2508 mov HV_FAST_SVC_RECV, %o5
2509 ta HV_FAST_TRAP
2510 stx %o1, [%i3]
2511 ret
2512 restore
2513 .size sun4v_svc_recv, .-sun4v_svc_recv
2514
2515 .globl sun4v_svc_getstatus
2516 .type sun4v_svc_getstatus,#function
2517sun4v_svc_getstatus:
2518 mov HV_FAST_SVC_GETSTATUS, %o5
2519 mov %o1, %o4
2520 ta HV_FAST_TRAP
2521 stx %o1, [%o4]
2522 retl
2523 nop
2524 .size sun4v_svc_getstatus, .-sun4v_svc_getstatus
2525
2526 .globl sun4v_svc_setstatus
2527 .type sun4v_svc_setstatus,#function
2528sun4v_svc_setstatus:
2529 mov HV_FAST_SVC_SETSTATUS, %o5
2530 ta HV_FAST_TRAP
2531 retl
2532 nop
2533 .size sun4v_svc_setstatus, .-sun4v_svc_setstatus
2534
2535 .globl sun4v_svc_clrstatus
2536 .type sun4v_svc_clrstatus,#function
2537sun4v_svc_clrstatus:
2538 mov HV_FAST_SVC_CLRSTATUS, %o5
2539 ta HV_FAST_TRAP
2540 retl
2541 nop
2542 .size sun4v_svc_clrstatus, .-sun4v_svc_clrstatus
2543
2544 .globl sun4v_mmustat_conf
2545 .type sun4v_mmustat_conf,#function
2546sun4v_mmustat_conf:
2547 mov %o1, %o4
2548 mov HV_FAST_MMUSTAT_CONF, %o5
2549 ta HV_FAST_TRAP
2550 stx %o1, [%o4]
2551 retl
2552 nop
2553 .size sun4v_mmustat_conf, .-sun4v_mmustat_conf
2554
2555 .globl sun4v_mmustat_info
2556 .type sun4v_mmustat_info,#function
2557sun4v_mmustat_info:
2558 mov %o0, %o4
2559 mov HV_FAST_MMUSTAT_INFO, %o5
2560 ta HV_FAST_TRAP
2561 stx %o1, [%o4]
2562 retl
2563 nop
2564 .size sun4v_mmustat_info, .-sun4v_mmustat_info
2565
2566 .globl sun4v_mmu_demap_all
2567 .type sun4v_mmu_demap_all,#function
2568sun4v_mmu_demap_all:
2569 clr %o0
2570 clr %o1
2571 mov HV_MMU_ALL, %o2
2572 mov HV_FAST_MMU_DEMAP_ALL, %o5
2573 ta HV_FAST_TRAP
2574 retl
2575 nop
2576 .size sun4v_mmu_demap_all, .-sun4v_mmu_demap_all
diff --git a/arch/sparc64/kernel/entry.h b/arch/sparc64/kernel/entry.h
index 4a91e9c6d31b..32fbab620852 100644
--- a/arch/sparc64/kernel/entry.h
+++ b/arch/sparc64/kernel/entry.h
@@ -20,7 +20,6 @@ extern void timer_interrupt(int irq, struct pt_regs *regs);
20 20
21extern void do_notify_resume(struct pt_regs *regs, 21extern void do_notify_resume(struct pt_regs *regs,
22 unsigned long orig_i0, 22 unsigned long orig_i0,
23 int restart_syscall,
24 unsigned long thread_info_flags); 23 unsigned long thread_info_flags);
25 24
26extern asmlinkage void syscall_trace(struct pt_regs *regs, 25extern asmlinkage void syscall_trace(struct pt_regs *regs,
diff --git a/arch/sparc64/kernel/etrap.S b/arch/sparc64/kernel/etrap.S
index 4b2bf9eb447a..b49d3b60bc0c 100644
--- a/arch/sparc64/kernel/etrap.S
+++ b/arch/sparc64/kernel/etrap.S
@@ -53,7 +53,11 @@ etrap_irq:
53 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC] 53 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
54 rd %y, %g3 54 rd %y, %g3
55 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC] 55 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
56 rdpr %tt, %g1
56 st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y] 57 st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
58 sethi %hi(PT_REGS_MAGIC), %g3
59 or %g3, %g1, %g1
60 st %g1, [%g2 + STACKFRAME_SZ + PT_V9_MAGIC]
57 61
58 rdpr %cansave, %g1 62 rdpr %cansave, %g1
59 brnz,pt %g1, etrap_save 63 brnz,pt %g1, etrap_save
diff --git a/arch/sparc64/kernel/fpu_traps.S b/arch/sparc64/kernel/fpu_traps.S
new file mode 100644
index 000000000000..a6864826a4bd
--- /dev/null
+++ b/arch/sparc64/kernel/fpu_traps.S
@@ -0,0 +1,384 @@
1 /* This is trivial with the new code... */
2 .globl do_fpdis
3 .type do_fpdis,#function
4do_fpdis:
5 sethi %hi(TSTATE_PEF), %g4
6 rdpr %tstate, %g5
7 andcc %g5, %g4, %g0
8 be,pt %xcc, 1f
9 nop
10 rd %fprs, %g5
11 andcc %g5, FPRS_FEF, %g0
12 be,pt %xcc, 1f
13 nop
14
15 /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */
16 sethi %hi(109f), %g7
17 ba,pt %xcc, etrap
18109: or %g7, %lo(109b), %g7
19 add %g0, %g0, %g0
20 ba,a,pt %xcc, rtrap
21
221: TRAP_LOAD_THREAD_REG(%g6, %g1)
23 ldub [%g6 + TI_FPSAVED], %g5
24 wr %g0, FPRS_FEF, %fprs
25 andcc %g5, FPRS_FEF, %g0
26 be,a,pt %icc, 1f
27 clr %g7
28 ldx [%g6 + TI_GSR], %g7
291: andcc %g5, FPRS_DL, %g0
30 bne,pn %icc, 2f
31 fzero %f0
32 andcc %g5, FPRS_DU, %g0
33 bne,pn %icc, 1f
34 fzero %f2
35 faddd %f0, %f2, %f4
36 fmuld %f0, %f2, %f6
37 faddd %f0, %f2, %f8
38 fmuld %f0, %f2, %f10
39 faddd %f0, %f2, %f12
40 fmuld %f0, %f2, %f14
41 faddd %f0, %f2, %f16
42 fmuld %f0, %f2, %f18
43 faddd %f0, %f2, %f20
44 fmuld %f0, %f2, %f22
45 faddd %f0, %f2, %f24
46 fmuld %f0, %f2, %f26
47 faddd %f0, %f2, %f28
48 fmuld %f0, %f2, %f30
49 faddd %f0, %f2, %f32
50 fmuld %f0, %f2, %f34
51 faddd %f0, %f2, %f36
52 fmuld %f0, %f2, %f38
53 faddd %f0, %f2, %f40
54 fmuld %f0, %f2, %f42
55 faddd %f0, %f2, %f44
56 fmuld %f0, %f2, %f46
57 faddd %f0, %f2, %f48
58 fmuld %f0, %f2, %f50
59 faddd %f0, %f2, %f52
60 fmuld %f0, %f2, %f54
61 faddd %f0, %f2, %f56
62 fmuld %f0, %f2, %f58
63 b,pt %xcc, fpdis_exit2
64 faddd %f0, %f2, %f60
651: mov SECONDARY_CONTEXT, %g3
66 add %g6, TI_FPREGS + 0x80, %g1
67 faddd %f0, %f2, %f4
68 fmuld %f0, %f2, %f6
69
70661: ldxa [%g3] ASI_DMMU, %g5
71 .section .sun4v_1insn_patch, "ax"
72 .word 661b
73 ldxa [%g3] ASI_MMU, %g5
74 .previous
75
76 sethi %hi(sparc64_kern_sec_context), %g2
77 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
78
79661: stxa %g2, [%g3] ASI_DMMU
80 .section .sun4v_1insn_patch, "ax"
81 .word 661b
82 stxa %g2, [%g3] ASI_MMU
83 .previous
84
85 membar #Sync
86 add %g6, TI_FPREGS + 0xc0, %g2
87 faddd %f0, %f2, %f8
88 fmuld %f0, %f2, %f10
89 membar #Sync
90 ldda [%g1] ASI_BLK_S, %f32
91 ldda [%g2] ASI_BLK_S, %f48
92 membar #Sync
93 faddd %f0, %f2, %f12
94 fmuld %f0, %f2, %f14
95 faddd %f0, %f2, %f16
96 fmuld %f0, %f2, %f18
97 faddd %f0, %f2, %f20
98 fmuld %f0, %f2, %f22
99 faddd %f0, %f2, %f24
100 fmuld %f0, %f2, %f26
101 faddd %f0, %f2, %f28
102 fmuld %f0, %f2, %f30
103 b,pt %xcc, fpdis_exit
104 nop
1052: andcc %g5, FPRS_DU, %g0
106 bne,pt %icc, 3f
107 fzero %f32
108 mov SECONDARY_CONTEXT, %g3
109 fzero %f34
110
111661: ldxa [%g3] ASI_DMMU, %g5
112 .section .sun4v_1insn_patch, "ax"
113 .word 661b
114 ldxa [%g3] ASI_MMU, %g5
115 .previous
116
117 add %g6, TI_FPREGS, %g1
118 sethi %hi(sparc64_kern_sec_context), %g2
119 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
120
121661: stxa %g2, [%g3] ASI_DMMU
122 .section .sun4v_1insn_patch, "ax"
123 .word 661b
124 stxa %g2, [%g3] ASI_MMU
125 .previous
126
127 membar #Sync
128 add %g6, TI_FPREGS + 0x40, %g2
129 faddd %f32, %f34, %f36
130 fmuld %f32, %f34, %f38
131 membar #Sync
132 ldda [%g1] ASI_BLK_S, %f0
133 ldda [%g2] ASI_BLK_S, %f16
134 membar #Sync
135 faddd %f32, %f34, %f40
136 fmuld %f32, %f34, %f42
137 faddd %f32, %f34, %f44
138 fmuld %f32, %f34, %f46
139 faddd %f32, %f34, %f48
140 fmuld %f32, %f34, %f50
141 faddd %f32, %f34, %f52
142 fmuld %f32, %f34, %f54
143 faddd %f32, %f34, %f56
144 fmuld %f32, %f34, %f58
145 faddd %f32, %f34, %f60
146 fmuld %f32, %f34, %f62
147 ba,pt %xcc, fpdis_exit
148 nop
1493: mov SECONDARY_CONTEXT, %g3
150 add %g6, TI_FPREGS, %g1
151
152661: ldxa [%g3] ASI_DMMU, %g5
153 .section .sun4v_1insn_patch, "ax"
154 .word 661b
155 ldxa [%g3] ASI_MMU, %g5
156 .previous
157
158 sethi %hi(sparc64_kern_sec_context), %g2
159 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
160
161661: stxa %g2, [%g3] ASI_DMMU
162 .section .sun4v_1insn_patch, "ax"
163 .word 661b
164 stxa %g2, [%g3] ASI_MMU
165 .previous
166
167 membar #Sync
168 mov 0x40, %g2
169 membar #Sync
170 ldda [%g1] ASI_BLK_S, %f0
171 ldda [%g1 + %g2] ASI_BLK_S, %f16
172 add %g1, 0x80, %g1
173 ldda [%g1] ASI_BLK_S, %f32
174 ldda [%g1 + %g2] ASI_BLK_S, %f48
175 membar #Sync
176fpdis_exit:
177
178661: stxa %g5, [%g3] ASI_DMMU
179 .section .sun4v_1insn_patch, "ax"
180 .word 661b
181 stxa %g5, [%g3] ASI_MMU
182 .previous
183
184 membar #Sync
185fpdis_exit2:
186 wr %g7, 0, %gsr
187 ldx [%g6 + TI_XFSR], %fsr
188 rdpr %tstate, %g3
189 or %g3, %g4, %g3 ! anal...
190 wrpr %g3, %tstate
191 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
192 retry
193 .size do_fpdis,.-do_fpdis
194
195 .align 32
196 .type fp_other_bounce,#function
197fp_other_bounce:
198 call do_fpother
199 add %sp, PTREGS_OFF, %o0
200 ba,pt %xcc, rtrap
201 nop
202 .size fp_other_bounce,.-fp_other_bounce
203
204 .align 32
205 .globl do_fpother_check_fitos
206 .type do_fpother_check_fitos,#function
207do_fpother_check_fitos:
208 TRAP_LOAD_THREAD_REG(%g6, %g1)
209 sethi %hi(fp_other_bounce - 4), %g7
210 or %g7, %lo(fp_other_bounce - 4), %g7
211
212 /* NOTE: Need to preserve %g7 until we fully commit
213 * to the fitos fixup.
214 */
215 stx %fsr, [%g6 + TI_XFSR]
216 rdpr %tstate, %g3
217 andcc %g3, TSTATE_PRIV, %g0
218 bne,pn %xcc, do_fptrap_after_fsr
219 nop
220 ldx [%g6 + TI_XFSR], %g3
221 srlx %g3, 14, %g1
222 and %g1, 7, %g1
223 cmp %g1, 2 ! Unfinished FP-OP
224 bne,pn %xcc, do_fptrap_after_fsr
225 sethi %hi(1 << 23), %g1 ! Inexact
226 andcc %g3, %g1, %g0
227 bne,pn %xcc, do_fptrap_after_fsr
228 rdpr %tpc, %g1
229 lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail
230#define FITOS_MASK 0xc1f83fe0
231#define FITOS_COMPARE 0x81a01880
232 sethi %hi(FITOS_MASK), %g1
233 or %g1, %lo(FITOS_MASK), %g1
234 and %g3, %g1, %g1
235 sethi %hi(FITOS_COMPARE), %g2
236 or %g2, %lo(FITOS_COMPARE), %g2
237 cmp %g1, %g2
238 bne,pn %xcc, do_fptrap_after_fsr
239 nop
240 std %f62, [%g6 + TI_FPREGS + (62 * 4)]
241 sethi %hi(fitos_table_1), %g1
242 and %g3, 0x1f, %g2
243 or %g1, %lo(fitos_table_1), %g1
244 sllx %g2, 2, %g2
245 jmpl %g1 + %g2, %g0
246 ba,pt %xcc, fitos_emul_continue
247
248fitos_table_1:
249 fitod %f0, %f62
250 fitod %f1, %f62
251 fitod %f2, %f62
252 fitod %f3, %f62
253 fitod %f4, %f62
254 fitod %f5, %f62
255 fitod %f6, %f62
256 fitod %f7, %f62
257 fitod %f8, %f62
258 fitod %f9, %f62
259 fitod %f10, %f62
260 fitod %f11, %f62
261 fitod %f12, %f62
262 fitod %f13, %f62
263 fitod %f14, %f62
264 fitod %f15, %f62
265 fitod %f16, %f62
266 fitod %f17, %f62
267 fitod %f18, %f62
268 fitod %f19, %f62
269 fitod %f20, %f62
270 fitod %f21, %f62
271 fitod %f22, %f62
272 fitod %f23, %f62
273 fitod %f24, %f62
274 fitod %f25, %f62
275 fitod %f26, %f62
276 fitod %f27, %f62
277 fitod %f28, %f62
278 fitod %f29, %f62
279 fitod %f30, %f62
280 fitod %f31, %f62
281
282fitos_emul_continue:
283 sethi %hi(fitos_table_2), %g1
284 srl %g3, 25, %g2
285 or %g1, %lo(fitos_table_2), %g1
286 and %g2, 0x1f, %g2
287 sllx %g2, 2, %g2
288 jmpl %g1 + %g2, %g0
289 ba,pt %xcc, fitos_emul_fini
290
291fitos_table_2:
292 fdtos %f62, %f0
293 fdtos %f62, %f1
294 fdtos %f62, %f2
295 fdtos %f62, %f3
296 fdtos %f62, %f4
297 fdtos %f62, %f5
298 fdtos %f62, %f6
299 fdtos %f62, %f7
300 fdtos %f62, %f8
301 fdtos %f62, %f9
302 fdtos %f62, %f10
303 fdtos %f62, %f11
304 fdtos %f62, %f12
305 fdtos %f62, %f13
306 fdtos %f62, %f14
307 fdtos %f62, %f15
308 fdtos %f62, %f16
309 fdtos %f62, %f17
310 fdtos %f62, %f18
311 fdtos %f62, %f19
312 fdtos %f62, %f20
313 fdtos %f62, %f21
314 fdtos %f62, %f22
315 fdtos %f62, %f23
316 fdtos %f62, %f24
317 fdtos %f62, %f25
318 fdtos %f62, %f26
319 fdtos %f62, %f27
320 fdtos %f62, %f28
321 fdtos %f62, %f29
322 fdtos %f62, %f30
323 fdtos %f62, %f31
324
325fitos_emul_fini:
326 ldd [%g6 + TI_FPREGS + (62 * 4)], %f62
327 done
328 .size do_fpother_check_fitos,.-do_fpother_check_fitos
329
330 .align 32
331 .globl do_fptrap
332 .type do_fptrap,#function
333do_fptrap:
334 TRAP_LOAD_THREAD_REG(%g6, %g1)
335 stx %fsr, [%g6 + TI_XFSR]
336do_fptrap_after_fsr:
337 ldub [%g6 + TI_FPSAVED], %g3
338 rd %fprs, %g1
339 or %g3, %g1, %g3
340 stb %g3, [%g6 + TI_FPSAVED]
341 rd %gsr, %g3
342 stx %g3, [%g6 + TI_GSR]
343 mov SECONDARY_CONTEXT, %g3
344
345661: ldxa [%g3] ASI_DMMU, %g5
346 .section .sun4v_1insn_patch, "ax"
347 .word 661b
348 ldxa [%g3] ASI_MMU, %g5
349 .previous
350
351 sethi %hi(sparc64_kern_sec_context), %g2
352 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
353
354661: stxa %g2, [%g3] ASI_DMMU
355 .section .sun4v_1insn_patch, "ax"
356 .word 661b
357 stxa %g2, [%g3] ASI_MMU
358 .previous
359
360 membar #Sync
361 add %g6, TI_FPREGS, %g2
362 andcc %g1, FPRS_DL, %g0
363 be,pn %icc, 4f
364 mov 0x40, %g3
365 stda %f0, [%g2] ASI_BLK_S
366 stda %f16, [%g2 + %g3] ASI_BLK_S
367 andcc %g1, FPRS_DU, %g0
368 be,pn %icc, 5f
3694: add %g2, 128, %g2
370 stda %f32, [%g2] ASI_BLK_S
371 stda %f48, [%g2 + %g3] ASI_BLK_S
3725: mov SECONDARY_CONTEXT, %g1
373 membar #Sync
374
375661: stxa %g5, [%g1] ASI_DMMU
376 .section .sun4v_1insn_patch, "ax"
377 .word 661b
378 stxa %g5, [%g1] ASI_MMU
379 .previous
380
381 membar #Sync
382 ba,pt %xcc, etrap
383 wr %g0, 0, %fprs
384 .size do_fptrap,.-do_fptrap
diff --git a/arch/sparc64/kernel/getsetcc.S b/arch/sparc64/kernel/getsetcc.S
new file mode 100644
index 000000000000..a14d272d2061
--- /dev/null
+++ b/arch/sparc64/kernel/getsetcc.S
@@ -0,0 +1,24 @@
1 .globl getcc
2 .type getcc,#function
3getcc:
4 ldx [%o0 + PT_V9_TSTATE], %o1
5 srlx %o1, 32, %o1
6 and %o1, 0xf, %o1
7 retl
8 stx %o1, [%o0 + PT_V9_G1]
9 .size getcc,.-getcc
10
11 .globl setcc
12 .type setcc,#function
13setcc:
14 ldx [%o0 + PT_V9_TSTATE], %o1
15 ldx [%o0 + PT_V9_G1], %o2
16 or %g0, %ulo(TSTATE_ICC), %o3
17 sllx %o3, 32, %o3
18 andn %o1, %o3, %o1
19 sllx %o2, 32, %o2
20 and %o2, %o3, %o2
21 or %o1, %o2, %o1
22 retl
23 stx %o1, [%o0 + PT_V9_TSTATE]
24 .size setcc,.-setcc
diff --git a/arch/sparc64/kernel/head.S b/arch/sparc64/kernel/head.S
index 34f8ff57c56b..c9afef093d51 100644
--- a/arch/sparc64/kernel/head.S
+++ b/arch/sparc64/kernel/head.S
@@ -27,6 +27,10 @@
27#include <asm/ttable.h> 27#include <asm/ttable.h>
28#include <asm/mmu.h> 28#include <asm/mmu.h>
29#include <asm/cpudata.h> 29#include <asm/cpudata.h>
30#include <asm/pil.h>
31#include <asm/estate.h>
32#include <asm/sfafsr.h>
33#include <asm/unistd.h>
30 34
31/* This section from from _start to sparc64_boot_end should fit into 35/* This section from from _start to sparc64_boot_end should fit into
32 * 0x0000000000404000 to 0x0000000000408000. 36 * 0x0000000000404000 to 0x0000000000408000.
@@ -823,7 +827,16 @@ sparc64_boot_end:
823#include "etrap.S" 827#include "etrap.S"
824#include "rtrap.S" 828#include "rtrap.S"
825#include "winfixup.S" 829#include "winfixup.S"
826#include "entry.S" 830#include "fpu_traps.S"
831#include "ivec.S"
832#include "getsetcc.S"
833#include "utrap.S"
834#include "spiterrs.S"
835#include "cherrs.S"
836#include "misctrap.S"
837#include "syscalls.S"
838#include "helpers.S"
839#include "hvcalls.S"
827#include "sun4v_tlb_miss.S" 840#include "sun4v_tlb_miss.S"
828#include "sun4v_ivec.S" 841#include "sun4v_ivec.S"
829#include "ktlb.S" 842#include "ktlb.S"
diff --git a/arch/sparc64/kernel/helpers.S b/arch/sparc64/kernel/helpers.S
new file mode 100644
index 000000000000..314dd0c9fc5b
--- /dev/null
+++ b/arch/sparc64/kernel/helpers.S
@@ -0,0 +1,63 @@
1 .align 32
2 .globl __flushw_user
3 .type __flushw_user,#function
4__flushw_user:
5 rdpr %otherwin, %g1
6 brz,pn %g1, 2f
7 clr %g2
81: save %sp, -128, %sp
9 rdpr %otherwin, %g1
10 brnz,pt %g1, 1b
11 add %g2, 1, %g2
121: sub %g2, 1, %g2
13 brnz,pt %g2, 1b
14 restore %g0, %g0, %g0
152: retl
16 nop
17 .size __flushw_user,.-__flushw_user
18
19 /* Flush %fp and %i7 to the stack for all register
20 * windows active inside of the cpu. This allows
21 * show_stack_trace() to avoid using an expensive
22 * 'flushw'.
23 */
24 .globl stack_trace_flush
25 .type stack_trace_flush,#function
26stack_trace_flush:
27 rdpr %pstate, %o0
28 wrpr %o0, PSTATE_IE, %pstate
29
30 rdpr %cwp, %g1
31 rdpr %canrestore, %g2
32 sub %g1, 1, %g3
33
341: brz,pn %g2, 2f
35 sub %g2, 1, %g2
36 wrpr %g3, %cwp
37 stx %fp, [%sp + STACK_BIAS + RW_V9_I6]
38 stx %i7, [%sp + STACK_BIAS + RW_V9_I7]
39 ba,pt %xcc, 1b
40 sub %g3, 1, %g3
41
422: wrpr %g1, %cwp
43 wrpr %o0, %pstate
44
45 retl
46 nop
47 .size stack_trace_flush,.-stack_trace_flush
48
49#ifdef CONFIG_SMP
50 .globl hard_smp_processor_id
51 .type hard_smp_processor_id,#function
52hard_smp_processor_id:
53#endif
54 .globl real_hard_smp_processor_id
55 .type real_hard_smp_processor_id,#function
56real_hard_smp_processor_id:
57 __GET_CPUID(%o0)
58 retl
59 nop
60#ifdef CONFIG_SMP
61 .size hard_smp_processor_id,.-hard_smp_processor_id
62#endif
63 .size real_hard_smp_processor_id,.-real_hard_smp_processor_id
diff --git a/arch/sparc64/kernel/hvcalls.S b/arch/sparc64/kernel/hvcalls.S
new file mode 100644
index 000000000000..a2810f3ac70f
--- /dev/null
+++ b/arch/sparc64/kernel/hvcalls.S
@@ -0,0 +1,886 @@
1 /* %o0: devhandle
2 * %o1: devino
3 *
4 * returns %o0: sysino
5 */
6 .globl sun4v_devino_to_sysino
7 .type sun4v_devino_to_sysino,#function
8sun4v_devino_to_sysino:
9 mov HV_FAST_INTR_DEVINO2SYSINO, %o5
10 ta HV_FAST_TRAP
11 retl
12 mov %o1, %o0
13 .size sun4v_devino_to_sysino, .-sun4v_devino_to_sysino
14
15 /* %o0: sysino
16 *
17 * returns %o0: intr_enabled (HV_INTR_{DISABLED,ENABLED})
18 */
19 .globl sun4v_intr_getenabled
20 .type sun4v_intr_getenabled,#function
21sun4v_intr_getenabled:
22 mov HV_FAST_INTR_GETENABLED, %o5
23 ta HV_FAST_TRAP
24 retl
25 mov %o1, %o0
26 .size sun4v_intr_getenabled, .-sun4v_intr_getenabled
27
28 /* %o0: sysino
29 * %o1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
30 */
31 .globl sun4v_intr_setenabled
32 .type sun4v_intr_setenabled,#function
33sun4v_intr_setenabled:
34 mov HV_FAST_INTR_SETENABLED, %o5
35 ta HV_FAST_TRAP
36 retl
37 nop
38 .size sun4v_intr_setenabled, .-sun4v_intr_setenabled
39
40 /* %o0: sysino
41 *
42 * returns %o0: intr_state (HV_INTR_STATE_*)
43 */
44 .globl sun4v_intr_getstate
45 .type sun4v_intr_getstate,#function
46sun4v_intr_getstate:
47 mov HV_FAST_INTR_GETSTATE, %o5
48 ta HV_FAST_TRAP
49 retl
50 mov %o1, %o0
51 .size sun4v_intr_getstate, .-sun4v_intr_getstate
52
53 /* %o0: sysino
54 * %o1: intr_state (HV_INTR_STATE_*)
55 */
56 .globl sun4v_intr_setstate
57 .type sun4v_intr_setstate,#function
58sun4v_intr_setstate:
59 mov HV_FAST_INTR_SETSTATE, %o5
60 ta HV_FAST_TRAP
61 retl
62 nop
63 .size sun4v_intr_setstate, .-sun4v_intr_setstate
64
65 /* %o0: sysino
66 *
67 * returns %o0: cpuid
68 */
69 .globl sun4v_intr_gettarget
70 .type sun4v_intr_gettarget,#function
71sun4v_intr_gettarget:
72 mov HV_FAST_INTR_GETTARGET, %o5
73 ta HV_FAST_TRAP
74 retl
75 mov %o1, %o0
76 .size sun4v_intr_gettarget, .-sun4v_intr_gettarget
77
78 /* %o0: sysino
79 * %o1: cpuid
80 */
81 .globl sun4v_intr_settarget
82 .type sun4v_intr_settarget,#function
83sun4v_intr_settarget:
84 mov HV_FAST_INTR_SETTARGET, %o5
85 ta HV_FAST_TRAP
86 retl
87 nop
88 .size sun4v_intr_settarget, .-sun4v_intr_settarget
89
90 /* %o0: cpuid
91 * %o1: pc
92 * %o2: rtba
93 * %o3: arg0
94 *
95 * returns %o0: status
96 */
97 .globl sun4v_cpu_start
98 .type sun4v_cpu_start,#function
99sun4v_cpu_start:
100 mov HV_FAST_CPU_START, %o5
101 ta HV_FAST_TRAP
102 retl
103 nop
104 .size sun4v_cpu_start, .-sun4v_cpu_start
105
106 /* %o0: cpuid
107 *
108 * returns %o0: status
109 */
110 .globl sun4v_cpu_stop
111 .type sun4v_cpu_stop,#function
112sun4v_cpu_stop:
113 mov HV_FAST_CPU_STOP, %o5
114 ta HV_FAST_TRAP
115 retl
116 nop
117 .size sun4v_cpu_stop, .-sun4v_cpu_stop
118
119 /* returns %o0: status */
120 .globl sun4v_cpu_yield
121 .type sun4v_cpu_yield, #function
122sun4v_cpu_yield:
123 mov HV_FAST_CPU_YIELD, %o5
124 ta HV_FAST_TRAP
125 retl
126 nop
127 .size sun4v_cpu_yield, .-sun4v_cpu_yield
128
129 /* %o0: type
130 * %o1: queue paddr
131 * %o2: num queue entries
132 *
133 * returns %o0: status
134 */
135 .globl sun4v_cpu_qconf
136 .type sun4v_cpu_qconf,#function
137sun4v_cpu_qconf:
138 mov HV_FAST_CPU_QCONF, %o5
139 ta HV_FAST_TRAP
140 retl
141 nop
142 .size sun4v_cpu_qconf, .-sun4v_cpu_qconf
143
144 /* %o0: num cpus in cpu list
145 * %o1: cpu list paddr
146 * %o2: mondo block paddr
147 *
148 * returns %o0: status
149 */
150 .globl sun4v_cpu_mondo_send
151 .type sun4v_cpu_mondo_send,#function
152sun4v_cpu_mondo_send:
153 mov HV_FAST_CPU_MONDO_SEND, %o5
154 ta HV_FAST_TRAP
155 retl
156 nop
157 .size sun4v_cpu_mondo_send, .-sun4v_cpu_mondo_send
158
159 /* %o0: CPU ID
160 *
161 * returns %o0: -status if status non-zero, else
162 * %o0: cpu state as HV_CPU_STATE_*
163 */
164 .globl sun4v_cpu_state
165 .type sun4v_cpu_state,#function
166sun4v_cpu_state:
167 mov HV_FAST_CPU_STATE, %o5
168 ta HV_FAST_TRAP
169 brnz,pn %o0, 1f
170 sub %g0, %o0, %o0
171 mov %o1, %o0
1721: retl
173 nop
174 .size sun4v_cpu_state, .-sun4v_cpu_state
175
176 /* %o0: virtual address
177 * %o1: must be zero
178 * %o2: TTE
179 * %o3: HV_MMU_* flags
180 *
181 * returns %o0: status
182 */
183 .globl sun4v_mmu_map_perm_addr
184 .type sun4v_mmu_map_perm_addr,#function
185sun4v_mmu_map_perm_addr:
186 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
187 ta HV_FAST_TRAP
188 retl
189 nop
190 .size sun4v_mmu_map_perm_addr, .-sun4v_mmu_map_perm_addr
191
192 /* %o0: number of TSB descriptions
193 * %o1: TSB descriptions real address
194 *
195 * returns %o0: status
196 */
197 .globl sun4v_mmu_tsb_ctx0
198 .type sun4v_mmu_tsb_ctx0,#function
199sun4v_mmu_tsb_ctx0:
200 mov HV_FAST_MMU_TSB_CTX0, %o5
201 ta HV_FAST_TRAP
202 retl
203 nop
204 .size sun4v_mmu_tsb_ctx0, .-sun4v_mmu_tsb_ctx0
205
206 /* %o0: API group number
207 * %o1: pointer to unsigned long major number storage
208 * %o2: pointer to unsigned long minor number storage
209 *
210 * returns %o0: status
211 */
212 .globl sun4v_get_version
213 .type sun4v_get_version,#function
214sun4v_get_version:
215 mov HV_CORE_GET_VER, %o5
216 mov %o1, %o3
217 mov %o2, %o4
218 ta HV_CORE_TRAP
219 stx %o1, [%o3]
220 retl
221 stx %o2, [%o4]
222 .size sun4v_get_version, .-sun4v_get_version
223
224 /* %o0: API group number
225 * %o1: desired major number
226 * %o2: desired minor number
227 * %o3: pointer to unsigned long actual minor number storage
228 *
229 * returns %o0: status
230 */
231 .globl sun4v_set_version
232 .type sun4v_set_version,#function
233sun4v_set_version:
234 mov HV_CORE_SET_VER, %o5
235 mov %o3, %o4
236 ta HV_CORE_TRAP
237 retl
238 stx %o1, [%o4]
239 .size sun4v_set_version, .-sun4v_set_version
240
241 /* %o0: pointer to unsigned long time
242 *
243 * returns %o0: status
244 */
245 .globl sun4v_tod_get
246 .type sun4v_tod_get,#function
247sun4v_tod_get:
248 mov %o0, %o4
249 mov HV_FAST_TOD_GET, %o5
250 ta HV_FAST_TRAP
251 stx %o1, [%o4]
252 retl
253 nop
254 .size sun4v_tod_get, .-sun4v_tod_get
255
256 /* %o0: time
257 *
258 * returns %o0: status
259 */
260 .globl sun4v_tod_set
261 .type sun4v_tod_set,#function
262sun4v_tod_set:
263 mov HV_FAST_TOD_SET, %o5
264 ta HV_FAST_TRAP
265 retl
266 nop
267 .size sun4v_tod_set, .-sun4v_tod_set
268
269 /* %o0: pointer to unsigned long status
270 *
271 * returns %o0: signed character
272 */
273 .globl sun4v_con_getchar
274 .type sun4v_con_getchar,#function
275sun4v_con_getchar:
276 mov %o0, %o4
277 mov HV_FAST_CONS_GETCHAR, %o5
278 clr %o0
279 clr %o1
280 ta HV_FAST_TRAP
281 stx %o0, [%o4]
282 retl
283 sra %o1, 0, %o0
284 .size sun4v_con_getchar, .-sun4v_con_getchar
285
286 /* %o0: signed long character
287 *
288 * returns %o0: status
289 */
290 .globl sun4v_con_putchar
291 .type sun4v_con_putchar,#function
292sun4v_con_putchar:
293 mov HV_FAST_CONS_PUTCHAR, %o5
294 ta HV_FAST_TRAP
295 retl
296 sra %o0, 0, %o0
297 .size sun4v_con_putchar, .-sun4v_con_putchar
298
299 /* %o0: buffer real address
300 * %o1: buffer size
301 * %o2: pointer to unsigned long bytes_read
302 *
303 * returns %o0: status
304 */
305 .globl sun4v_con_read
306 .type sun4v_con_read,#function
307sun4v_con_read:
308 mov %o2, %o4
309 mov HV_FAST_CONS_READ, %o5
310 ta HV_FAST_TRAP
311 brnz %o0, 1f
312 cmp %o1, -1 /* break */
313 be,a,pn %icc, 1f
314 mov %o1, %o0
315 cmp %o1, -2 /* hup */
316 be,a,pn %icc, 1f
317 mov %o1, %o0
318 stx %o1, [%o4]
3191: retl
320 nop
321 .size sun4v_con_read, .-sun4v_con_read
322
323 /* %o0: buffer real address
324 * %o1: buffer size
325 * %o2: pointer to unsigned long bytes_written
326 *
327 * returns %o0: status
328 */
329 .globl sun4v_con_write
330 .type sun4v_con_write,#function
331sun4v_con_write:
332 mov %o2, %o4
333 mov HV_FAST_CONS_WRITE, %o5
334 ta HV_FAST_TRAP
335 stx %o1, [%o4]
336 retl
337 nop
338 .size sun4v_con_write, .-sun4v_con_write
339
340 /* %o0: soft state
341 * %o1: address of description string
342 *
343 * returns %o0: status
344 */
345 .globl sun4v_mach_set_soft_state
346 .type sun4v_mach_set_soft_state,#function
347sun4v_mach_set_soft_state:
348 mov HV_FAST_MACH_SET_SOFT_STATE, %o5
349 ta HV_FAST_TRAP
350 retl
351 nop
352 .size sun4v_mach_set_soft_state, .-sun4v_mach_set_soft_state
353
354 /* %o0: exit code
355 *
356 * Does not return.
357 */
358 .globl sun4v_mach_exit
359 .type sun4v_mach_exit,#function
360sun4v_mach_exit:
361 mov HV_FAST_MACH_EXIT, %o5
362 ta HV_FAST_TRAP
363 retl
364 nop
365 .size sun4v_mach_exit, .-sun4v_mach_exit
366
367 /* %o0: buffer real address
368 * %o1: buffer length
369 * %o2: pointer to unsigned long real_buf_len
370 *
371 * returns %o0: status
372 */
373 .globl sun4v_mach_desc
374 .type sun4v_mach_desc,#function
375sun4v_mach_desc:
376 mov %o2, %o4
377 mov HV_FAST_MACH_DESC, %o5
378 ta HV_FAST_TRAP
379 stx %o1, [%o4]
380 retl
381 nop
382 .size sun4v_mach_desc, .-sun4v_mach_desc
383
384 /* %o0: new timeout in milliseconds
385 * %o1: pointer to unsigned long orig_timeout
386 *
387 * returns %o0: status
388 */
389 .globl sun4v_mach_set_watchdog
390 .type sun4v_mach_set_watchdog,#function
391sun4v_mach_set_watchdog:
392 mov %o1, %o4
393 mov HV_FAST_MACH_SET_WATCHDOG, %o5
394 ta HV_FAST_TRAP
395 stx %o1, [%o4]
396 retl
397 nop
398 .size sun4v_mach_set_watchdog, .-sun4v_mach_set_watchdog
399
400 /* No inputs and does not return. */
401 .globl sun4v_mach_sir
402 .type sun4v_mach_sir,#function
403sun4v_mach_sir:
404 mov %o1, %o4
405 mov HV_FAST_MACH_SIR, %o5
406 ta HV_FAST_TRAP
407 stx %o1, [%o4]
408 retl
409 nop
410 .size sun4v_mach_sir, .-sun4v_mach_sir
411
412 /* %o0: channel
413 * %o1: ra
414 * %o2: num_entries
415 *
416 * returns %o0: status
417 */
418 .globl sun4v_ldc_tx_qconf
419 .type sun4v_ldc_tx_qconf,#function
420sun4v_ldc_tx_qconf:
421 mov HV_FAST_LDC_TX_QCONF, %o5
422 ta HV_FAST_TRAP
423 retl
424 nop
425 .size sun4v_ldc_tx_qconf, .-sun4v_ldc_tx_qconf
426
427 /* %o0: channel
428 * %o1: pointer to unsigned long ra
429 * %o2: pointer to unsigned long num_entries
430 *
431 * returns %o0: status
432 */
433 .globl sun4v_ldc_tx_qinfo
434 .type sun4v_ldc_tx_qinfo,#function
435sun4v_ldc_tx_qinfo:
436 mov %o1, %g1
437 mov %o2, %g2
438 mov HV_FAST_LDC_TX_QINFO, %o5
439 ta HV_FAST_TRAP
440 stx %o1, [%g1]
441 stx %o2, [%g2]
442 retl
443 nop
444 .size sun4v_ldc_tx_qinfo, .-sun4v_ldc_tx_qinfo
445
446 /* %o0: channel
447 * %o1: pointer to unsigned long head_off
448 * %o2: pointer to unsigned long tail_off
449 * %o2: pointer to unsigned long chan_state
450 *
451 * returns %o0: status
452 */
453 .globl sun4v_ldc_tx_get_state
454 .type sun4v_ldc_tx_get_state,#function
455sun4v_ldc_tx_get_state:
456 mov %o1, %g1
457 mov %o2, %g2
458 mov %o3, %g3
459 mov HV_FAST_LDC_TX_GET_STATE, %o5
460 ta HV_FAST_TRAP
461 stx %o1, [%g1]
462 stx %o2, [%g2]
463 stx %o3, [%g3]
464 retl
465 nop
466 .size sun4v_ldc_tx_get_state, .-sun4v_ldc_tx_get_state
467
468 /* %o0: channel
469 * %o1: tail_off
470 *
471 * returns %o0: status
472 */
473 .globl sun4v_ldc_tx_set_qtail
474 .type sun4v_ldc_tx_set_qtail,#function
475sun4v_ldc_tx_set_qtail:
476 mov HV_FAST_LDC_TX_SET_QTAIL, %o5
477 ta HV_FAST_TRAP
478 retl
479 nop
480 .size sun4v_ldc_tx_set_qtail, .-sun4v_ldc_tx_set_qtail
481
482 /* %o0: channel
483 * %o1: ra
484 * %o2: num_entries
485 *
486 * returns %o0: status
487 */
488 .globl sun4v_ldc_rx_qconf
489 .type sun4v_ldc_rx_qconf,#function
490sun4v_ldc_rx_qconf:
491 mov HV_FAST_LDC_RX_QCONF, %o5
492 ta HV_FAST_TRAP
493 retl
494 nop
495 .size sun4v_ldc_rx_qconf, .-sun4v_ldc_rx_qconf
496
497 /* %o0: channel
498 * %o1: pointer to unsigned long ra
499 * %o2: pointer to unsigned long num_entries
500 *
501 * returns %o0: status
502 */
503 .globl sun4v_ldc_rx_qinfo
504 .type sun4v_ldc_rx_qinfo,#function
505sun4v_ldc_rx_qinfo:
506 mov %o1, %g1
507 mov %o2, %g2
508 mov HV_FAST_LDC_RX_QINFO, %o5
509 ta HV_FAST_TRAP
510 stx %o1, [%g1]
511 stx %o2, [%g2]
512 retl
513 nop
514 .size sun4v_ldc_rx_qinfo, .-sun4v_ldc_rx_qinfo
515
516 /* %o0: channel
517 * %o1: pointer to unsigned long head_off
518 * %o2: pointer to unsigned long tail_off
519 * %o2: pointer to unsigned long chan_state
520 *
521 * returns %o0: status
522 */
523 .globl sun4v_ldc_rx_get_state
524 .type sun4v_ldc_rx_get_state,#function
525sun4v_ldc_rx_get_state:
526 mov %o1, %g1
527 mov %o2, %g2
528 mov %o3, %g3
529 mov HV_FAST_LDC_RX_GET_STATE, %o5
530 ta HV_FAST_TRAP
531 stx %o1, [%g1]
532 stx %o2, [%g2]
533 stx %o3, [%g3]
534 retl
535 nop
536 .size sun4v_ldc_rx_get_state, .-sun4v_ldc_rx_get_state
537
538 /* %o0: channel
539 * %o1: head_off
540 *
541 * returns %o0: status
542 */
543 .globl sun4v_ldc_rx_set_qhead
544 .type sun4v_ldc_rx_set_qhead,#function
545sun4v_ldc_rx_set_qhead:
546 mov HV_FAST_LDC_RX_SET_QHEAD, %o5
547 ta HV_FAST_TRAP
548 retl
549 nop
550 .size sun4v_ldc_rx_set_qhead, .-sun4v_ldc_rx_set_qhead
551
552 /* %o0: channel
553 * %o1: ra
554 * %o2: num_entries
555 *
556 * returns %o0: status
557 */
558 .globl sun4v_ldc_set_map_table
559 .type sun4v_ldc_set_map_table,#function
560sun4v_ldc_set_map_table:
561 mov HV_FAST_LDC_SET_MAP_TABLE, %o5
562 ta HV_FAST_TRAP
563 retl
564 nop
565 .size sun4v_ldc_set_map_table, .-sun4v_ldc_set_map_table
566
567 /* %o0: channel
568 * %o1: pointer to unsigned long ra
569 * %o2: pointer to unsigned long num_entries
570 *
571 * returns %o0: status
572 */
573 .globl sun4v_ldc_get_map_table
574 .type sun4v_ldc_get_map_table,#function
575sun4v_ldc_get_map_table:
576 mov %o1, %g1
577 mov %o2, %g2
578 mov HV_FAST_LDC_GET_MAP_TABLE, %o5
579 ta HV_FAST_TRAP
580 stx %o1, [%g1]
581 stx %o2, [%g2]
582 retl
583 nop
584 .size sun4v_ldc_get_map_table, .-sun4v_ldc_get_map_table
585
586 /* %o0: channel
587 * %o1: dir_code
588 * %o2: tgt_raddr
589 * %o3: lcl_raddr
590 * %o4: len
591 * %o5: pointer to unsigned long actual_len
592 *
593 * returns %o0: status
594 */
595 .globl sun4v_ldc_copy
596 .type sun4v_ldc_copy,#function
597sun4v_ldc_copy:
598 mov %o5, %g1
599 mov HV_FAST_LDC_COPY, %o5
600 ta HV_FAST_TRAP
601 stx %o1, [%g1]
602 retl
603 nop
604 .size sun4v_ldc_copy, .-sun4v_ldc_copy
605
606 /* %o0: channel
607 * %o1: cookie
608 * %o2: pointer to unsigned long ra
609 * %o3: pointer to unsigned long perm
610 *
611 * returns %o0: status
612 */
613 .globl sun4v_ldc_mapin
614 .type sun4v_ldc_mapin,#function
615sun4v_ldc_mapin:
616 mov %o2, %g1
617 mov %o3, %g2
618 mov HV_FAST_LDC_MAPIN, %o5
619 ta HV_FAST_TRAP
620 stx %o1, [%g1]
621 stx %o2, [%g2]
622 retl
623 nop
624 .size sun4v_ldc_mapin, .-sun4v_ldc_mapin
625
626 /* %o0: ra
627 *
628 * returns %o0: status
629 */
630 .globl sun4v_ldc_unmap
631 .type sun4v_ldc_unmap,#function
632sun4v_ldc_unmap:
633 mov HV_FAST_LDC_UNMAP, %o5
634 ta HV_FAST_TRAP
635 retl
636 nop
637 .size sun4v_ldc_unmap, .-sun4v_ldc_unmap
638
639 /* %o0: channel
640 * %o1: cookie
641 * %o2: mte_cookie
642 *
643 * returns %o0: status
644 */
645 .globl sun4v_ldc_revoke
646 .type sun4v_ldc_revoke,#function
647sun4v_ldc_revoke:
648 mov HV_FAST_LDC_REVOKE, %o5
649 ta HV_FAST_TRAP
650 retl
651 nop
652 .size sun4v_ldc_revoke, .-sun4v_ldc_revoke
653
654 /* %o0: device handle
655 * %o1: device INO
656 * %o2: pointer to unsigned long cookie
657 *
658 * returns %o0: status
659 */
660 .globl sun4v_vintr_get_cookie
661 .type sun4v_vintr_get_cookie,#function
662sun4v_vintr_get_cookie:
663 mov %o2, %g1
664 mov HV_FAST_VINTR_GET_COOKIE, %o5
665 ta HV_FAST_TRAP
666 stx %o1, [%g1]
667 retl
668 nop
669 .size sun4v_vintr_get_cookie, .-sun4v_vintr_get_cookie
670
671 /* %o0: device handle
672 * %o1: device INO
673 * %o2: cookie
674 *
675 * returns %o0: status
676 */
677 .globl sun4v_vintr_set_cookie
678 .type sun4v_vintr_set_cookie,#function
679sun4v_vintr_set_cookie:
680 mov HV_FAST_VINTR_SET_COOKIE, %o5
681 ta HV_FAST_TRAP
682 retl
683 nop
684 .size sun4v_vintr_set_cookie, .-sun4v_vintr_set_cookie
685
686 /* %o0: device handle
687 * %o1: device INO
688 * %o2: pointer to unsigned long valid_state
689 *
690 * returns %o0: status
691 */
692 .globl sun4v_vintr_get_valid
693 .type sun4v_vintr_get_valid,#function
694sun4v_vintr_get_valid:
695 mov %o2, %g1
696 mov HV_FAST_VINTR_GET_VALID, %o5
697 ta HV_FAST_TRAP
698 stx %o1, [%g1]
699 retl
700 nop
701 .size sun4v_vintr_get_valid, .-sun4v_vintr_get_valid
702
703 /* %o0: device handle
704 * %o1: device INO
705 * %o2: valid_state
706 *
707 * returns %o0: status
708 */
709 .globl sun4v_vintr_set_valid
710 .type sun4v_vintr_set_valid,#function
711sun4v_vintr_set_valid:
712 mov HV_FAST_VINTR_SET_VALID, %o5
713 ta HV_FAST_TRAP
714 retl
715 nop
716 .size sun4v_vintr_set_valid, .-sun4v_vintr_set_valid
717
718 /* %o0: device handle
719 * %o1: device INO
720 * %o2: pointer to unsigned long state
721 *
722 * returns %o0: status
723 */
724 .globl sun4v_vintr_get_state
725 .type sun4v_vintr_get_state,#function
726sun4v_vintr_get_state:
727 mov %o2, %g1
728 mov HV_FAST_VINTR_GET_STATE, %o5
729 ta HV_FAST_TRAP
730 stx %o1, [%g1]
731 retl
732 nop
733 .size sun4v_vintr_get_state, .-sun4v_vintr_get_state
734
735 /* %o0: device handle
736 * %o1: device INO
737 * %o2: state
738 *
739 * returns %o0: status
740 */
741 .globl sun4v_vintr_set_state
742 .type sun4v_vintr_set_state,#function
743sun4v_vintr_set_state:
744 mov HV_FAST_VINTR_SET_STATE, %o5
745 ta HV_FAST_TRAP
746 retl
747 nop
748 .size sun4v_vintr_set_state, .-sun4v_vintr_set_state
749
750 /* %o0: device handle
751 * %o1: device INO
752 * %o2: pointer to unsigned long cpuid
753 *
754 * returns %o0: status
755 */
756 .globl sun4v_vintr_get_target
757 .type sun4v_vintr_get_target,#function
758sun4v_vintr_get_target:
759 mov %o2, %g1
760 mov HV_FAST_VINTR_GET_TARGET, %o5
761 ta HV_FAST_TRAP
762 stx %o1, [%g1]
763 retl
764 nop
765 .size sun4v_vintr_get_target, .-sun4v_vintr_get_target
766
767 /* %o0: device handle
768 * %o1: device INO
769 * %o2: cpuid
770 *
771 * returns %o0: status
772 */
773 .globl sun4v_vintr_set_target
774 .type sun4v_vintr_set_target,#function
775sun4v_vintr_set_target:
776 mov HV_FAST_VINTR_SET_TARGET, %o5
777 ta HV_FAST_TRAP
778 retl
779 nop
780 .size sun4v_vintr_set_target, .-sun4v_vintr_set_target
781
782 /* %o0: NCS sub-function
783 * %o1: sub-function arg real-address
784 * %o2: sub-function arg size
785 *
786 * returns %o0: status
787 */
788 .globl sun4v_ncs_request
789 .type sun4v_ncs_request,#function
790sun4v_ncs_request:
791 mov HV_FAST_NCS_REQUEST, %o5
792 ta HV_FAST_TRAP
793 retl
794 nop
795 .size sun4v_ncs_request, .-sun4v_ncs_request
796
797 .globl sun4v_svc_send
798 .type sun4v_svc_send,#function
799sun4v_svc_send:
800 save %sp, -192, %sp
801 mov %i0, %o0
802 mov %i1, %o1
803 mov %i2, %o2
804 mov HV_FAST_SVC_SEND, %o5
805 ta HV_FAST_TRAP
806 stx %o1, [%i3]
807 ret
808 restore
809 .size sun4v_svc_send, .-sun4v_svc_send
810
811 .globl sun4v_svc_recv
812 .type sun4v_svc_recv,#function
813sun4v_svc_recv:
814 save %sp, -192, %sp
815 mov %i0, %o0
816 mov %i1, %o1
817 mov %i2, %o2
818 mov HV_FAST_SVC_RECV, %o5
819 ta HV_FAST_TRAP
820 stx %o1, [%i3]
821 ret
822 restore
823 .size sun4v_svc_recv, .-sun4v_svc_recv
824
825 .globl sun4v_svc_getstatus
826 .type sun4v_svc_getstatus,#function
827sun4v_svc_getstatus:
828 mov HV_FAST_SVC_GETSTATUS, %o5
829 mov %o1, %o4
830 ta HV_FAST_TRAP
831 stx %o1, [%o4]
832 retl
833 nop
834 .size sun4v_svc_getstatus, .-sun4v_svc_getstatus
835
836 .globl sun4v_svc_setstatus
837 .type sun4v_svc_setstatus,#function
838sun4v_svc_setstatus:
839 mov HV_FAST_SVC_SETSTATUS, %o5
840 ta HV_FAST_TRAP
841 retl
842 nop
843 .size sun4v_svc_setstatus, .-sun4v_svc_setstatus
844
845 .globl sun4v_svc_clrstatus
846 .type sun4v_svc_clrstatus,#function
847sun4v_svc_clrstatus:
848 mov HV_FAST_SVC_CLRSTATUS, %o5
849 ta HV_FAST_TRAP
850 retl
851 nop
852 .size sun4v_svc_clrstatus, .-sun4v_svc_clrstatus
853
854 .globl sun4v_mmustat_conf
855 .type sun4v_mmustat_conf,#function
856sun4v_mmustat_conf:
857 mov %o1, %o4
858 mov HV_FAST_MMUSTAT_CONF, %o5
859 ta HV_FAST_TRAP
860 stx %o1, [%o4]
861 retl
862 nop
863 .size sun4v_mmustat_conf, .-sun4v_mmustat_conf
864
865 .globl sun4v_mmustat_info
866 .type sun4v_mmustat_info,#function
867sun4v_mmustat_info:
868 mov %o0, %o4
869 mov HV_FAST_MMUSTAT_INFO, %o5
870 ta HV_FAST_TRAP
871 stx %o1, [%o4]
872 retl
873 nop
874 .size sun4v_mmustat_info, .-sun4v_mmustat_info
875
876 .globl sun4v_mmu_demap_all
877 .type sun4v_mmu_demap_all,#function
878sun4v_mmu_demap_all:
879 clr %o0
880 clr %o1
881 mov HV_MMU_ALL, %o2
882 mov HV_FAST_MMU_DEMAP_ALL, %o5
883 ta HV_FAST_TRAP
884 retl
885 nop
886 .size sun4v_mmu_demap_all, .-sun4v_mmu_demap_all
diff --git a/arch/sparc64/kernel/iommu.c b/arch/sparc64/kernel/iommu.c
index 756fa24eeefa..2a37a6ca2a16 100644
--- a/arch/sparc64/kernel/iommu.c
+++ b/arch/sparc64/kernel/iommu.c
@@ -173,9 +173,11 @@ void iommu_range_free(struct iommu *iommu, dma_addr_t dma_addr, unsigned long np
173} 173}
174 174
175int iommu_table_init(struct iommu *iommu, int tsbsize, 175int iommu_table_init(struct iommu *iommu, int tsbsize,
176 u32 dma_offset, u32 dma_addr_mask) 176 u32 dma_offset, u32 dma_addr_mask,
177 int numa_node)
177{ 178{
178 unsigned long i, tsbbase, order, sz, num_tsb_entries; 179 unsigned long i, order, sz, num_tsb_entries;
180 struct page *page;
179 181
180 num_tsb_entries = tsbsize / sizeof(iopte_t); 182 num_tsb_entries = tsbsize / sizeof(iopte_t);
181 183
@@ -188,11 +190,12 @@ int iommu_table_init(struct iommu *iommu, int tsbsize,
188 /* Allocate and initialize the free area map. */ 190 /* Allocate and initialize the free area map. */
189 sz = num_tsb_entries / 8; 191 sz = num_tsb_entries / 8;
190 sz = (sz + 7UL) & ~7UL; 192 sz = (sz + 7UL) & ~7UL;
191 iommu->arena.map = kzalloc(sz, GFP_KERNEL); 193 iommu->arena.map = kmalloc_node(sz, GFP_KERNEL, numa_node);
192 if (!iommu->arena.map) { 194 if (!iommu->arena.map) {
193 printk(KERN_ERR "IOMMU: Error, kmalloc(arena.map) failed.\n"); 195 printk(KERN_ERR "IOMMU: Error, kmalloc(arena.map) failed.\n");
194 return -ENOMEM; 196 return -ENOMEM;
195 } 197 }
198 memset(iommu->arena.map, 0, sz);
196 iommu->arena.limit = num_tsb_entries; 199 iommu->arena.limit = num_tsb_entries;
197 200
198 if (tlb_type != hypervisor) 201 if (tlb_type != hypervisor)
@@ -201,21 +204,23 @@ int iommu_table_init(struct iommu *iommu, int tsbsize,
201 /* Allocate and initialize the dummy page which we 204 /* Allocate and initialize the dummy page which we
202 * set inactive IO PTEs to point to. 205 * set inactive IO PTEs to point to.
203 */ 206 */
204 iommu->dummy_page = get_zeroed_page(GFP_KERNEL); 207 page = alloc_pages_node(numa_node, GFP_KERNEL, 0);
205 if (!iommu->dummy_page) { 208 if (!page) {
206 printk(KERN_ERR "IOMMU: Error, gfp(dummy_page) failed.\n"); 209 printk(KERN_ERR "IOMMU: Error, gfp(dummy_page) failed.\n");
207 goto out_free_map; 210 goto out_free_map;
208 } 211 }
212 iommu->dummy_page = (unsigned long) page_address(page);
213 memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
209 iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page); 214 iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
210 215
211 /* Now allocate and setup the IOMMU page table itself. */ 216 /* Now allocate and setup the IOMMU page table itself. */
212 order = get_order(tsbsize); 217 order = get_order(tsbsize);
213 tsbbase = __get_free_pages(GFP_KERNEL, order); 218 page = alloc_pages_node(numa_node, GFP_KERNEL, order);
214 if (!tsbbase) { 219 if (!page) {
215 printk(KERN_ERR "IOMMU: Error, gfp(tsb) failed.\n"); 220 printk(KERN_ERR "IOMMU: Error, gfp(tsb) failed.\n");
216 goto out_free_dummy_page; 221 goto out_free_dummy_page;
217 } 222 }
218 iommu->page_table = (iopte_t *)tsbbase; 223 iommu->page_table = (iopte_t *)page_address(page);
219 224
220 for (i = 0; i < num_tsb_entries; i++) 225 for (i = 0; i < num_tsb_entries; i++)
221 iopte_make_dummy(iommu, &iommu->page_table[i]); 226 iopte_make_dummy(iommu, &iommu->page_table[i]);
@@ -276,20 +281,24 @@ static inline void iommu_free_ctx(struct iommu *iommu, int ctx)
276static void *dma_4u_alloc_coherent(struct device *dev, size_t size, 281static void *dma_4u_alloc_coherent(struct device *dev, size_t size,
277 dma_addr_t *dma_addrp, gfp_t gfp) 282 dma_addr_t *dma_addrp, gfp_t gfp)
278{ 283{
284 unsigned long flags, order, first_page;
279 struct iommu *iommu; 285 struct iommu *iommu;
286 struct page *page;
287 int npages, nid;
280 iopte_t *iopte; 288 iopte_t *iopte;
281 unsigned long flags, order, first_page;
282 void *ret; 289 void *ret;
283 int npages;
284 290
285 size = IO_PAGE_ALIGN(size); 291 size = IO_PAGE_ALIGN(size);
286 order = get_order(size); 292 order = get_order(size);
287 if (order >= 10) 293 if (order >= 10)
288 return NULL; 294 return NULL;
289 295
290 first_page = __get_free_pages(gfp, order); 296 nid = dev->archdata.numa_node;
291 if (first_page == 0UL) 297 page = alloc_pages_node(nid, gfp, order);
298 if (unlikely(!page))
292 return NULL; 299 return NULL;
300
301 first_page = (unsigned long) page_address(page);
293 memset((char *)first_page, 0, PAGE_SIZE << order); 302 memset((char *)first_page, 0, PAGE_SIZE << order);
294 303
295 iommu = dev->archdata.iommu; 304 iommu = dev->archdata.iommu;
diff --git a/arch/sparc64/kernel/irq.c b/arch/sparc64/kernel/irq.c
index eb88bd6e674e..b441a26b73b0 100644
--- a/arch/sparc64/kernel/irq.c
+++ b/arch/sparc64/kernel/irq.c
@@ -1,6 +1,6 @@
1/* irq.c: UltraSparc IRQ handling/init/registry. 1/* irq.c: UltraSparc IRQ handling/init/registry.
2 * 2 *
3 * Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net) 3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) 4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) 5 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
6 */ 6 */
@@ -308,6 +308,7 @@ static void sun4u_irq_enable(unsigned int virt_irq)
308 IMAP_AID_SAFARI | IMAP_NID_SAFARI); 308 IMAP_AID_SAFARI | IMAP_NID_SAFARI);
309 val |= tid | IMAP_VALID; 309 val |= tid | IMAP_VALID;
310 upa_writeq(val, imap); 310 upa_writeq(val, imap);
311 upa_writeq(ICLR_IDLE, data->iclr);
311 } 312 }
312} 313}
313 314
diff --git a/arch/sparc64/kernel/isa.c b/arch/sparc64/kernel/isa.c
deleted file mode 100644
index b5f7b354084f..000000000000
--- a/arch/sparc64/kernel/isa.c
+++ /dev/null
@@ -1,190 +0,0 @@
1#include <linux/kernel.h>
2#include <linux/init.h>
3#include <linux/pci.h>
4#include <linux/slab.h>
5#include <asm/oplib.h>
6#include <asm/prom.h>
7#include <asm/of_device.h>
8#include <asm/isa.h>
9
10struct sparc_isa_bridge *isa_chain;
11
12static void __init fatal_err(const char *reason)
13{
14 prom_printf("ISA: fatal error, %s.\n", reason);
15}
16
17static void __init report_dev(struct sparc_isa_device *isa_dev, int child)
18{
19 if (child)
20 printk(" (%s)", isa_dev->prom_node->name);
21 else
22 printk(" [%s", isa_dev->prom_node->name);
23}
24
25static void __init isa_dev_get_resource(struct sparc_isa_device *isa_dev)
26{
27 struct of_device *op = of_find_device_by_node(isa_dev->prom_node);
28
29 memcpy(&isa_dev->resource, &op->resource[0], sizeof(struct resource));
30}
31
32static void __init isa_dev_get_irq(struct sparc_isa_device *isa_dev)
33{
34 struct of_device *op = of_find_device_by_node(isa_dev->prom_node);
35
36 if (!op || !op->num_irqs) {
37 isa_dev->irq = PCI_IRQ_NONE;
38 } else {
39 isa_dev->irq = op->irqs[0];
40 }
41}
42
43static void __init isa_fill_children(struct sparc_isa_device *parent_isa_dev)
44{
45 struct device_node *dp = parent_isa_dev->prom_node->child;
46
47 if (!dp)
48 return;
49
50 printk(" ->");
51 while (dp) {
52 struct sparc_isa_device *isa_dev;
53
54 isa_dev = kzalloc(sizeof(*isa_dev), GFP_KERNEL);
55 if (!isa_dev) {
56 fatal_err("cannot allocate child isa_dev");
57 prom_halt();
58 }
59
60 /* Link it in to parent. */
61 isa_dev->next = parent_isa_dev->child;
62 parent_isa_dev->child = isa_dev;
63
64 isa_dev->bus = parent_isa_dev->bus;
65 isa_dev->prom_node = dp;
66
67 isa_dev_get_resource(isa_dev);
68 isa_dev_get_irq(isa_dev);
69
70 report_dev(isa_dev, 1);
71
72 dp = dp->sibling;
73 }
74}
75
76static void __init isa_fill_devices(struct sparc_isa_bridge *isa_br)
77{
78 struct device_node *dp = isa_br->prom_node->child;
79
80 while (dp) {
81 struct sparc_isa_device *isa_dev;
82 struct dev_archdata *sd;
83
84 isa_dev = kzalloc(sizeof(*isa_dev), GFP_KERNEL);
85 if (!isa_dev) {
86 printk(KERN_DEBUG "ISA: cannot allocate isa_dev");
87 return;
88 }
89
90 sd = &isa_dev->ofdev.dev.archdata;
91 sd->prom_node = dp;
92 sd->op = &isa_dev->ofdev;
93 sd->iommu = isa_br->ofdev.dev.parent->archdata.iommu;
94 sd->stc = isa_br->ofdev.dev.parent->archdata.stc;
95
96 isa_dev->ofdev.node = dp;
97 isa_dev->ofdev.dev.parent = &isa_br->ofdev.dev;
98 isa_dev->ofdev.dev.bus = &isa_bus_type;
99 sprintf(isa_dev->ofdev.dev.bus_id, "isa[%08x]", dp->node);
100
101 /* Register with core */
102 if (of_device_register(&isa_dev->ofdev) != 0) {
103 printk(KERN_DEBUG "isa: device registration error for %s!\n",
104 dp->path_component_name);
105 kfree(isa_dev);
106 goto next_sibling;
107 }
108
109 /* Link it in. */
110 isa_dev->next = NULL;
111 if (isa_br->devices == NULL) {
112 isa_br->devices = isa_dev;
113 } else {
114 struct sparc_isa_device *tmp = isa_br->devices;
115
116 while (tmp->next)
117 tmp = tmp->next;
118
119 tmp->next = isa_dev;
120 }
121
122 isa_dev->bus = isa_br;
123 isa_dev->prom_node = dp;
124
125 isa_dev_get_resource(isa_dev);
126 isa_dev_get_irq(isa_dev);
127
128 report_dev(isa_dev, 0);
129
130 isa_fill_children(isa_dev);
131
132 printk("]");
133
134 next_sibling:
135 dp = dp->sibling;
136 }
137}
138
139void __init isa_init(void)
140{
141 struct pci_dev *pdev;
142 unsigned short vendor, device;
143 int index = 0;
144
145 vendor = PCI_VENDOR_ID_AL;
146 device = PCI_DEVICE_ID_AL_M1533;
147
148 pdev = NULL;
149 while ((pdev = pci_get_device(vendor, device, pdev)) != NULL) {
150 struct sparc_isa_bridge *isa_br;
151 struct device_node *dp;
152
153 dp = pci_device_to_OF_node(pdev);
154
155 isa_br = kzalloc(sizeof(*isa_br), GFP_KERNEL);
156 if (!isa_br) {
157 printk(KERN_DEBUG "isa: cannot allocate sparc_isa_bridge");
158 pci_dev_put(pdev);
159 return;
160 }
161
162 isa_br->ofdev.node = dp;
163 isa_br->ofdev.dev.parent = &pdev->dev;
164 isa_br->ofdev.dev.bus = &isa_bus_type;
165 sprintf(isa_br->ofdev.dev.bus_id, "isa%d", index);
166
167 /* Register with core */
168 if (of_device_register(&isa_br->ofdev) != 0) {
169 printk(KERN_DEBUG "isa: device registration error for %s!\n",
170 dp->path_component_name);
171 kfree(isa_br);
172 pci_dev_put(pdev);
173 return;
174 }
175
176 /* Link it in. */
177 isa_br->next = isa_chain;
178 isa_chain = isa_br;
179
180 isa_br->self = pdev;
181 isa_br->index = index++;
182 isa_br->prom_node = dp;
183
184 printk("isa%d:", isa_br->index);
185
186 isa_fill_devices(isa_br);
187
188 printk("\n");
189 }
190}
diff --git a/arch/sparc64/kernel/ivec.S b/arch/sparc64/kernel/ivec.S
new file mode 100644
index 000000000000..d29f92ebca5e
--- /dev/null
+++ b/arch/sparc64/kernel/ivec.S
@@ -0,0 +1,51 @@
1 /* The registers for cross calls will be:
2 *
3 * DATA 0: [low 32-bits] Address of function to call, jmp to this
4 * [high 32-bits] MMU Context Argument 0, place in %g5
5 * DATA 1: Address Argument 1, place in %g1
6 * DATA 2: Address Argument 2, place in %g7
7 *
8 * With this method we can do most of the cross-call tlb/cache
9 * flushing very quickly.
10 */
11 .align 32
12 .globl do_ivec
13 .type do_ivec,#function
14do_ivec:
15 mov 0x40, %g3
16 ldxa [%g3 + %g0] ASI_INTR_R, %g3
17 sethi %hi(KERNBASE), %g4
18 cmp %g3, %g4
19 bgeu,pn %xcc, do_ivec_xcall
20 srlx %g3, 32, %g5
21 stxa %g0, [%g0] ASI_INTR_RECEIVE
22 membar #Sync
23
24 sethi %hi(ivector_table_pa), %g2
25 ldx [%g2 + %lo(ivector_table_pa)], %g2
26 sllx %g3, 4, %g3
27 add %g2, %g3, %g3
28
29 TRAP_LOAD_IRQ_WORK_PA(%g6, %g1)
30
31 ldx [%g6], %g5
32 stxa %g5, [%g3] ASI_PHYS_USE_EC
33 stx %g3, [%g6]
34 wr %g0, 1 << PIL_DEVICE_IRQ, %set_softint
35 retry
36do_ivec_xcall:
37 mov 0x50, %g1
38 ldxa [%g1 + %g0] ASI_INTR_R, %g1
39 srl %g3, 0, %g3
40
41 mov 0x60, %g7
42 ldxa [%g7 + %g0] ASI_INTR_R, %g7
43 stxa %g0, [%g0] ASI_INTR_RECEIVE
44 membar #Sync
45 ba,pt %xcc, 1f
46 nop
47
48 .align 32
491: jmpl %g3, %g0
50 nop
51 .size do_ivec,.-do_ivec
diff --git a/arch/sparc64/kernel/kgdb.c b/arch/sparc64/kernel/kgdb.c
new file mode 100644
index 000000000000..fefbe6dc51be
--- /dev/null
+++ b/arch/sparc64/kernel/kgdb.c
@@ -0,0 +1,186 @@
1/* kgdb.c: KGDB support for 64-bit sparc.
2 *
3 * Copyright (C) 2008 David S. Miller <davem@davemloft.net>
4 */
5
6#include <linux/kgdb.h>
7#include <linux/kdebug.h>
8
9#include <asm/kdebug.h>
10#include <asm/ptrace.h>
11#include <asm/irq.h>
12
13void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
14{
15 struct reg_window *win;
16 int i;
17
18 gdb_regs[GDB_G0] = 0;
19 for (i = 0; i < 15; i++)
20 gdb_regs[GDB_G1 + i] = regs->u_regs[UREG_G1 + i];
21
22 win = (struct reg_window *) (regs->u_regs[UREG_FP] + STACK_BIAS);
23 for (i = 0; i < 8; i++)
24 gdb_regs[GDB_L0 + i] = win->locals[i];
25 for (i = 0; i < 8; i++)
26 gdb_regs[GDB_I0 + i] = win->ins[i];
27
28 for (i = GDB_F0; i <= GDB_F62; i++)
29 gdb_regs[i] = 0;
30
31 gdb_regs[GDB_PC] = regs->tpc;
32 gdb_regs[GDB_NPC] = regs->tnpc;
33 gdb_regs[GDB_STATE] = regs->tstate;
34 gdb_regs[GDB_FSR] = 0;
35 gdb_regs[GDB_FPRS] = 0;
36 gdb_regs[GDB_Y] = regs->y;
37}
38
39void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
40{
41 struct thread_info *t = task_thread_info(p);
42 extern unsigned int switch_to_pc;
43 extern unsigned int ret_from_syscall;
44 struct reg_window *win;
45 unsigned long pc, cwp;
46 int i;
47
48 for (i = GDB_G0; i < GDB_G6; i++)
49 gdb_regs[i] = 0;
50 gdb_regs[GDB_G6] = (unsigned long) t;
51 gdb_regs[GDB_G7] = (unsigned long) p;
52 for (i = GDB_O0; i < GDB_SP; i++)
53 gdb_regs[i] = 0;
54 gdb_regs[GDB_SP] = t->ksp;
55 gdb_regs[GDB_O7] = 0;
56
57 win = (struct reg_window *) (t->ksp + STACK_BIAS);
58 for (i = 0; i < 8; i++)
59 gdb_regs[GDB_L0 + i] = win->locals[i];
60 for (i = 0; i < 8; i++)
61 gdb_regs[GDB_I0 + i] = win->ins[i];
62
63 for (i = GDB_F0; i <= GDB_F62; i++)
64 gdb_regs[i] = 0;
65
66 if (t->new_child)
67 pc = (unsigned long) &ret_from_syscall;
68 else
69 pc = (unsigned long) &switch_to_pc;
70
71 gdb_regs[GDB_PC] = pc;
72 gdb_regs[GDB_NPC] = pc + 4;
73
74 cwp = __thread_flag_byte_ptr(t)[TI_FLAG_BYTE_CWP];
75
76 gdb_regs[GDB_STATE] = (TSTATE_PRIV | TSTATE_IE | cwp);
77 gdb_regs[GDB_FSR] = 0;
78 gdb_regs[GDB_FPRS] = 0;
79 gdb_regs[GDB_Y] = 0;
80}
81
82void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
83{
84 struct reg_window *win;
85 int i;
86
87 for (i = 0; i < 15; i++)
88 regs->u_regs[UREG_G1 + i] = gdb_regs[GDB_G1 + i];
89
90 /* If the TSTATE register is changing, we have to preserve
91 * the CWP field, otherwise window save/restore explodes.
92 */
93 if (regs->tstate != gdb_regs[GDB_STATE]) {
94 unsigned long cwp = regs->tstate & TSTATE_CWP;
95
96 regs->tstate = (gdb_regs[GDB_STATE] & ~TSTATE_CWP) | cwp;
97 }
98
99 regs->tpc = gdb_regs[GDB_PC];
100 regs->tnpc = gdb_regs[GDB_NPC];
101 regs->y = gdb_regs[GDB_Y];
102
103 win = (struct reg_window *) (regs->u_regs[UREG_FP] + STACK_BIAS);
104 for (i = 0; i < 8; i++)
105 win->locals[i] = gdb_regs[GDB_L0 + i];
106 for (i = 0; i < 8; i++)
107 win->ins[i] = gdb_regs[GDB_I0 + i];
108}
109
110#ifdef CONFIG_SMP
111void smp_kgdb_capture_client(struct pt_regs *regs)
112{
113 unsigned long flags;
114
115 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
116 "wrpr %0, %1, %%pstate"
117 : "=r" (flags)
118 : "i" (PSTATE_IE));
119
120 flushw_all();
121
122 if (atomic_read(&kgdb_active) != -1)
123 kgdb_nmicallback(raw_smp_processor_id(), regs);
124
125 __asm__ __volatile__("wrpr %0, 0, %%pstate"
126 : : "r" (flags));
127}
128#endif
129
130int kgdb_arch_handle_exception(int e_vector, int signo, int err_code,
131 char *remcomInBuffer, char *remcomOutBuffer,
132 struct pt_regs *linux_regs)
133{
134 unsigned long addr;
135 char *ptr;
136
137 switch (remcomInBuffer[0]) {
138 case 'c':
139 /* try to read optional parameter, pc unchanged if no parm */
140 ptr = &remcomInBuffer[1];
141 if (kgdb_hex2long(&ptr, &addr)) {
142 linux_regs->tpc = addr;
143 linux_regs->tnpc = addr + 4;
144 }
145 /* fallthru */
146
147 case 'D':
148 case 'k':
149 if (linux_regs->tpc == (unsigned long) arch_kgdb_breakpoint) {
150 linux_regs->tpc = linux_regs->tnpc;
151 linux_regs->tnpc += 4;
152 }
153 return 0;
154 }
155 return -1;
156}
157
158asmlinkage void kgdb_trap(unsigned long trap_level, struct pt_regs *regs)
159{
160 unsigned long flags;
161
162 if (user_mode(regs)) {
163 bad_trap(regs, trap_level);
164 return;
165 }
166
167 flushw_all();
168
169 local_irq_save(flags);
170 kgdb_handle_exception(0x172, SIGTRAP, 0, regs);
171 local_irq_restore(flags);
172}
173
174int kgdb_arch_init(void)
175{
176 return 0;
177}
178
179void kgdb_arch_exit(void)
180{
181}
182
183struct kgdb_arch arch_kgdb_ops = {
184 /* Breakpoint instruction: ta 0x72 */
185 .gdb_bpt_instr = { 0x91, 0xd0, 0x20, 0x72 },
186};
diff --git a/arch/sparc64/kernel/mdesc.c b/arch/sparc64/kernel/mdesc.c
index 910083589569..dde52bcf5c64 100644
--- a/arch/sparc64/kernel/mdesc.c
+++ b/arch/sparc64/kernel/mdesc.c
@@ -1,10 +1,10 @@
1/* mdesc.c: Sun4V machine description handling. 1/* mdesc.c: Sun4V machine description handling.
2 * 2 *
3 * Copyright (C) 2007 David S. Miller <davem@davemloft.net> 3 * Copyright (C) 2007, 2008 David S. Miller <davem@davemloft.net>
4 */ 4 */
5#include <linux/kernel.h> 5#include <linux/kernel.h>
6#include <linux/types.h> 6#include <linux/types.h>
7#include <linux/bootmem.h> 7#include <linux/lmb.h>
8#include <linux/log2.h> 8#include <linux/log2.h>
9#include <linux/list.h> 9#include <linux/list.h>
10#include <linux/slab.h> 10#include <linux/slab.h>
@@ -84,24 +84,28 @@ static void mdesc_handle_init(struct mdesc_handle *hp,
84 hp->handle_size = handle_size; 84 hp->handle_size = handle_size;
85} 85}
86 86
87static struct mdesc_handle * __init mdesc_bootmem_alloc(unsigned int mdesc_size) 87static struct mdesc_handle * __init mdesc_lmb_alloc(unsigned int mdesc_size)
88{ 88{
89 struct mdesc_handle *hp;
90 unsigned int handle_size, alloc_size; 89 unsigned int handle_size, alloc_size;
90 struct mdesc_handle *hp;
91 unsigned long paddr;
91 92
92 handle_size = (sizeof(struct mdesc_handle) - 93 handle_size = (sizeof(struct mdesc_handle) -
93 sizeof(struct mdesc_hdr) + 94 sizeof(struct mdesc_hdr) +
94 mdesc_size); 95 mdesc_size);
95 alloc_size = PAGE_ALIGN(handle_size); 96 alloc_size = PAGE_ALIGN(handle_size);
96 97
97 hp = __alloc_bootmem(alloc_size, PAGE_SIZE, 0UL); 98 paddr = lmb_alloc(alloc_size, PAGE_SIZE);
98 if (hp)
99 mdesc_handle_init(hp, handle_size, hp);
100 99
100 hp = NULL;
101 if (paddr) {
102 hp = __va(paddr);
103 mdesc_handle_init(hp, handle_size, hp);
104 }
101 return hp; 105 return hp;
102} 106}
103 107
104static void mdesc_bootmem_free(struct mdesc_handle *hp) 108static void mdesc_lmb_free(struct mdesc_handle *hp)
105{ 109{
106 unsigned int alloc_size, handle_size = hp->handle_size; 110 unsigned int alloc_size, handle_size = hp->handle_size;
107 unsigned long start, end; 111 unsigned long start, end;
@@ -124,9 +128,9 @@ static void mdesc_bootmem_free(struct mdesc_handle *hp)
124 } 128 }
125} 129}
126 130
127static struct mdesc_mem_ops bootmem_mdesc_ops = { 131static struct mdesc_mem_ops lmb_mdesc_ops = {
128 .alloc = mdesc_bootmem_alloc, 132 .alloc = mdesc_lmb_alloc,
129 .free = mdesc_bootmem_free, 133 .free = mdesc_lmb_free,
130}; 134};
131 135
132static struct mdesc_handle *mdesc_kmalloc(unsigned int mdesc_size) 136static struct mdesc_handle *mdesc_kmalloc(unsigned int mdesc_size)
@@ -888,7 +892,7 @@ void __init sun4v_mdesc_init(void)
888 892
889 printk("MDESC: Size is %lu bytes.\n", len); 893 printk("MDESC: Size is %lu bytes.\n", len);
890 894
891 hp = mdesc_alloc(len, &bootmem_mdesc_ops); 895 hp = mdesc_alloc(len, &lmb_mdesc_ops);
892 if (hp == NULL) { 896 if (hp == NULL) {
893 prom_printf("MDESC: alloc of %lu bytes failed.\n", len); 897 prom_printf("MDESC: alloc of %lu bytes failed.\n", len);
894 prom_halt(); 898 prom_halt();
diff --git a/arch/sparc64/kernel/misctrap.S b/arch/sparc64/kernel/misctrap.S
new file mode 100644
index 000000000000..753b4f031bfb
--- /dev/null
+++ b/arch/sparc64/kernel/misctrap.S
@@ -0,0 +1,97 @@
1#ifdef CONFIG_KGDB
2 .globl arch_kgdb_breakpoint
3 .type arch_kgdb_breakpoint,#function
4arch_kgdb_breakpoint:
5 ta 0x72
6 retl
7 nop
8 .size arch_kgdb_breakpoint,.-arch_kgdb_breakpoint
9#endif
10
11 .type __do_privact,#function
12__do_privact:
13 mov TLB_SFSR, %g3
14 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
15 membar #Sync
16 sethi %hi(109f), %g7
17 ba,pt %xcc, etrap
18109: or %g7, %lo(109b), %g7
19 call do_privact
20 add %sp, PTREGS_OFF, %o0
21 ba,pt %xcc, rtrap
22 nop
23 .size __do_privact,.-__do_privact
24
25 .type do_mna,#function
26do_mna:
27 rdpr %tl, %g3
28 cmp %g3, 1
29
30 /* Setup %g4/%g5 now as they are used in the
31 * winfixup code.
32 */
33 mov TLB_SFSR, %g3
34 mov DMMU_SFAR, %g4
35 ldxa [%g4] ASI_DMMU, %g4
36 ldxa [%g3] ASI_DMMU, %g5
37 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
38 membar #Sync
39 bgu,pn %icc, winfix_mna
40 rdpr %tpc, %g3
41
421: sethi %hi(109f), %g7
43 ba,pt %xcc, etrap
44109: or %g7, %lo(109b), %g7
45 mov %l4, %o1
46 mov %l5, %o2
47 call mem_address_unaligned
48 add %sp, PTREGS_OFF, %o0
49 ba,pt %xcc, rtrap
50 nop
51 .size do_mna,.-do_mna
52
53 .type do_lddfmna,#function
54do_lddfmna:
55 sethi %hi(109f), %g7
56 mov TLB_SFSR, %g4
57 ldxa [%g4] ASI_DMMU, %g5
58 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
59 membar #Sync
60 mov DMMU_SFAR, %g4
61 ldxa [%g4] ASI_DMMU, %g4
62 ba,pt %xcc, etrap
63109: or %g7, %lo(109b), %g7
64 mov %l4, %o1
65 mov %l5, %o2
66 call handle_lddfmna
67 add %sp, PTREGS_OFF, %o0
68 ba,pt %xcc, rtrap
69 nop
70 .size do_lddfmna,.-do_lddfmna
71
72 .type do_stdfmna,#function
73do_stdfmna:
74 sethi %hi(109f), %g7
75 mov TLB_SFSR, %g4
76 ldxa [%g4] ASI_DMMU, %g5
77 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
78 membar #Sync
79 mov DMMU_SFAR, %g4
80 ldxa [%g4] ASI_DMMU, %g4
81 ba,pt %xcc, etrap
82109: or %g7, %lo(109b), %g7
83 mov %l4, %o1
84 mov %l5, %o2
85 call handle_stdfmna
86 add %sp, PTREGS_OFF, %o0
87 ba,pt %xcc, rtrap
88 nop
89 .size do_stdfmna,.-do_stdfmna
90
91 .type breakpoint_trap,#function
92breakpoint_trap:
93 call sparc_breakpoint
94 add %sp, PTREGS_OFF, %o0
95 ba,pt %xcc, rtrap
96 nop
97 .size breakpoint_trap,.-breakpoint_trap
diff --git a/arch/sparc64/kernel/of_device.c b/arch/sparc64/kernel/of_device.c
index 0fd9db95b896..d569f60c24b8 100644
--- a/arch/sparc64/kernel/of_device.c
+++ b/arch/sparc64/kernel/of_device.c
@@ -6,6 +6,7 @@
6#include <linux/mod_devicetable.h> 6#include <linux/mod_devicetable.h>
7#include <linux/slab.h> 7#include <linux/slab.h>
8#include <linux/errno.h> 8#include <linux/errno.h>
9#include <linux/irq.h>
9#include <linux/of_device.h> 10#include <linux/of_device.h>
10#include <linux/of_platform.h> 11#include <linux/of_platform.h>
11 12
@@ -411,12 +412,6 @@ static int __init build_one_resource(struct device_node *parent,
411 412
412static int __init use_1to1_mapping(struct device_node *pp) 413static int __init use_1to1_mapping(struct device_node *pp)
413{ 414{
414 /* If this is on the PMU bus, don't try to translate it even
415 * if a ranges property exists.
416 */
417 if (!strcmp(pp->name, "pmu"))
418 return 1;
419
420 /* If we have a ranges property in the parent, use it. */ 415 /* If we have a ranges property in the parent, use it. */
421 if (of_find_property(pp, "ranges", NULL) != NULL) 416 if (of_find_property(pp, "ranges", NULL) != NULL)
422 return 0; 417 return 0;
@@ -660,6 +655,7 @@ static unsigned int __init build_one_device_irq(struct of_device *op,
660 struct device_node *dp = op->node; 655 struct device_node *dp = op->node;
661 struct device_node *pp, *ip; 656 struct device_node *pp, *ip;
662 unsigned int orig_irq = irq; 657 unsigned int orig_irq = irq;
658 int nid;
663 659
664 if (irq == 0xffffffff) 660 if (irq == 0xffffffff)
665 return irq; 661 return irq;
@@ -672,7 +668,7 @@ static unsigned int __init build_one_device_irq(struct of_device *op,
672 printk("%s: direct translate %x --> %x\n", 668 printk("%s: direct translate %x --> %x\n",
673 dp->full_name, orig_irq, irq); 669 dp->full_name, orig_irq, irq);
674 670
675 return irq; 671 goto out;
676 } 672 }
677 673
678 /* Something more complicated. Walk up to the root, applying 674 /* Something more complicated. Walk up to the root, applying
@@ -744,6 +740,14 @@ static unsigned int __init build_one_device_irq(struct of_device *op,
744 printk("%s: Apply IRQ trans [%s] %x --> %x\n", 740 printk("%s: Apply IRQ trans [%s] %x --> %x\n",
745 op->node->full_name, ip->full_name, orig_irq, irq); 741 op->node->full_name, ip->full_name, orig_irq, irq);
746 742
743out:
744 nid = of_node_to_nid(dp);
745 if (nid != -1) {
746 cpumask_t numa_mask = node_to_cpumask(nid);
747
748 irq_set_affinity(irq, numa_mask);
749 }
750
747 return irq; 751 return irq;
748} 752}
749 753
diff --git a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c
index 545356b00e2e..112b09f16f36 100644
--- a/arch/sparc64/kernel/pci.c
+++ b/arch/sparc64/kernel/pci.c
@@ -23,7 +23,6 @@
23#include <asm/pgtable.h> 23#include <asm/pgtable.h>
24#include <asm/irq.h> 24#include <asm/irq.h>
25#include <asm/ebus.h> 25#include <asm/ebus.h>
26#include <asm/isa.h>
27#include <asm/prom.h> 26#include <asm/prom.h>
28#include <asm/apb.h> 27#include <asm/apb.h>
29 28
@@ -351,8 +350,7 @@ static void pci_parse_of_addrs(struct of_device *op,
351 350
352struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, 351struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
353 struct device_node *node, 352 struct device_node *node,
354 struct pci_bus *bus, int devfn, 353 struct pci_bus *bus, int devfn)
355 int host_controller)
356{ 354{
357 struct dev_archdata *sd; 355 struct dev_archdata *sd;
358 struct pci_dev *dev; 356 struct pci_dev *dev;
@@ -369,10 +367,12 @@ struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
369 sd->host_controller = pbm; 367 sd->host_controller = pbm;
370 sd->prom_node = node; 368 sd->prom_node = node;
371 sd->op = of_find_device_by_node(node); 369 sd->op = of_find_device_by_node(node);
370 sd->numa_node = pbm->numa_node;
372 371
373 sd = &sd->op->dev.archdata; 372 sd = &sd->op->dev.archdata;
374 sd->iommu = pbm->iommu; 373 sd->iommu = pbm->iommu;
375 sd->stc = &pbm->stc; 374 sd->stc = &pbm->stc;
375 sd->numa_node = pbm->numa_node;
376 376
377 type = of_get_property(node, "device_type", NULL); 377 type = of_get_property(node, "device_type", NULL);
378 if (type == NULL) 378 if (type == NULL)
@@ -389,43 +389,28 @@ struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
389 dev->devfn = devfn; 389 dev->devfn = devfn;
390 dev->multifunction = 0; /* maybe a lie? */ 390 dev->multifunction = 0; /* maybe a lie? */
391 391
392 if (host_controller) { 392 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
393 if (tlb_type != hypervisor) { 393 dev->device = of_getintprop_default(node, "device-id", 0xffff);
394 pci_read_config_word(dev, PCI_VENDOR_ID, 394 dev->subsystem_vendor =
395 &dev->vendor); 395 of_getintprop_default(node, "subsystem-vendor-id", 0);
396 pci_read_config_word(dev, PCI_DEVICE_ID, 396 dev->subsystem_device =
397 &dev->device); 397 of_getintprop_default(node, "subsystem-id", 0);
398 } else { 398
399 dev->vendor = PCI_VENDOR_ID_SUN; 399 dev->cfg_size = pci_cfg_space_size(dev);
400 dev->device = 0x80f0; 400
401 } 401 /* We can't actually use the firmware value, we have
402 dev->cfg_size = 256; 402 * to read what is in the register right now. One
403 dev->class = PCI_CLASS_BRIDGE_HOST << 8; 403 * reason is that in the case of IDE interfaces the
404 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), 404 * firmware can sample the value before the the IDE
405 0x00, PCI_SLOT(devfn), PCI_FUNC(devfn)); 405 * interface is programmed into native mode.
406 } else { 406 */
407 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff); 407 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
408 dev->device = of_getintprop_default(node, "device-id", 0xffff); 408 dev->class = class >> 8;
409 dev->subsystem_vendor = 409 dev->revision = class & 0xff;
410 of_getintprop_default(node, "subsystem-vendor-id", 0); 410
411 dev->subsystem_device = 411 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
412 of_getintprop_default(node, "subsystem-id", 0); 412 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
413
414 dev->cfg_size = pci_cfg_space_size(dev);
415
416 /* We can't actually use the firmware value, we have
417 * to read what is in the register right now. One
418 * reason is that in the case of IDE interfaces the
419 * firmware can sample the value before the the IDE
420 * interface is programmed into native mode.
421 */
422 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
423 dev->class = class >> 8;
424 dev->revision = class & 0xff;
425 413
426 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
427 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
428 }
429 if (ofpci_verbose) 414 if (ofpci_verbose)
430 printk(" class: 0x%x device name: %s\n", 415 printk(" class: 0x%x device name: %s\n",
431 dev->class, pci_name(dev)); 416 dev->class, pci_name(dev));
@@ -440,26 +425,21 @@ struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
440 dev->current_state = 4; /* unknown power state */ 425 dev->current_state = 4; /* unknown power state */
441 dev->error_state = pci_channel_io_normal; 426 dev->error_state = pci_channel_io_normal;
442 427
443 if (host_controller) { 428 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
429 /* a PCI-PCI bridge */
444 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; 430 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
445 dev->rom_base_reg = PCI_ROM_ADDRESS1; 431 dev->rom_base_reg = PCI_ROM_ADDRESS1;
446 dev->irq = PCI_IRQ_NONE; 432 } else if (!strcmp(type, "cardbus")) {
433 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
447 } else { 434 } else {
448 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) { 435 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
449 /* a PCI-PCI bridge */ 436 dev->rom_base_reg = PCI_ROM_ADDRESS;
450 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
451 dev->rom_base_reg = PCI_ROM_ADDRESS1;
452 } else if (!strcmp(type, "cardbus")) {
453 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
454 } else {
455 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
456 dev->rom_base_reg = PCI_ROM_ADDRESS;
457 437
458 dev->irq = sd->op->irqs[0]; 438 dev->irq = sd->op->irqs[0];
459 if (dev->irq == 0xffffffff) 439 if (dev->irq == 0xffffffff)
460 dev->irq = PCI_IRQ_NONE; 440 dev->irq = PCI_IRQ_NONE;
461 }
462 } 441 }
442
463 pci_parse_of_addrs(sd->op, node, dev); 443 pci_parse_of_addrs(sd->op, node, dev);
464 444
465 if (ofpci_verbose) 445 if (ofpci_verbose)
@@ -748,7 +728,7 @@ static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
748 prev_devfn = devfn; 728 prev_devfn = devfn;
749 729
750 /* create a new pci_dev for this device */ 730 /* create a new pci_dev for this device */
751 dev = of_create_pci_dev(pbm, child, bus, devfn, 0); 731 dev = of_create_pci_dev(pbm, child, bus, devfn);
752 if (!dev) 732 if (!dev)
753 continue; 733 continue;
754 if (ofpci_verbose) 734 if (ofpci_verbose)
@@ -795,48 +775,9 @@ static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
795 pci_bus_register_of_sysfs(child_bus); 775 pci_bus_register_of_sysfs(child_bus);
796} 776}
797 777
798int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev,
799 unsigned int devfn,
800 int where, int size,
801 u32 *value)
802{
803 static u8 fake_pci_config[] = {
804 0x8e, 0x10, /* Vendor: 0x108e (Sun) */
805 0xf0, 0x80, /* Device: 0x80f0 (Fire) */
806 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */
807 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */
808 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */
809 0x00, /* Cacheline: 0x00 */
810 0x40, /* Latency: 0x40 */
811 0x00, /* Header-Type: 0x00 normal */
812 };
813
814 *value = 0;
815 if (where >= 0 && where < sizeof(fake_pci_config) &&
816 (where + size) >= 0 &&
817 (where + size) < sizeof(fake_pci_config) &&
818 size <= sizeof(u32)) {
819 while (size--) {
820 *value <<= 8;
821 *value |= fake_pci_config[where + size];
822 }
823 }
824
825 return PCIBIOS_SUCCESSFUL;
826}
827
828int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
829 unsigned int devfn,
830 int where, int size,
831 u32 value)
832{
833 return PCIBIOS_SUCCESSFUL;
834}
835
836struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm) 778struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
837{ 779{
838 struct device_node *node = pbm->prom_node; 780 struct device_node *node = pbm->prom_node;
839 struct pci_dev *host_pdev;
840 struct pci_bus *bus; 781 struct pci_bus *bus;
841 782
842 printk("PCI: Scanning PBM %s\n", node->full_name); 783 printk("PCI: Scanning PBM %s\n", node->full_name);
@@ -854,10 +795,6 @@ struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
854 bus->resource[0] = &pbm->io_space; 795 bus->resource[0] = &pbm->io_space;
855 bus->resource[1] = &pbm->mem_space; 796 bus->resource[1] = &pbm->mem_space;
856 797
857 /* Create the dummy host bridge and link it in. */
858 host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1);
859 bus->self = host_pdev;
860
861 pci_of_scan_bus(pbm, node, bus); 798 pci_of_scan_bus(pbm, node, bus);
862 pci_bus_add_devices(bus); 799 pci_bus_add_devices(bus);
863 pci_bus_register_of_sysfs(bus); 800 pci_bus_register_of_sysfs(bus);
@@ -883,7 +820,6 @@ static int __init pcibios_init(void)
883 820
884 pci_scan_each_controller_bus(); 821 pci_scan_each_controller_bus();
885 822
886 isa_init();
887 ebus_init(); 823 ebus_init();
888 power_init(); 824 power_init();
889 825
@@ -1159,6 +1095,16 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1159 return 0; 1095 return 0;
1160} 1096}
1161 1097
1098#ifdef CONFIG_NUMA
1099int pcibus_to_node(struct pci_bus *pbus)
1100{
1101 struct pci_pbm_info *pbm = pbus->sysdata;
1102
1103 return pbm->numa_node;
1104}
1105EXPORT_SYMBOL(pcibus_to_node);
1106#endif
1107
1162/* Return the domain nuber for this pci bus */ 1108/* Return the domain nuber for this pci bus */
1163 1109
1164int pci_domain_nr(struct pci_bus *pbus) 1110int pci_domain_nr(struct pci_bus *pbus)
diff --git a/arch/sparc64/kernel/pci_common.c b/arch/sparc64/kernel/pci_common.c
index 923e0bcc3bfd..19fa621d6a60 100644
--- a/arch/sparc64/kernel/pci_common.c
+++ b/arch/sparc64/kernel/pci_common.c
@@ -264,9 +264,6 @@ static int sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
264 unsigned int func = PCI_FUNC(devfn); 264 unsigned int func = PCI_FUNC(devfn);
265 unsigned long ret; 265 unsigned long ret;
266 266
267 if (!bus && devfn == 0x00)
268 return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
269 size, value);
270 if (config_out_of_range(pbm, bus, devfn, where)) { 267 if (config_out_of_range(pbm, bus, devfn, where)) {
271 ret = ~0UL; 268 ret = ~0UL;
272 } else { 269 } else {
@@ -300,9 +297,6 @@ static int sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
300 unsigned int func = PCI_FUNC(devfn); 297 unsigned int func = PCI_FUNC(devfn);
301 unsigned long ret; 298 unsigned long ret;
302 299
303 if (!bus && devfn == 0x00)
304 return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
305 size, value);
306 if (config_out_of_range(pbm, bus, devfn, where)) { 300 if (config_out_of_range(pbm, bus, devfn, where)) {
307 /* Do nothing. */ 301 /* Do nothing. */
308 } else { 302 } else {
diff --git a/arch/sparc64/kernel/pci_fire.c b/arch/sparc64/kernel/pci_fire.c
index 7571ed563147..d23bb6f53cda 100644
--- a/arch/sparc64/kernel/pci_fire.c
+++ b/arch/sparc64/kernel/pci_fire.c
@@ -71,7 +71,8 @@ static int pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
71 */ 71 */
72 fire_write(iommu->iommu_flushinv, ~(u64)0); 72 fire_write(iommu->iommu_flushinv, ~(u64)0);
73 73
74 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask); 74 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
75 pbm->numa_node);
75 if (err) 76 if (err)
76 return err; 77 return err;
77 78
@@ -449,6 +450,8 @@ static int __init pci_fire_pbm_init(struct pci_controller_info *p,
449 pbm->next = pci_pbm_root; 450 pbm->next = pci_pbm_root;
450 pci_pbm_root = pbm; 451 pci_pbm_root = pbm;
451 452
453 pbm->numa_node = -1;
454
452 pbm->scan_bus = pci_fire_scan_bus; 455 pbm->scan_bus = pci_fire_scan_bus;
453 pbm->pci_ops = &sun4u_pci_ops; 456 pbm->pci_ops = &sun4u_pci_ops;
454 pbm->config_space_reg_bits = 12; 457 pbm->config_space_reg_bits = 12;
diff --git a/arch/sparc64/kernel/pci_impl.h b/arch/sparc64/kernel/pci_impl.h
index 4a50da13ce48..c385d126be11 100644
--- a/arch/sparc64/kernel/pci_impl.h
+++ b/arch/sparc64/kernel/pci_impl.h
@@ -148,6 +148,8 @@ struct pci_pbm_info {
148 struct pci_bus *pci_bus; 148 struct pci_bus *pci_bus;
149 void (*scan_bus)(struct pci_pbm_info *); 149 void (*scan_bus)(struct pci_pbm_info *);
150 struct pci_ops *pci_ops; 150 struct pci_ops *pci_ops;
151
152 int numa_node;
151}; 153};
152 154
153struct pci_controller_info { 155struct pci_controller_info {
@@ -161,21 +163,10 @@ extern struct pci_pbm_info *pci_pbm_root;
161extern int pci_num_pbms; 163extern int pci_num_pbms;
162 164
163/* PCI bus scanning and fixup support. */ 165/* PCI bus scanning and fixup support. */
164extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize,
165 u32 dma_offset, u32 dma_addr_mask);
166extern void pci_get_pbm_props(struct pci_pbm_info *pbm); 166extern void pci_get_pbm_props(struct pci_pbm_info *pbm);
167extern struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm); 167extern struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm);
168extern void pci_determine_mem_io_space(struct pci_pbm_info *pbm); 168extern void pci_determine_mem_io_space(struct pci_pbm_info *pbm);
169 169
170extern int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev,
171 unsigned int devfn,
172 int where, int size,
173 u32 *value);
174extern int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
175 unsigned int devfn,
176 int where, int size,
177 u32 value);
178
179/* Error reporting support. */ 170/* Error reporting support. */
180extern void pci_scan_for_target_abort(struct pci_pbm_info *, struct pci_bus *); 171extern void pci_scan_for_target_abort(struct pci_pbm_info *, struct pci_bus *);
181extern void pci_scan_for_master_abort(struct pci_pbm_info *, struct pci_bus *); 172extern void pci_scan_for_master_abort(struct pci_pbm_info *, struct pci_bus *);
diff --git a/arch/sparc64/kernel/pci_msi.c b/arch/sparc64/kernel/pci_msi.c
index d6d64b44af63..db5e8fd8f674 100644
--- a/arch/sparc64/kernel/pci_msi.c
+++ b/arch/sparc64/kernel/pci_msi.c
@@ -279,11 +279,17 @@ static int bringup_one_msi_queue(struct pci_pbm_info *pbm,
279 unsigned long devino) 279 unsigned long devino)
280{ 280{
281 int irq = ops->msiq_build_irq(pbm, msiqid, devino); 281 int irq = ops->msiq_build_irq(pbm, msiqid, devino);
282 int err; 282 int err, nid;
283 283
284 if (irq < 0) 284 if (irq < 0)
285 return irq; 285 return irq;
286 286
287 nid = pbm->numa_node;
288 if (nid != -1) {
289 cpumask_t numa_mask = node_to_cpumask(nid);
290
291 irq_set_affinity(irq, numa_mask);
292 }
287 err = request_irq(irq, sparc64_msiq_interrupt, 0, 293 err = request_irq(irq, sparc64_msiq_interrupt, 0,
288 "MSIQ", 294 "MSIQ",
289 &pbm->msiq_irq_cookies[msiqid - pbm->msiq_first]); 295 &pbm->msiq_irq_cookies[msiqid - pbm->msiq_first]);
diff --git a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c
index 0bad96e5d184..994dbe0603da 100644
--- a/arch/sparc64/kernel/pci_psycho.c
+++ b/arch/sparc64/kernel/pci_psycho.c
@@ -848,7 +848,8 @@ static int psycho_iommu_init(struct pci_pbm_info *pbm)
848 /* Leave diag mode enabled for full-flushing done 848 /* Leave diag mode enabled for full-flushing done
849 * in pci_iommu.c 849 * in pci_iommu.c
850 */ 850 */
851 err = iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff); 851 err = iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff,
852 pbm->numa_node);
852 if (err) 853 if (err)
853 return err; 854 return err;
854 855
@@ -979,6 +980,8 @@ static void __init psycho_pbm_init(struct pci_controller_info *p,
979 pbm->next = pci_pbm_root; 980 pbm->next = pci_pbm_root;
980 pci_pbm_root = pbm; 981 pci_pbm_root = pbm;
981 982
983 pbm->numa_node = -1;
984
982 pbm->scan_bus = psycho_scan_bus; 985 pbm->scan_bus = psycho_scan_bus;
983 pbm->pci_ops = &sun4u_pci_ops; 986 pbm->pci_ops = &sun4u_pci_ops;
984 pbm->config_space_reg_bits = 8; 987 pbm->config_space_reg_bits = 8;
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
index 1c5f5fa2339f..4c34195baf37 100644
--- a/arch/sparc64/kernel/pci_sabre.c
+++ b/arch/sparc64/kernel/pci_sabre.c
@@ -704,7 +704,7 @@ static int sabre_iommu_init(struct pci_pbm_info *pbm,
704 * in pci_iommu.c 704 * in pci_iommu.c
705 */ 705 */
706 err = iommu_table_init(iommu, tsbsize * 1024 * 8, 706 err = iommu_table_init(iommu, tsbsize * 1024 * 8,
707 dvma_offset, dma_mask); 707 dvma_offset, dma_mask, pbm->numa_node);
708 if (err) 708 if (err)
709 return err; 709 return err;
710 710
@@ -737,6 +737,8 @@ static void __init sabre_pbm_init(struct pci_controller_info *p,
737 pbm->name = dp->full_name; 737 pbm->name = dp->full_name;
738 printk("%s: SABRE PCI Bus Module\n", pbm->name); 738 printk("%s: SABRE PCI Bus Module\n", pbm->name);
739 739
740 pbm->numa_node = -1;
741
740 pbm->scan_bus = sabre_scan_bus; 742 pbm->scan_bus = sabre_scan_bus;
741 pbm->pci_ops = &sun4u_pci_ops; 743 pbm->pci_ops = &sun4u_pci_ops;
742 pbm->config_space_reg_bits = 8; 744 pbm->config_space_reg_bits = 8;
diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c
index e30609362322..615edd9c8e2a 100644
--- a/arch/sparc64/kernel/pci_schizo.c
+++ b/arch/sparc64/kernel/pci_schizo.c
@@ -1220,7 +1220,8 @@ static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1220 /* Leave diag mode enabled for full-flushing done 1220 /* Leave diag mode enabled for full-flushing done
1221 * in pci_iommu.c 1221 * in pci_iommu.c
1222 */ 1222 */
1223 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask); 1223 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
1224 pbm->numa_node);
1224 if (err) 1225 if (err)
1225 return err; 1226 return err;
1226 1227
@@ -1379,6 +1380,8 @@ static int __init schizo_pbm_init(struct pci_controller_info *p,
1379 pbm->next = pci_pbm_root; 1380 pbm->next = pci_pbm_root;
1380 pci_pbm_root = pbm; 1381 pci_pbm_root = pbm;
1381 1382
1383 pbm->numa_node = -1;
1384
1382 pbm->scan_bus = schizo_scan_bus; 1385 pbm->scan_bus = schizo_scan_bus;
1383 pbm->pci_ops = &sun4u_pci_ops; 1386 pbm->pci_ops = &sun4u_pci_ops;
1384 pbm->config_space_reg_bits = 8; 1387 pbm->config_space_reg_bits = 8;
diff --git a/arch/sparc64/kernel/pci_sun4v.c b/arch/sparc64/kernel/pci_sun4v.c
index 01839706bd52..e2bb9790039c 100644
--- a/arch/sparc64/kernel/pci_sun4v.c
+++ b/arch/sparc64/kernel/pci_sun4v.c
@@ -127,10 +127,12 @@ static inline long iommu_batch_end(void)
127static void *dma_4v_alloc_coherent(struct device *dev, size_t size, 127static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
128 dma_addr_t *dma_addrp, gfp_t gfp) 128 dma_addr_t *dma_addrp, gfp_t gfp)
129{ 129{
130 struct iommu *iommu;
131 unsigned long flags, order, first_page, npages, n; 130 unsigned long flags, order, first_page, npages, n;
131 struct iommu *iommu;
132 struct page *page;
132 void *ret; 133 void *ret;
133 long entry; 134 long entry;
135 int nid;
134 136
135 size = IO_PAGE_ALIGN(size); 137 size = IO_PAGE_ALIGN(size);
136 order = get_order(size); 138 order = get_order(size);
@@ -139,10 +141,12 @@ static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
139 141
140 npages = size >> IO_PAGE_SHIFT; 142 npages = size >> IO_PAGE_SHIFT;
141 143
142 first_page = __get_free_pages(gfp, order); 144 nid = dev->archdata.numa_node;
143 if (unlikely(first_page == 0UL)) 145 page = alloc_pages_node(nid, gfp, order);
146 if (unlikely(!page))
144 return NULL; 147 return NULL;
145 148
149 first_page = (unsigned long) page_address(page);
146 memset((char *)first_page, 0, PAGE_SIZE << order); 150 memset((char *)first_page, 0, PAGE_SIZE << order);
147 151
148 iommu = dev->archdata.iommu; 152 iommu = dev->archdata.iommu;
@@ -899,6 +903,8 @@ static void __init pci_sun4v_pbm_init(struct pci_controller_info *p,
899 pbm->next = pci_pbm_root; 903 pbm->next = pci_pbm_root;
900 pci_pbm_root = pbm; 904 pci_pbm_root = pbm;
901 905
906 pbm->numa_node = of_node_to_nid(dp);
907
902 pbm->scan_bus = pci_sun4v_scan_bus; 908 pbm->scan_bus = pci_sun4v_scan_bus;
903 pbm->pci_ops = &sun4v_pci_ops; 909 pbm->pci_ops = &sun4v_pci_ops;
904 pbm->config_space_reg_bits = 12; 910 pbm->config_space_reg_bits = 12;
@@ -913,6 +919,7 @@ static void __init pci_sun4v_pbm_init(struct pci_controller_info *p,
913 pbm->name = dp->full_name; 919 pbm->name = dp->full_name;
914 920
915 printk("%s: SUN4V PCI Bus Module\n", pbm->name); 921 printk("%s: SUN4V PCI Bus Module\n", pbm->name);
922 printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node);
916 923
917 pci_determine_mem_io_space(pbm); 924 pci_determine_mem_io_space(pbm);
918 925
diff --git a/arch/sparc64/kernel/process.c b/arch/sparc64/kernel/process.c
index acf8c5250aa9..500ac6d483a0 100644
--- a/arch/sparc64/kernel/process.c
+++ b/arch/sparc64/kernel/process.c
@@ -1,5 +1,4 @@
1/* $Id: process.c,v 1.131 2002/02/09 19:49:30 davem Exp $ 1/* arch/sparc64/kernel/process.c
2 * arch/sparc64/kernel/process.c
3 * 2 *
4 * Copyright (C) 1995, 1996 David S. Miller (davem@caip.rutgers.edu) 3 * Copyright (C) 1995, 1996 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be) 4 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
@@ -368,9 +367,6 @@ void flush_thread(void)
368 367
369 if (get_thread_current_ds() != ASI_AIUS) 368 if (get_thread_current_ds() != ASI_AIUS)
370 set_fs(USER_DS); 369 set_fs(USER_DS);
371
372 /* Init new signal delivery disposition. */
373 clear_thread_flag(TIF_NEWSIGNALS);
374} 370}
375 371
376/* It's a bit more tricky when 64-bit tasks are involved... */ 372/* It's a bit more tricky when 64-bit tasks are involved... */
diff --git a/arch/sparc64/kernel/prom.c b/arch/sparc64/kernel/prom.c
index 68964ddcde1e..ed03a18d3b36 100644
--- a/arch/sparc64/kernel/prom.c
+++ b/arch/sparc64/kernel/prom.c
@@ -19,8 +19,8 @@
19#include <linux/types.h> 19#include <linux/types.h>
20#include <linux/string.h> 20#include <linux/string.h>
21#include <linux/mm.h> 21#include <linux/mm.h>
22#include <linux/bootmem.h>
23#include <linux/module.h> 22#include <linux/module.h>
23#include <linux/lmb.h>
24 24
25#include <asm/prom.h> 25#include <asm/prom.h>
26#include <asm/of_device.h> 26#include <asm/of_device.h>
@@ -122,16 +122,20 @@ int of_find_in_proplist(const char *list, const char *match, int len)
122} 122}
123EXPORT_SYMBOL(of_find_in_proplist); 123EXPORT_SYMBOL(of_find_in_proplist);
124 124
125static unsigned int prom_early_allocated; 125static unsigned int prom_early_allocated __initdata;
126 126
127static void * __init prom_early_alloc(unsigned long size) 127static void * __init prom_early_alloc(unsigned long size)
128{ 128{
129 unsigned long paddr = lmb_alloc(size, SMP_CACHE_BYTES);
129 void *ret; 130 void *ret;
130 131
131 ret = __alloc_bootmem(size, SMP_CACHE_BYTES, 0UL); 132 if (!paddr) {
132 if (ret != NULL) 133 prom_printf("prom_early_alloc(%lu) failed\n");
133 memset(ret, 0, size); 134 prom_halt();
135 }
134 136
137 ret = __va(paddr);
138 memset(ret, 0, size);
135 prom_early_allocated += size; 139 prom_early_allocated += size;
136 140
137 return ret; 141 return ret;
diff --git a/arch/sparc64/kernel/rtrap.S b/arch/sparc64/kernel/rtrap.S
index 079d18a11d24..ecf6753b204a 100644
--- a/arch/sparc64/kernel/rtrap.S
+++ b/arch/sparc64/kernel/rtrap.S
@@ -18,12 +18,6 @@
18#define RTRAP_PSTATE_IRQOFF (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV) 18#define RTRAP_PSTATE_IRQOFF (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV)
19#define RTRAP_PSTATE_AG_IRQOFF (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG) 19#define RTRAP_PSTATE_AG_IRQOFF (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)
20 20
21 /* Register %l6 keeps track of whether we are returning
22 * from a system call or not. It is cleared if we call
23 * do_notify_resume, and it must not be otherwise modified
24 * until we fully commit to returning to userspace.
25 */
26
27 .text 21 .text
28 .align 32 22 .align 32
29__handle_softirq: 23__handle_softirq:
@@ -56,14 +50,12 @@ __handle_user_windows:
56 be,pt %xcc, __handle_user_windows_continue 50 be,pt %xcc, __handle_user_windows_continue
57 nop 51 nop
58 mov %l5, %o1 52 mov %l5, %o1
59 mov %l6, %o2
60 add %sp, PTREGS_OFF, %o0 53 add %sp, PTREGS_OFF, %o0
61 mov %l0, %o3 54 mov %l0, %o2
62 55
63 call do_notify_resume 56 call do_notify_resume
64 wrpr %g0, RTRAP_PSTATE, %pstate 57 wrpr %g0, RTRAP_PSTATE, %pstate
65 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate 58 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
66 clr %l6
67 /* Signal delivery can modify pt_regs tstate, so we must 59 /* Signal delivery can modify pt_regs tstate, so we must
68 * reload it. 60 * reload it.
69 */ 61 */
@@ -99,14 +91,12 @@ __handle_perfctrs:
99 be,pt %xcc, __handle_perfctrs_continue 91 be,pt %xcc, __handle_perfctrs_continue
100 sethi %hi(TSTATE_PEF), %o0 92 sethi %hi(TSTATE_PEF), %o0
101 mov %l5, %o1 93 mov %l5, %o1
102 mov %l6, %o2
103 add %sp, PTREGS_OFF, %o0 94 add %sp, PTREGS_OFF, %o0
104 mov %l0, %o3 95 mov %l0, %o2
105 call do_notify_resume 96 call do_notify_resume
106 97
107 wrpr %g0, RTRAP_PSTATE, %pstate 98 wrpr %g0, RTRAP_PSTATE, %pstate
108 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate 99 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
109 clr %l6
110 /* Signal delivery can modify pt_regs tstate, so we must 100 /* Signal delivery can modify pt_regs tstate, so we must
111 * reload it. 101 * reload it.
112 */ 102 */
@@ -127,13 +117,11 @@ __handle_userfpu:
127 117
128__handle_signal: 118__handle_signal:
129 mov %l5, %o1 119 mov %l5, %o1
130 mov %l6, %o2
131 add %sp, PTREGS_OFF, %o0 120 add %sp, PTREGS_OFF, %o0
132 mov %l0, %o3 121 mov %l0, %o2
133 call do_notify_resume 122 call do_notify_resume
134 wrpr %g0, RTRAP_PSTATE, %pstate 123 wrpr %g0, RTRAP_PSTATE, %pstate
135 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate 124 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
136 clr %l6
137 125
138 /* Signal delivery can modify pt_regs tstate, so we must 126 /* Signal delivery can modify pt_regs tstate, so we must
139 * reload it. 127 * reload it.
@@ -145,9 +133,8 @@ __handle_signal:
145 andn %l1, %l4, %l1 133 andn %l1, %l4, %l1
146 134
147 .align 64 135 .align 64
148 .globl rtrap_irq, rtrap_clr_l6, rtrap, irqsz_patchme, rtrap_xcall 136 .globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
149rtrap_irq: 137rtrap_irq:
150rtrap_clr_l6: clr %l6
151rtrap: 138rtrap:
152#ifndef CONFIG_SMP 139#ifndef CONFIG_SMP
153 sethi %hi(per_cpu____cpu_data), %l0 140 sethi %hi(per_cpu____cpu_data), %l0
diff --git a/arch/sparc64/kernel/sbus.c b/arch/sparc64/kernel/sbus.c
index d1fb13ba02b5..fa2827c4a3ad 100644
--- a/arch/sparc64/kernel/sbus.c
+++ b/arch/sparc64/kernel/sbus.c
@@ -544,6 +544,7 @@ static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus)
544 544
545 sbus->ofdev.dev.archdata.iommu = iommu; 545 sbus->ofdev.dev.archdata.iommu = iommu;
546 sbus->ofdev.dev.archdata.stc = strbuf; 546 sbus->ofdev.dev.archdata.stc = strbuf;
547 sbus->ofdev.dev.archdata.numa_node = -1;
547 548
548 reg_base = regs + SYSIO_IOMMUREG_BASE; 549 reg_base = regs + SYSIO_IOMMUREG_BASE;
549 iommu->iommu_control = reg_base + IOMMU_CONTROL; 550 iommu->iommu_control = reg_base + IOMMU_CONTROL;
@@ -575,7 +576,7 @@ static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus)
575 sbus->portid, regs); 576 sbus->portid, regs);
576 577
577 /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */ 578 /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
578 if (iommu_table_init(iommu, IO_TSB_SIZE, MAP_BASE, 0xffffffff)) 579 if (iommu_table_init(iommu, IO_TSB_SIZE, MAP_BASE, 0xffffffff, -1))
579 goto fatal_memory_error; 580 goto fatal_memory_error;
580 581
581 control = upa_readq(iommu->iommu_control); 582 control = upa_readq(iommu->iommu_control);
diff --git a/arch/sparc64/kernel/setup.c b/arch/sparc64/kernel/setup.c
index 6acb4c51cfe4..da5e6ee0c661 100644
--- a/arch/sparc64/kernel/setup.c
+++ b/arch/sparc64/kernel/setup.c
@@ -82,7 +82,7 @@ unsigned long cmdline_memory_size = 0;
82static struct console prom_early_console = { 82static struct console prom_early_console = {
83 .name = "earlyprom", 83 .name = "earlyprom",
84 .write = prom_console_write, 84 .write = prom_console_write,
85 .flags = CON_PRINTBUFFER | CON_BOOT, 85 .flags = CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
86 .index = -1, 86 .index = -1,
87}; 87};
88 88
@@ -281,6 +281,7 @@ void __init setup_arch(char **cmdline_p)
281 /* Initialize PROM console and command line. */ 281 /* Initialize PROM console and command line. */
282 *cmdline_p = prom_getbootargs(); 282 *cmdline_p = prom_getbootargs();
283 strcpy(boot_command_line, *cmdline_p); 283 strcpy(boot_command_line, *cmdline_p);
284 parse_early_param();
284 285
285 boot_flags_init(*cmdline_p); 286 boot_flags_init(*cmdline_p);
286 register_console(&prom_early_console); 287 register_console(&prom_early_console);
diff --git a/arch/sparc64/kernel/signal.c b/arch/sparc64/kernel/signal.c
index 1c47009eb5ec..45d6bf632daa 100644
--- a/arch/sparc64/kernel/signal.c
+++ b/arch/sparc64/kernel/signal.c
@@ -8,7 +8,7 @@
8 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 8 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 */ 9 */
10 10
11#ifdef CONFIG_SPARC32_COMPAT 11#ifdef CONFIG_COMPAT
12#include <linux/compat.h> /* for compat_old_sigset_t */ 12#include <linux/compat.h> /* for compat_old_sigset_t */
13#endif 13#endif
14#include <linux/sched.h> 14#include <linux/sched.h>
@@ -236,9 +236,6 @@ struct rt_signal_frame {
236 __siginfo_fpu_t fpu_state; 236 __siginfo_fpu_t fpu_state;
237}; 237};
238 238
239/* Align macros */
240#define RT_ALIGNEDSZ (((sizeof(struct rt_signal_frame) + 7) & (~7)))
241
242static long _sigpause_common(old_sigset_t set) 239static long _sigpause_common(old_sigset_t set)
243{ 240{
244 set &= _BLOCKABLE; 241 set &= _BLOCKABLE;
@@ -335,6 +332,9 @@ void do_rt_sigreturn(struct pt_regs *regs)
335 regs->tpc = tpc; 332 regs->tpc = tpc;
336 regs->tnpc = tnpc; 333 regs->tnpc = tnpc;
337 334
335 /* Prevent syscall restart. */
336 pt_regs_clear_trap_type(regs);
337
338 sigdelsetmask(&set, ~_BLOCKABLE); 338 sigdelsetmask(&set, ~_BLOCKABLE);
339 spin_lock_irq(&current->sighand->siglock); 339 spin_lock_irq(&current->sighand->siglock);
340 current->blocked = set; 340 current->blocked = set;
@@ -400,7 +400,7 @@ setup_rt_frame(struct k_sigaction *ka, struct pt_regs *regs,
400 synchronize_user_stack(); 400 synchronize_user_stack();
401 save_and_clear_fpu(); 401 save_and_clear_fpu();
402 402
403 sigframe_size = RT_ALIGNEDSZ; 403 sigframe_size = sizeof(struct rt_signal_frame);
404 if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) 404 if (!(current_thread_info()->fpsaved[0] & FPRS_FEF))
405 sigframe_size -= sizeof(__siginfo_fpu_t); 405 sigframe_size -= sizeof(__siginfo_fpu_t);
406 406
@@ -510,15 +510,20 @@ static inline void syscall_restart(unsigned long orig_i0, struct pt_regs *regs,
510 * want to handle. Thus you cannot kill init even with a SIGKILL even by 510 * want to handle. Thus you cannot kill init even with a SIGKILL even by
511 * mistake. 511 * mistake.
512 */ 512 */
513static void do_signal(struct pt_regs *regs, unsigned long orig_i0, int restart_syscall) 513static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
514{ 514{
515 siginfo_t info;
516 struct signal_deliver_cookie cookie; 515 struct signal_deliver_cookie cookie;
517 struct k_sigaction ka; 516 struct k_sigaction ka;
518 int signr;
519 sigset_t *oldset; 517 sigset_t *oldset;
518 siginfo_t info;
519 int signr;
520 520
521 cookie.restart_syscall = restart_syscall; 521 if (pt_regs_is_syscall(regs) &&
522 (regs->tstate & (TSTATE_XCARRY | TSTATE_ICARRY))) {
523 pt_regs_clear_trap_type(regs);
524 cookie.restart_syscall = 1;
525 } else
526 cookie.restart_syscall = 0;
522 cookie.orig_i0 = orig_i0; 527 cookie.orig_i0 = orig_i0;
523 528
524 if (test_thread_flag(TIF_RESTORE_SIGMASK)) 529 if (test_thread_flag(TIF_RESTORE_SIGMASK))
@@ -526,12 +531,11 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0, int restart_s
526 else 531 else
527 oldset = &current->blocked; 532 oldset = &current->blocked;
528 533
529#ifdef CONFIG_SPARC32_COMPAT 534#ifdef CONFIG_COMPAT
530 if (test_thread_flag(TIF_32BIT)) { 535 if (test_thread_flag(TIF_32BIT)) {
531 extern void do_signal32(sigset_t *, struct pt_regs *, 536 extern void do_signal32(sigset_t *, struct pt_regs *,
532 unsigned long, int); 537 struct signal_deliver_cookie *);
533 do_signal32(oldset, regs, orig_i0, 538 do_signal32(oldset, regs, &cookie);
534 cookie.restart_syscall);
535 return; 539 return;
536 } 540 }
537#endif 541#endif
@@ -539,7 +543,7 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0, int restart_s
539 signr = get_signal_to_deliver(&info, &ka, regs, &cookie); 543 signr = get_signal_to_deliver(&info, &ka, regs, &cookie);
540 if (signr > 0) { 544 if (signr > 0) {
541 if (cookie.restart_syscall) 545 if (cookie.restart_syscall)
542 syscall_restart(orig_i0, regs, &ka.sa); 546 syscall_restart(cookie.orig_i0, regs, &ka.sa);
543 handle_signal(signr, &ka, &info, oldset, regs); 547 handle_signal(signr, &ka, &info, oldset, regs);
544 548
545 /* a signal was successfully delivered; the saved 549 /* a signal was successfully delivered; the saved
@@ -576,11 +580,10 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0, int restart_s
576 } 580 }
577} 581}
578 582
579void do_notify_resume(struct pt_regs *regs, unsigned long orig_i0, int restart_syscall, 583void do_notify_resume(struct pt_regs *regs, unsigned long orig_i0, unsigned long thread_info_flags)
580 unsigned long thread_info_flags)
581{ 584{
582 if (thread_info_flags & (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK)) 585 if (thread_info_flags & (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK))
583 do_signal(regs, orig_i0, restart_syscall); 586 do_signal(regs, orig_i0);
584} 587}
585 588
586void ptrace_signal_deliver(struct pt_regs *regs, void *cookie) 589void ptrace_signal_deliver(struct pt_regs *regs, void *cookie)
diff --git a/arch/sparc64/kernel/signal32.c b/arch/sparc64/kernel/signal32.c
index 74e0512f135c..9415d2c918c5 100644
--- a/arch/sparc64/kernel/signal32.c
+++ b/arch/sparc64/kernel/signal32.c
@@ -1,5 +1,4 @@
1/* $Id: signal32.c,v 1.74 2002/02/09 19:49:30 davem Exp $ 1/* arch/sparc64/kernel/signal32.c
2 * arch/sparc64/kernel/signal32.c
3 * 2 *
4 * Copyright (C) 1991, 1992 Linus Torvalds 3 * Copyright (C) 1991, 1992 Linus Torvalds
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
@@ -31,30 +30,6 @@
31 30
32#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) 31#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
33 32
34/* Signal frames: the original one (compatible with SunOS):
35 *
36 * Set up a signal frame... Make the stack look the way SunOS
37 * expects it to look which is basically:
38 *
39 * ---------------------------------- <-- %sp at signal time
40 * Struct sigcontext
41 * Signal address
42 * Ptr to sigcontext area above
43 * Signal code
44 * The signal number itself
45 * One register window
46 * ---------------------------------- <-- New %sp
47 */
48struct signal_sframe32 {
49 struct reg_window32 sig_window;
50 int sig_num;
51 int sig_code;
52 /* struct sigcontext32 * */ u32 sig_scptr;
53 int sig_address;
54 struct sigcontext32 sig_context;
55 unsigned int extramask[_COMPAT_NSIG_WORDS - 1];
56};
57
58/* This magic should be in g_upper[0] for all upper parts 33/* This magic should be in g_upper[0] for all upper parts
59 * to be valid. 34 * to be valid.
60 */ 35 */
@@ -65,12 +40,7 @@ typedef struct {
65 unsigned int asi; 40 unsigned int asi;
66} siginfo_extra_v8plus_t; 41} siginfo_extra_v8plus_t;
67 42
68/* 43struct signal_frame32 {
69 * And the new one, intended to be used for Linux applications only
70 * (we have enough in there to work with clone).
71 * All the interesting bits are in the info field.
72 */
73struct new_signal_frame32 {
74 struct sparc_stackf32 ss; 44 struct sparc_stackf32 ss;
75 __siginfo32_t info; 45 __siginfo32_t info;
76 /* __siginfo_fpu32_t * */ u32 fpu_save; 46 /* __siginfo_fpu32_t * */ u32 fpu_save;
@@ -149,8 +119,7 @@ struct rt_signal_frame32 {
149}; 119};
150 120
151/* Align macros */ 121/* Align macros */
152#define SF_ALIGNEDSZ (((sizeof(struct signal_sframe32) + 7) & (~7))) 122#define SF_ALIGNEDSZ (((sizeof(struct signal_frame32) + 7) & (~7)))
153#define NF_ALIGNEDSZ (((sizeof(struct new_signal_frame32) + 7) & (~7)))
154#define RT_ALIGNEDSZ (((sizeof(struct rt_signal_frame32) + 7) & (~7))) 123#define RT_ALIGNEDSZ (((sizeof(struct rt_signal_frame32) + 7) & (~7)))
155 124
156int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from) 125int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from)
@@ -241,17 +210,22 @@ static int restore_fpu_state32(struct pt_regs *regs, __siginfo_fpu_t __user *fpu
241 return err; 210 return err;
242} 211}
243 212
244void do_new_sigreturn32(struct pt_regs *regs) 213void do_sigreturn32(struct pt_regs *regs)
245{ 214{
246 struct new_signal_frame32 __user *sf; 215 struct signal_frame32 __user *sf;
247 unsigned int psr; 216 unsigned int psr;
248 unsigned pc, npc, fpu_save; 217 unsigned pc, npc, fpu_save;
249 sigset_t set; 218 sigset_t set;
250 unsigned seta[_COMPAT_NSIG_WORDS]; 219 unsigned seta[_COMPAT_NSIG_WORDS];
251 int err, i; 220 int err, i;
252 221
222 /* Always make any pending restarted system calls return -EINTR */
223 current_thread_info()->restart_block.fn = do_no_restart_syscall;
224
225 synchronize_user_stack();
226
253 regs->u_regs[UREG_FP] &= 0x00000000ffffffffUL; 227 regs->u_regs[UREG_FP] &= 0x00000000ffffffffUL;
254 sf = (struct new_signal_frame32 __user *) regs->u_regs[UREG_FP]; 228 sf = (struct signal_frame32 __user *) regs->u_regs[UREG_FP];
255 229
256 /* 1. Make sure we are not getting garbage from the user */ 230 /* 1. Make sure we are not getting garbage from the user */
257 if (!access_ok(VERIFY_READ, sf, sizeof(*sf)) || 231 if (!access_ok(VERIFY_READ, sf, sizeof(*sf)) ||
@@ -294,6 +268,9 @@ void do_new_sigreturn32(struct pt_regs *regs)
294 regs->tstate &= ~(TSTATE_ICC|TSTATE_XCC); 268 regs->tstate &= ~(TSTATE_ICC|TSTATE_XCC);
295 regs->tstate |= psr_to_tstate_icc(psr); 269 regs->tstate |= psr_to_tstate_icc(psr);
296 270
271 /* Prevent syscall restart. */
272 pt_regs_clear_trap_type(regs);
273
297 err |= __get_user(fpu_save, &sf->fpu_save); 274 err |= __get_user(fpu_save, &sf->fpu_save);
298 if (fpu_save) 275 if (fpu_save)
299 err |= restore_fpu_state32(regs, &sf->fpu_state); 276 err |= restore_fpu_state32(regs, &sf->fpu_state);
@@ -319,76 +296,6 @@ segv:
319 force_sig(SIGSEGV, current); 296 force_sig(SIGSEGV, current);
320} 297}
321 298
322asmlinkage void do_sigreturn32(struct pt_regs *regs)
323{
324 struct sigcontext32 __user *scptr;
325 unsigned int pc, npc, psr;
326 sigset_t set;
327 unsigned int seta[_COMPAT_NSIG_WORDS];
328 int err;
329
330 /* Always make any pending restarted system calls return -EINTR */
331 current_thread_info()->restart_block.fn = do_no_restart_syscall;
332
333 synchronize_user_stack();
334 if (test_thread_flag(TIF_NEWSIGNALS)) {
335 do_new_sigreturn32(regs);
336 return;
337 }
338
339 scptr = (struct sigcontext32 __user *)
340 (regs->u_regs[UREG_I0] & 0x00000000ffffffffUL);
341 /* Check sanity of the user arg. */
342 if (!access_ok(VERIFY_READ, scptr, sizeof(struct sigcontext32)) ||
343 (((unsigned long) scptr) & 3))
344 goto segv;
345
346 err = __get_user(pc, &scptr->sigc_pc);
347 err |= __get_user(npc, &scptr->sigc_npc);
348
349 if ((pc | npc) & 3)
350 goto segv; /* Nice try. */
351
352 err |= __get_user(seta[0], &scptr->sigc_mask);
353 /* Note that scptr + 1 points to extramask */
354 err |= copy_from_user(seta+1, scptr + 1,
355 (_COMPAT_NSIG_WORDS - 1) * sizeof(unsigned int));
356 if (err)
357 goto segv;
358 switch (_NSIG_WORDS) {
359 case 4: set.sig[3] = seta[6] + (((long)seta[7]) << 32);
360 case 3: set.sig[2] = seta[4] + (((long)seta[5]) << 32);
361 case 2: set.sig[1] = seta[2] + (((long)seta[3]) << 32);
362 case 1: set.sig[0] = seta[0] + (((long)seta[1]) << 32);
363 }
364 sigdelsetmask(&set, ~_BLOCKABLE);
365 spin_lock_irq(&current->sighand->siglock);
366 current->blocked = set;
367 recalc_sigpending();
368 spin_unlock_irq(&current->sighand->siglock);
369
370 if (test_thread_flag(TIF_32BIT)) {
371 pc &= 0xffffffff;
372 npc &= 0xffffffff;
373 }
374 regs->tpc = pc;
375 regs->tnpc = npc;
376 err = __get_user(regs->u_regs[UREG_FP], &scptr->sigc_sp);
377 err |= __get_user(regs->u_regs[UREG_I0], &scptr->sigc_o0);
378 err |= __get_user(regs->u_regs[UREG_G1], &scptr->sigc_g1);
379
380 /* User can only change condition codes in %tstate. */
381 err |= __get_user(psr, &scptr->sigc_psr);
382 if (err)
383 goto segv;
384 regs->tstate &= ~(TSTATE_ICC|TSTATE_XCC);
385 regs->tstate |= psr_to_tstate_icc(psr);
386 return;
387
388segv:
389 force_sig(SIGSEGV, current);
390}
391
392asmlinkage void do_rt_sigreturn32(struct pt_regs *regs) 299asmlinkage void do_rt_sigreturn32(struct pt_regs *regs)
393{ 300{
394 struct rt_signal_frame32 __user *sf; 301 struct rt_signal_frame32 __user *sf;
@@ -447,6 +354,9 @@ asmlinkage void do_rt_sigreturn32(struct pt_regs *regs)
447 regs->tstate &= ~(TSTATE_ICC|TSTATE_XCC); 354 regs->tstate &= ~(TSTATE_ICC|TSTATE_XCC);
448 regs->tstate |= psr_to_tstate_icc(psr); 355 regs->tstate |= psr_to_tstate_icc(psr);
449 356
357 /* Prevent syscall restart. */
358 pt_regs_clear_trap_type(regs);
359
450 err |= __get_user(fpu_save, &sf->fpu_save); 360 err |= __get_user(fpu_save, &sf->fpu_save);
451 if (fpu_save) 361 if (fpu_save)
452 err |= restore_fpu_state32(regs, &sf->fpu_state); 362 err |= restore_fpu_state32(regs, &sf->fpu_state);
@@ -504,145 +414,6 @@ static void __user *get_sigframe(struct sigaction *sa, struct pt_regs *regs, uns
504 return (void __user *)(sp - framesize); 414 return (void __user *)(sp - framesize);
505} 415}
506 416
507static void
508setup_frame32(struct sigaction *sa, struct pt_regs *regs, int signr, sigset_t *oldset, siginfo_t *info)
509{
510 struct signal_sframe32 __user *sframep;
511 struct sigcontext32 __user *sc;
512 unsigned int seta[_COMPAT_NSIG_WORDS];
513 int err = 0;
514 void __user *sig_address;
515 int sig_code;
516 unsigned long pc = regs->tpc;
517 unsigned long npc = regs->tnpc;
518 unsigned int psr;
519
520 if (test_thread_flag(TIF_32BIT)) {
521 pc &= 0xffffffff;
522 npc &= 0xffffffff;
523 }
524
525 synchronize_user_stack();
526 save_and_clear_fpu();
527
528 sframep = (struct signal_sframe32 __user *)
529 get_sigframe(sa, regs, SF_ALIGNEDSZ);
530 if (invalid_frame_pointer(sframep, sizeof(*sframep))){
531 /* Don't change signal code and address, so that
532 * post mortem debuggers can have a look.
533 */
534 do_exit(SIGILL);
535 }
536
537 sc = &sframep->sig_context;
538
539 /* We've already made sure frame pointer isn't in kernel space... */
540 err = __put_user((sas_ss_flags(regs->u_regs[UREG_FP]) == SS_ONSTACK),
541 &sc->sigc_onstack);
542
543 switch (_NSIG_WORDS) {
544 case 4: seta[7] = (oldset->sig[3] >> 32);
545 seta[6] = oldset->sig[3];
546 case 3: seta[5] = (oldset->sig[2] >> 32);
547 seta[4] = oldset->sig[2];
548 case 2: seta[3] = (oldset->sig[1] >> 32);
549 seta[2] = oldset->sig[1];
550 case 1: seta[1] = (oldset->sig[0] >> 32);
551 seta[0] = oldset->sig[0];
552 }
553 err |= __put_user(seta[0], &sc->sigc_mask);
554 err |= __copy_to_user(sframep->extramask, seta + 1,
555 (_COMPAT_NSIG_WORDS - 1) * sizeof(unsigned int));
556 err |= __put_user(regs->u_regs[UREG_FP], &sc->sigc_sp);
557 err |= __put_user(pc, &sc->sigc_pc);
558 err |= __put_user(npc, &sc->sigc_npc);
559 psr = tstate_to_psr(regs->tstate);
560 if (current_thread_info()->fpsaved[0] & FPRS_FEF)
561 psr |= PSR_EF;
562 err |= __put_user(psr, &sc->sigc_psr);
563 err |= __put_user(regs->u_regs[UREG_G1], &sc->sigc_g1);
564 err |= __put_user(regs->u_regs[UREG_I0], &sc->sigc_o0);
565 err |= __put_user(get_thread_wsaved(), &sc->sigc_oswins);
566
567 err |= copy_in_user((u32 __user *)sframep,
568 (u32 __user *)(regs->u_regs[UREG_FP]),
569 sizeof(struct reg_window32));
570
571 set_thread_wsaved(0); /* So process is allowed to execute. */
572 err |= __put_user(signr, &sframep->sig_num);
573 sig_address = NULL;
574 sig_code = 0;
575 if (SI_FROMKERNEL (info) && (info->si_code & __SI_MASK) == __SI_FAULT) {
576 sig_address = info->si_addr;
577 switch (signr) {
578 case SIGSEGV:
579 switch (info->si_code) {
580 case SEGV_MAPERR: sig_code = SUBSIG_NOMAPPING; break;
581 default: sig_code = SUBSIG_PROTECTION; break;
582 }
583 break;
584 case SIGILL:
585 switch (info->si_code) {
586 case ILL_ILLOPC: sig_code = SUBSIG_ILLINST; break;
587 case ILL_PRVOPC: sig_code = SUBSIG_PRIVINST; break;
588 case ILL_ILLTRP: sig_code = SUBSIG_BADTRAP(info->si_trapno); break;
589 default: sig_code = SUBSIG_STACK; break;
590 }
591 break;
592 case SIGFPE:
593 switch (info->si_code) {
594 case FPE_INTDIV: sig_code = SUBSIG_IDIVZERO; break;
595 case FPE_INTOVF: sig_code = SUBSIG_FPINTOVFL; break;
596 case FPE_FLTDIV: sig_code = SUBSIG_FPDIVZERO; break;
597 case FPE_FLTOVF: sig_code = SUBSIG_FPOVFLOW; break;
598 case FPE_FLTUND: sig_code = SUBSIG_FPUNFLOW; break;
599 case FPE_FLTRES: sig_code = SUBSIG_FPINEXACT; break;
600 case FPE_FLTINV: sig_code = SUBSIG_FPOPERROR; break;
601 default: sig_code = SUBSIG_FPERROR; break;
602 }
603 break;
604 case SIGBUS:
605 switch (info->si_code) {
606 case BUS_ADRALN: sig_code = SUBSIG_ALIGNMENT; break;
607 case BUS_ADRERR: sig_code = SUBSIG_MISCERROR; break;
608 default: sig_code = SUBSIG_BUSTIMEOUT; break;
609 }
610 break;
611 case SIGEMT:
612 switch (info->si_code) {
613 case EMT_TAGOVF: sig_code = SUBSIG_TAG; break;
614 }
615 break;
616 case SIGSYS:
617 if (info->si_code == (__SI_FAULT|0x100)) {
618 /* See sys_sunos32.c */
619 sig_code = info->si_trapno;
620 break;
621 }
622 default:
623 sig_address = NULL;
624 }
625 }
626 err |= __put_user(ptr_to_compat(sig_address), &sframep->sig_address);
627 err |= __put_user(sig_code, &sframep->sig_code);
628 err |= __put_user(ptr_to_compat(sc), &sframep->sig_scptr);
629 if (err)
630 goto sigsegv;
631
632 regs->u_regs[UREG_FP] = (unsigned long) sframep;
633 regs->tpc = (unsigned long) sa->sa_handler;
634 regs->tnpc = (regs->tpc + 4);
635 if (test_thread_flag(TIF_32BIT)) {
636 regs->tpc &= 0xffffffff;
637 regs->tnpc &= 0xffffffff;
638 }
639 return;
640
641sigsegv:
642 force_sigsegv(signr, current);
643}
644
645
646static int save_fpu_state32(struct pt_regs *regs, __siginfo_fpu_t __user *fpu) 417static int save_fpu_state32(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
647{ 418{
648 unsigned long *fpregs = current_thread_info()->fpregs; 419 unsigned long *fpregs = current_thread_info()->fpregs;
@@ -663,10 +434,10 @@ static int save_fpu_state32(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
663 return err; 434 return err;
664} 435}
665 436
666static void new_setup_frame32(struct k_sigaction *ka, struct pt_regs *regs, 437static void setup_frame32(struct k_sigaction *ka, struct pt_regs *regs,
667 int signo, sigset_t *oldset) 438 int signo, sigset_t *oldset)
668{ 439{
669 struct new_signal_frame32 __user *sf; 440 struct signal_frame32 __user *sf;
670 int sigframe_size; 441 int sigframe_size;
671 u32 psr; 442 u32 psr;
672 int i, err; 443 int i, err;
@@ -676,11 +447,11 @@ static void new_setup_frame32(struct k_sigaction *ka, struct pt_regs *regs,
676 synchronize_user_stack(); 447 synchronize_user_stack();
677 save_and_clear_fpu(); 448 save_and_clear_fpu();
678 449
679 sigframe_size = NF_ALIGNEDSZ; 450 sigframe_size = SF_ALIGNEDSZ;
680 if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) 451 if (!(current_thread_info()->fpsaved[0] & FPRS_FEF))
681 sigframe_size -= sizeof(__siginfo_fpu_t); 452 sigframe_size -= sizeof(__siginfo_fpu_t);
682 453
683 sf = (struct new_signal_frame32 __user *) 454 sf = (struct signal_frame32 __user *)
684 get_sigframe(&ka->sa, regs, sigframe_size); 455 get_sigframe(&ka->sa, regs, sigframe_size);
685 456
686 if (invalid_frame_pointer(sf, sigframe_size)) 457 if (invalid_frame_pointer(sf, sigframe_size))
@@ -944,10 +715,9 @@ static inline void handle_signal32(unsigned long signr, struct k_sigaction *ka,
944{ 715{
945 if (ka->sa.sa_flags & SA_SIGINFO) 716 if (ka->sa.sa_flags & SA_SIGINFO)
946 setup_rt_frame32(ka, regs, signr, oldset, info); 717 setup_rt_frame32(ka, regs, signr, oldset, info);
947 else if (test_thread_flag(TIF_NEWSIGNALS))
948 new_setup_frame32(ka, regs, signr, oldset);
949 else 718 else
950 setup_frame32(&ka->sa, regs, signr, oldset, info); 719 setup_frame32(ka, regs, signr, oldset);
720
951 spin_lock_irq(&current->sighand->siglock); 721 spin_lock_irq(&current->sighand->siglock);
952 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask); 722 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
953 if (!(ka->sa.sa_flags & SA_NOMASK)) 723 if (!(ka->sa.sa_flags & SA_NOMASK))
@@ -982,20 +752,16 @@ static inline void syscall_restart32(unsigned long orig_i0, struct pt_regs *regs
982 * mistake. 752 * mistake.
983 */ 753 */
984void do_signal32(sigset_t *oldset, struct pt_regs * regs, 754void do_signal32(sigset_t *oldset, struct pt_regs * regs,
985 unsigned long orig_i0, int restart_syscall) 755 struct signal_deliver_cookie *cookie)
986{ 756{
987 siginfo_t info;
988 struct signal_deliver_cookie cookie;
989 struct k_sigaction ka; 757 struct k_sigaction ka;
758 siginfo_t info;
990 int signr; 759 int signr;
991 760
992 cookie.restart_syscall = restart_syscall; 761 signr = get_signal_to_deliver(&info, &ka, regs, cookie);
993 cookie.orig_i0 = orig_i0;
994
995 signr = get_signal_to_deliver(&info, &ka, regs, &cookie);
996 if (signr > 0) { 762 if (signr > 0) {
997 if (cookie.restart_syscall) 763 if (cookie->restart_syscall)
998 syscall_restart32(orig_i0, regs, &ka.sa); 764 syscall_restart32(cookie->orig_i0, regs, &ka.sa);
999 handle_signal32(signr, &ka, &info, oldset, regs); 765 handle_signal32(signr, &ka, &info, oldset, regs);
1000 766
1001 /* a signal was successfully delivered; the saved 767 /* a signal was successfully delivered; the saved
@@ -1007,16 +773,16 @@ void do_signal32(sigset_t *oldset, struct pt_regs * regs,
1007 clear_thread_flag(TIF_RESTORE_SIGMASK); 773 clear_thread_flag(TIF_RESTORE_SIGMASK);
1008 return; 774 return;
1009 } 775 }
1010 if (cookie.restart_syscall && 776 if (cookie->restart_syscall &&
1011 (regs->u_regs[UREG_I0] == ERESTARTNOHAND || 777 (regs->u_regs[UREG_I0] == ERESTARTNOHAND ||
1012 regs->u_regs[UREG_I0] == ERESTARTSYS || 778 regs->u_regs[UREG_I0] == ERESTARTSYS ||
1013 regs->u_regs[UREG_I0] == ERESTARTNOINTR)) { 779 regs->u_regs[UREG_I0] == ERESTARTNOINTR)) {
1014 /* replay the system call when we are done */ 780 /* replay the system call when we are done */
1015 regs->u_regs[UREG_I0] = cookie.orig_i0; 781 regs->u_regs[UREG_I0] = cookie->orig_i0;
1016 regs->tpc -= 4; 782 regs->tpc -= 4;
1017 regs->tnpc -= 4; 783 regs->tnpc -= 4;
1018 } 784 }
1019 if (cookie.restart_syscall && 785 if (cookie->restart_syscall &&
1020 regs->u_regs[UREG_I0] == ERESTART_RESTARTBLOCK) { 786 regs->u_regs[UREG_I0] == ERESTART_RESTARTBLOCK) {
1021 regs->u_regs[UREG_G1] = __NR_restart_syscall; 787 regs->u_regs[UREG_G1] = __NR_restart_syscall;
1022 regs->tpc -= 4; 788 regs->tpc -= 4;
diff --git a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c
index 59f020d69d4c..3aba47624df4 100644
--- a/arch/sparc64/kernel/smp.c
+++ b/arch/sparc64/kernel/smp.c
@@ -20,7 +20,7 @@
20#include <linux/cache.h> 20#include <linux/cache.h>
21#include <linux/jiffies.h> 21#include <linux/jiffies.h>
22#include <linux/profile.h> 22#include <linux/profile.h>
23#include <linux/bootmem.h> 23#include <linux/lmb.h>
24 24
25#include <asm/head.h> 25#include <asm/head.h>
26#include <asm/ptrace.h> 26#include <asm/ptrace.h>
@@ -38,7 +38,6 @@
38#include <asm/pgtable.h> 38#include <asm/pgtable.h>
39#include <asm/oplib.h> 39#include <asm/oplib.h>
40#include <asm/uaccess.h> 40#include <asm/uaccess.h>
41#include <asm/timer.h>
42#include <asm/starfire.h> 41#include <asm/starfire.h>
43#include <asm/tlb.h> 42#include <asm/tlb.h>
44#include <asm/sections.h> 43#include <asm/sections.h>
@@ -866,14 +865,21 @@ void smp_call_function_client(int irq, struct pt_regs *regs)
866 void *info = call_data->info; 865 void *info = call_data->info;
867 866
868 clear_softint(1 << irq); 867 clear_softint(1 << irq);
868
869 irq_enter();
870
871 if (!call_data->wait) {
872 /* let initiator proceed after getting data */
873 atomic_inc(&call_data->finished);
874 }
875
876 func(info);
877
878 irq_exit();
879
869 if (call_data->wait) { 880 if (call_data->wait) {
870 /* let initiator proceed only after completion */ 881 /* let initiator proceed only after completion */
871 func(info);
872 atomic_inc(&call_data->finished);
873 } else {
874 /* let initiator proceed after getting data */
875 atomic_inc(&call_data->finished); 882 atomic_inc(&call_data->finished);
876 func(info);
877 } 883 }
878} 884}
879 885
@@ -903,6 +909,9 @@ extern unsigned long xcall_flush_tlb_kernel_range;
903extern unsigned long xcall_report_regs; 909extern unsigned long xcall_report_regs;
904extern unsigned long xcall_receive_signal; 910extern unsigned long xcall_receive_signal;
905extern unsigned long xcall_new_mmu_context_version; 911extern unsigned long xcall_new_mmu_context_version;
912#ifdef CONFIG_KGDB
913extern unsigned long xcall_kgdb_capture;
914#endif
906 915
907#ifdef DCACHE_ALIASING_POSSIBLE 916#ifdef DCACHE_ALIASING_POSSIBLE
908extern unsigned long xcall_flush_dcache_page_cheetah; 917extern unsigned long xcall_flush_dcache_page_cheetah;
@@ -1032,7 +1041,9 @@ void smp_receive_signal(int cpu)
1032 1041
1033void smp_receive_signal_client(int irq, struct pt_regs *regs) 1042void smp_receive_signal_client(int irq, struct pt_regs *regs)
1034{ 1043{
1044 irq_enter();
1035 clear_softint(1 << irq); 1045 clear_softint(1 << irq);
1046 irq_exit();
1036} 1047}
1037 1048
1038void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs) 1049void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
@@ -1040,6 +1051,8 @@ void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
1040 struct mm_struct *mm; 1051 struct mm_struct *mm;
1041 unsigned long flags; 1052 unsigned long flags;
1042 1053
1054 irq_enter();
1055
1043 clear_softint(1 << irq); 1056 clear_softint(1 << irq);
1044 1057
1045 /* See if we need to allocate a new TLB context because 1058 /* See if we need to allocate a new TLB context because
@@ -1059,6 +1072,8 @@ void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
1059 load_secondary_context(mm); 1072 load_secondary_context(mm);
1060 __flush_tlb_mm(CTX_HWBITS(mm->context), 1073 __flush_tlb_mm(CTX_HWBITS(mm->context),
1061 SECONDARY_CONTEXT); 1074 SECONDARY_CONTEXT);
1075
1076 irq_exit();
1062} 1077}
1063 1078
1064void smp_new_mmu_context_version(void) 1079void smp_new_mmu_context_version(void)
@@ -1066,6 +1081,13 @@ void smp_new_mmu_context_version(void)
1066 smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0); 1081 smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
1067} 1082}
1068 1083
1084#ifdef CONFIG_KGDB
1085void kgdb_roundup_cpus(unsigned long flags)
1086{
1087 smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
1088}
1089#endif
1090
1069void smp_report_regs(void) 1091void smp_report_regs(void)
1070{ 1092{
1071 smp_cross_call(&xcall_report_regs, 0, 0, 0); 1093 smp_cross_call(&xcall_report_regs, 0, 0, 0);
@@ -1217,6 +1239,8 @@ void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1217{ 1239{
1218 clear_softint(1 << irq); 1240 clear_softint(1 << irq);
1219 1241
1242 irq_enter();
1243
1220 preempt_disable(); 1244 preempt_disable();
1221 1245
1222 __asm__ __volatile__("flushw"); 1246 __asm__ __volatile__("flushw");
@@ -1229,6 +1253,8 @@ void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1229 prom_world(0); 1253 prom_world(0);
1230 1254
1231 preempt_enable(); 1255 preempt_enable();
1256
1257 irq_exit();
1232} 1258}
1233 1259
1234/* /proc/profile writes can call this, don't __init it please. */ 1260/* /proc/profile writes can call this, don't __init it please. */
@@ -1431,7 +1457,7 @@ EXPORT_SYMBOL(__per_cpu_shift);
1431 1457
1432void __init real_setup_per_cpu_areas(void) 1458void __init real_setup_per_cpu_areas(void)
1433{ 1459{
1434 unsigned long goal, size, i; 1460 unsigned long paddr, goal, size, i;
1435 char *ptr; 1461 char *ptr;
1436 1462
1437 /* Copy section for each CPU (we discard the original) */ 1463 /* Copy section for each CPU (we discard the original) */
@@ -1441,8 +1467,13 @@ void __init real_setup_per_cpu_areas(void)
1441 for (size = PAGE_SIZE; size < goal; size <<= 1UL) 1467 for (size = PAGE_SIZE; size < goal; size <<= 1UL)
1442 __per_cpu_shift++; 1468 __per_cpu_shift++;
1443 1469
1444 ptr = alloc_bootmem_pages(size * NR_CPUS); 1470 paddr = lmb_alloc(size * NR_CPUS, PAGE_SIZE);
1471 if (!paddr) {
1472 prom_printf("Cannot allocate per-cpu memory.\n");
1473 prom_halt();
1474 }
1445 1475
1476 ptr = __va(paddr);
1446 __per_cpu_base = ptr - __per_cpu_start; 1477 __per_cpu_base = ptr - __per_cpu_start;
1447 1478
1448 for (i = 0; i < NR_CPUS; i++, ptr += size) 1479 for (i = 0; i < NR_CPUS; i++, ptr += size)
diff --git a/arch/sparc64/kernel/sparc64_ksyms.c b/arch/sparc64/kernel/sparc64_ksyms.c
index 38736460b8db..8ac0b99f2c55 100644
--- a/arch/sparc64/kernel/sparc64_ksyms.c
+++ b/arch/sparc64/kernel/sparc64_ksyms.c
@@ -49,7 +49,6 @@
49#endif 49#endif
50#ifdef CONFIG_PCI 50#ifdef CONFIG_PCI
51#include <asm/ebus.h> 51#include <asm/ebus.h>
52#include <asm/isa.h>
53#endif 52#endif
54#include <asm/ns87303.h> 53#include <asm/ns87303.h>
55#include <asm/timer.h> 54#include <asm/timer.h>
@@ -68,8 +67,6 @@ extern void *__memscan_zero(void *, size_t);
68extern void *__memscan_generic(void *, int, size_t); 67extern void *__memscan_generic(void *, int, size_t);
69extern int __memcmp(const void *, const void *, __kernel_size_t); 68extern int __memcmp(const void *, const void *, __kernel_size_t);
70extern __kernel_size_t strlen(const char *); 69extern __kernel_size_t strlen(const char *);
71extern void linux_sparc_syscall(void);
72extern void rtrap(void);
73extern void show_regs(struct pt_regs *); 70extern void show_regs(struct pt_regs *);
74extern void syscall_trace(struct pt_regs *, int); 71extern void syscall_trace(struct pt_regs *, int);
75extern void sys_sigsuspend(void); 72extern void sys_sigsuspend(void);
@@ -189,7 +186,6 @@ EXPORT_SYMBOL(insw);
189EXPORT_SYMBOL(insl); 186EXPORT_SYMBOL(insl);
190#ifdef CONFIG_PCI 187#ifdef CONFIG_PCI
191EXPORT_SYMBOL(ebus_chain); 188EXPORT_SYMBOL(ebus_chain);
192EXPORT_SYMBOL(isa_chain);
193EXPORT_SYMBOL(pci_alloc_consistent); 189EXPORT_SYMBOL(pci_alloc_consistent);
194EXPORT_SYMBOL(pci_free_consistent); 190EXPORT_SYMBOL(pci_free_consistent);
195EXPORT_SYMBOL(pci_map_single); 191EXPORT_SYMBOL(pci_map_single);
diff --git a/arch/sparc64/kernel/spiterrs.S b/arch/sparc64/kernel/spiterrs.S
new file mode 100644
index 000000000000..ef902c6f8e3c
--- /dev/null
+++ b/arch/sparc64/kernel/spiterrs.S
@@ -0,0 +1,245 @@
1 /* We need to carefully read the error status, ACK the errors,
2 * prevent recursive traps, and pass the information on to C
3 * code for logging.
4 *
5 * We pass the AFAR in as-is, and we encode the status
6 * information as described in asm-sparc64/sfafsr.h
7 */
8 .type __spitfire_access_error,#function
9__spitfire_access_error:
10 /* Disable ESTATE error reporting so that we do not take
11 * recursive traps and RED state the processor.
12 */
13 stxa %g0, [%g0] ASI_ESTATE_ERROR_EN
14 membar #Sync
15
16 mov UDBE_UE, %g1
17 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
18
19 /* __spitfire_cee_trap branches here with AFSR in %g4 and
20 * UDBE_CE in %g1. It only clears ESTATE_ERR_CE in the ESTATE
21 * Error Enable register.
22 */
23__spitfire_cee_trap_continue:
24 ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR
25
26 rdpr %tt, %g3
27 and %g3, 0x1ff, %g3 ! Paranoia
28 sllx %g3, SFSTAT_TRAP_TYPE_SHIFT, %g3
29 or %g4, %g3, %g4
30 rdpr %tl, %g3
31 cmp %g3, 1
32 mov 1, %g3
33 bleu %xcc, 1f
34 sllx %g3, SFSTAT_TL_GT_ONE_SHIFT, %g3
35
36 or %g4, %g3, %g4
37
38 /* Read in the UDB error register state, clearing the sticky
39 * error bits as-needed. We only clear them if the UE bit is
40 * set. Likewise, __spitfire_cee_trap below will only do so
41 * if the CE bit is set.
42 *
43 * NOTE: UltraSparc-I/II have high and low UDB error
44 * registers, corresponding to the two UDB units
45 * present on those chips. UltraSparc-IIi only
46 * has a single UDB, called "SDB" in the manual.
47 * For IIi the upper UDB register always reads
48 * as zero so for our purposes things will just
49 * work with the checks below.
50 */
511: ldxa [%g0] ASI_UDBH_ERROR_R, %g3
52 and %g3, 0x3ff, %g7 ! Paranoia
53 sllx %g7, SFSTAT_UDBH_SHIFT, %g7
54 or %g4, %g7, %g4
55 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
56 be,pn %xcc, 1f
57 nop
58 stxa %g3, [%g0] ASI_UDB_ERROR_W
59 membar #Sync
60
611: mov 0x18, %g3
62 ldxa [%g3] ASI_UDBL_ERROR_R, %g3
63 and %g3, 0x3ff, %g7 ! Paranoia
64 sllx %g7, SFSTAT_UDBL_SHIFT, %g7
65 or %g4, %g7, %g4
66 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
67 be,pn %xcc, 1f
68 nop
69 mov 0x18, %g7
70 stxa %g3, [%g7] ASI_UDB_ERROR_W
71 membar #Sync
72
731: /* Ok, now that we've latched the error state, clear the
74 * sticky bits in the AFSR.
75 */
76 stxa %g4, [%g0] ASI_AFSR
77 membar #Sync
78
79 rdpr %tl, %g2
80 cmp %g2, 1
81 rdpr %pil, %g2
82 bleu,pt %xcc, 1f
83 wrpr %g0, 15, %pil
84
85 ba,pt %xcc, etraptl1
86 rd %pc, %g7
87
88 ba,pt %xcc, 2f
89 nop
90
911: ba,pt %xcc, etrap_irq
92 rd %pc, %g7
93
942:
95#ifdef CONFIG_TRACE_IRQFLAGS
96 call trace_hardirqs_off
97 nop
98#endif
99 mov %l4, %o1
100 mov %l5, %o2
101 call spitfire_access_error
102 add %sp, PTREGS_OFF, %o0
103 ba,pt %xcc, rtrap
104 nop
105 .size __spitfire_access_error,.-__spitfire_access_error
106
107 /* This is the trap handler entry point for ECC correctable
108 * errors. They are corrected, but we listen for the trap so
109 * that the event can be logged.
110 *
111 * Disrupting errors are either:
112 * 1) single-bit ECC errors during UDB reads to system
113 * memory
114 * 2) data parity errors during write-back events
115 *
116 * As far as I can make out from the manual, the CEE trap is
117 * only for correctable errors during memory read accesses by
118 * the front-end of the processor.
119 *
120 * The code below is only for trap level 1 CEE events, as it
121 * is the only situation where we can safely record and log.
122 * For trap level >1 we just clear the CE bit in the AFSR and
123 * return.
124 *
125 * This is just like __spiftire_access_error above, but it
126 * specifically handles correctable errors. If an
127 * uncorrectable error is indicated in the AFSR we will branch
128 * directly above to __spitfire_access_error to handle it
129 * instead. Uncorrectable therefore takes priority over
130 * correctable, and the error logging C code will notice this
131 * case by inspecting the trap type.
132 */
133 .type __spitfire_cee_trap,#function
134__spitfire_cee_trap:
135 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
136 mov 1, %g3
137 sllx %g3, SFAFSR_UE_SHIFT, %g3
138 andcc %g4, %g3, %g0 ! Check for UE
139 bne,pn %xcc, __spitfire_access_error
140 nop
141
142 /* Ok, in this case we only have a correctable error.
143 * Indicate we only wish to capture that state in register
144 * %g1, and we only disable CE error reporting unlike UE
145 * handling which disables all errors.
146 */
147 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g3
148 andn %g3, ESTATE_ERR_CE, %g3
149 stxa %g3, [%g0] ASI_ESTATE_ERROR_EN
150 membar #Sync
151
152 /* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */
153 ba,pt %xcc, __spitfire_cee_trap_continue
154 mov UDBE_CE, %g1
155 .size __spitfire_cee_trap,.-__spitfire_cee_trap
156
157 .type __spitfire_data_access_exception_tl1,#function
158__spitfire_data_access_exception_tl1:
159 rdpr %pstate, %g4
160 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
161 mov TLB_SFSR, %g3
162 mov DMMU_SFAR, %g5
163 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
164 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
165 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
166 membar #Sync
167 rdpr %tt, %g3
168 cmp %g3, 0x80 ! first win spill/fill trap
169 blu,pn %xcc, 1f
170 cmp %g3, 0xff ! last win spill/fill trap
171 bgu,pn %xcc, 1f
172 nop
173 ba,pt %xcc, winfix_dax
174 rdpr %tpc, %g3
1751: sethi %hi(109f), %g7
176 ba,pt %xcc, etraptl1
177109: or %g7, %lo(109b), %g7
178 mov %l4, %o1
179 mov %l5, %o2
180 call spitfire_data_access_exception_tl1
181 add %sp, PTREGS_OFF, %o0
182 ba,pt %xcc, rtrap
183 nop
184 .size __spitfire_data_access_exception_tl1,.-__spitfire_data_access_exception_tl1
185
186 .type __spitfire_data_access_exception,#function
187__spitfire_data_access_exception:
188 rdpr %pstate, %g4
189 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
190 mov TLB_SFSR, %g3
191 mov DMMU_SFAR, %g5
192 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
193 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
194 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
195 membar #Sync
196 sethi %hi(109f), %g7
197 ba,pt %xcc, etrap
198109: or %g7, %lo(109b), %g7
199 mov %l4, %o1
200 mov %l5, %o2
201 call spitfire_data_access_exception
202 add %sp, PTREGS_OFF, %o0
203 ba,pt %xcc, rtrap
204 nop
205 .size __spitfire_data_access_exception,.-__spitfire_data_access_exception
206
207 .type __spitfire_insn_access_exception_tl1,#function
208__spitfire_insn_access_exception_tl1:
209 rdpr %pstate, %g4
210 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
211 mov TLB_SFSR, %g3
212 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
213 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
214 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
215 membar #Sync
216 sethi %hi(109f), %g7
217 ba,pt %xcc, etraptl1
218109: or %g7, %lo(109b), %g7
219 mov %l4, %o1
220 mov %l5, %o2
221 call spitfire_insn_access_exception_tl1
222 add %sp, PTREGS_OFF, %o0
223 ba,pt %xcc, rtrap
224 nop
225 .size __spitfire_insn_access_exception_tl1,.-__spitfire_insn_access_exception_tl1
226
227 .type __spitfire_insn_access_exception,#function
228__spitfire_insn_access_exception:
229 rdpr %pstate, %g4
230 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
231 mov TLB_SFSR, %g3
232 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
233 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
234 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
235 membar #Sync
236 sethi %hi(109f), %g7
237 ba,pt %xcc, etrap
238109: or %g7, %lo(109b), %g7
239 mov %l4, %o1
240 mov %l5, %o2
241 call spitfire_insn_access_exception
242 add %sp, PTREGS_OFF, %o0
243 ba,pt %xcc, rtrap
244 nop
245 .size __spitfire_insn_access_exception,.-__spitfire_insn_access_exception
diff --git a/arch/sparc64/kernel/stacktrace.c b/arch/sparc64/kernel/stacktrace.c
index 84d39e873e88..01b52f561af4 100644
--- a/arch/sparc64/kernel/stacktrace.c
+++ b/arch/sparc64/kernel/stacktrace.c
@@ -20,6 +20,8 @@ void save_stack_trace(struct stack_trace *trace)
20 thread_base = (unsigned long) tp; 20 thread_base = (unsigned long) tp;
21 do { 21 do {
22 struct reg_window *rw; 22 struct reg_window *rw;
23 struct pt_regs *regs;
24 unsigned long pc;
23 25
24 /* Bogus frame pointer? */ 26 /* Bogus frame pointer? */
25 if (fp < (thread_base + sizeof(struct thread_info)) || 27 if (fp < (thread_base + sizeof(struct thread_info)) ||
@@ -27,11 +29,19 @@ void save_stack_trace(struct stack_trace *trace)
27 break; 29 break;
28 30
29 rw = (struct reg_window *) fp; 31 rw = (struct reg_window *) fp;
32 regs = (struct pt_regs *) (rw + 1);
33
34 if ((regs->magic & ~0x1ff) == PT_REGS_MAGIC) {
35 pc = regs->tpc;
36 fp = regs->u_regs[UREG_I6] + STACK_BIAS;
37 } else {
38 pc = rw->ins[7];
39 fp = rw->ins[6] + STACK_BIAS;
40 }
41
30 if (trace->skip > 0) 42 if (trace->skip > 0)
31 trace->skip--; 43 trace->skip--;
32 else 44 else
33 trace->entries[trace->nr_entries++] = rw->ins[7]; 45 trace->entries[trace->nr_entries++] = pc;
34
35 fp = rw->ins[6] + STACK_BIAS;
36 } while (trace->nr_entries < trace->max_entries); 46 } while (trace->nr_entries < trace->max_entries);
37} 47}
diff --git a/arch/sparc64/kernel/sun4v_tlb_miss.S b/arch/sparc64/kernel/sun4v_tlb_miss.S
index fd9430562e0b..e1fbf8c75787 100644
--- a/arch/sparc64/kernel/sun4v_tlb_miss.S
+++ b/arch/sparc64/kernel/sun4v_tlb_miss.S
@@ -262,7 +262,7 @@ sun4v_iacc:
262 mov %l5, %o2 262 mov %l5, %o2
263 call sun4v_insn_access_exception 263 call sun4v_insn_access_exception
264 add %sp, PTREGS_OFF, %o0 264 add %sp, PTREGS_OFF, %o0
265 ba,a,pt %xcc, rtrap_clr_l6 265 ba,a,pt %xcc, rtrap
266 266
267 /* Instruction Access Exception, tl1. */ 267 /* Instruction Access Exception, tl1. */
268sun4v_iacc_tl1: 268sun4v_iacc_tl1:
@@ -278,7 +278,7 @@ sun4v_iacc_tl1:
278 mov %l5, %o2 278 mov %l5, %o2
279 call sun4v_insn_access_exception_tl1 279 call sun4v_insn_access_exception_tl1
280 add %sp, PTREGS_OFF, %o0 280 add %sp, PTREGS_OFF, %o0
281 ba,a,pt %xcc, rtrap_clr_l6 281 ba,a,pt %xcc, rtrap
282 282
283 /* Data Access Exception, tl0. */ 283 /* Data Access Exception, tl0. */
284sun4v_dacc: 284sun4v_dacc:
@@ -294,7 +294,7 @@ sun4v_dacc:
294 mov %l5, %o2 294 mov %l5, %o2
295 call sun4v_data_access_exception 295 call sun4v_data_access_exception
296 add %sp, PTREGS_OFF, %o0 296 add %sp, PTREGS_OFF, %o0
297 ba,a,pt %xcc, rtrap_clr_l6 297 ba,a,pt %xcc, rtrap
298 298
299 /* Data Access Exception, tl1. */ 299 /* Data Access Exception, tl1. */
300sun4v_dacc_tl1: 300sun4v_dacc_tl1:
@@ -310,7 +310,7 @@ sun4v_dacc_tl1:
310 mov %l5, %o2 310 mov %l5, %o2
311 call sun4v_data_access_exception_tl1 311 call sun4v_data_access_exception_tl1
312 add %sp, PTREGS_OFF, %o0 312 add %sp, PTREGS_OFF, %o0
313 ba,a,pt %xcc, rtrap_clr_l6 313 ba,a,pt %xcc, rtrap
314 314
315 /* Memory Address Unaligned. */ 315 /* Memory Address Unaligned. */
316sun4v_mna: 316sun4v_mna:
@@ -344,7 +344,7 @@ sun4v_mna:
344 mov %l5, %o2 344 mov %l5, %o2
345 call sun4v_do_mna 345 call sun4v_do_mna
346 add %sp, PTREGS_OFF, %o0 346 add %sp, PTREGS_OFF, %o0
347 ba,a,pt %xcc, rtrap_clr_l6 347 ba,a,pt %xcc, rtrap
348 348
349 /* Privileged Action. */ 349 /* Privileged Action. */
350sun4v_privact: 350sun4v_privact:
@@ -352,7 +352,7 @@ sun4v_privact:
352 rd %pc, %g7 352 rd %pc, %g7
353 call do_privact 353 call do_privact
354 add %sp, PTREGS_OFF, %o0 354 add %sp, PTREGS_OFF, %o0
355 ba,a,pt %xcc, rtrap_clr_l6 355 ba,a,pt %xcc, rtrap
356 356
357 /* Unaligned ldd float, tl0. */ 357 /* Unaligned ldd float, tl0. */
358sun4v_lddfmna: 358sun4v_lddfmna:
@@ -368,7 +368,7 @@ sun4v_lddfmna:
368 mov %l5, %o2 368 mov %l5, %o2
369 call handle_lddfmna 369 call handle_lddfmna
370 add %sp, PTREGS_OFF, %o0 370 add %sp, PTREGS_OFF, %o0
371 ba,a,pt %xcc, rtrap_clr_l6 371 ba,a,pt %xcc, rtrap
372 372
373 /* Unaligned std float, tl0. */ 373 /* Unaligned std float, tl0. */
374sun4v_stdfmna: 374sun4v_stdfmna:
@@ -384,7 +384,7 @@ sun4v_stdfmna:
384 mov %l5, %o2 384 mov %l5, %o2
385 call handle_stdfmna 385 call handle_stdfmna
386 add %sp, PTREGS_OFF, %o0 386 add %sp, PTREGS_OFF, %o0
387 ba,a,pt %xcc, rtrap_clr_l6 387 ba,a,pt %xcc, rtrap
388 388
389#define BRANCH_ALWAYS 0x10680000 389#define BRANCH_ALWAYS 0x10680000
390#define NOP 0x01000000 390#define NOP 0x01000000
diff --git a/arch/sparc64/kernel/sys_sparc.c b/arch/sparc64/kernel/sys_sparc.c
index 73ed01ba40dc..8d4761f15fa9 100644
--- a/arch/sparc64/kernel/sys_sparc.c
+++ b/arch/sparc64/kernel/sys_sparc.c
@@ -454,8 +454,8 @@ asmlinkage long sys_ipc(unsigned int call, int first, unsigned long second,
454 err = sys_semget(first, (int)second, (int)third); 454 err = sys_semget(first, (int)second, (int)third);
455 goto out; 455 goto out;
456 case SEMCTL: { 456 case SEMCTL: {
457 err = sys_semctl(first, third, 457 err = sys_semctl(first, second,
458 (int)second | IPC_64, 458 (int)third | IPC_64,
459 (union semun) ptr); 459 (union semun) ptr);
460 goto out; 460 goto out;
461 } 461 }
diff --git a/arch/sparc64/kernel/sys_sparc32.c b/arch/sparc64/kernel/sys_sparc32.c
index c1a61e98899a..161ce4710fe7 100644
--- a/arch/sparc64/kernel/sys_sparc32.c
+++ b/arch/sparc64/kernel/sys_sparc32.c
@@ -554,10 +554,8 @@ asmlinkage long compat_sys_sigaction(int sig, struct old_sigaction32 __user *act
554 struct k_sigaction new_ka, old_ka; 554 struct k_sigaction new_ka, old_ka;
555 int ret; 555 int ret;
556 556
557 if (sig < 0) { 557 WARN_ON_ONCE(sig >= 0);
558 set_thread_flag(TIF_NEWSIGNALS); 558 sig = -sig;
559 sig = -sig;
560 }
561 559
562 if (act) { 560 if (act) {
563 compat_old_sigset_t mask; 561 compat_old_sigset_t mask;
@@ -601,11 +599,6 @@ asmlinkage long compat_sys_rt_sigaction(int sig,
601 if (sigsetsize != sizeof(compat_sigset_t)) 599 if (sigsetsize != sizeof(compat_sigset_t))
602 return -EINVAL; 600 return -EINVAL;
603 601
604 /* All tasks which use RT signals (effectively) use
605 * new style signals.
606 */
607 set_thread_flag(TIF_NEWSIGNALS);
608
609 if (act) { 602 if (act) {
610 u32 u_handler, u_restorer; 603 u32 u_handler, u_restorer;
611 604
diff --git a/arch/sparc64/kernel/syscalls.S b/arch/sparc64/kernel/syscalls.S
new file mode 100644
index 000000000000..db19ed67acf6
--- /dev/null
+++ b/arch/sparc64/kernel/syscalls.S
@@ -0,0 +1,279 @@
1 /* SunOS's execv() call only specifies the argv argument, the
2 * environment settings are the same as the calling processes.
3 */
4sys_execve:
5 sethi %hi(sparc_execve), %g1
6 ba,pt %xcc, execve_merge
7 or %g1, %lo(sparc_execve), %g1
8
9#ifdef CONFIG_COMPAT
10sunos_execv:
11 stx %g0, [%sp + PTREGS_OFF + PT_V9_I2]
12sys32_execve:
13 sethi %hi(sparc32_execve), %g1
14 or %g1, %lo(sparc32_execve), %g1
15#endif
16
17execve_merge:
18 flushw
19 jmpl %g1, %g0
20 add %sp, PTREGS_OFF, %o0
21
22 .align 32
23sys_pipe:
24 ba,pt %xcc, sparc_pipe
25 add %sp, PTREGS_OFF, %o0
26sys_nis_syscall:
27 ba,pt %xcc, c_sys_nis_syscall
28 add %sp, PTREGS_OFF, %o0
29sys_memory_ordering:
30 ba,pt %xcc, sparc_memory_ordering
31 add %sp, PTREGS_OFF, %o1
32sys_sigaltstack:
33 ba,pt %xcc, do_sigaltstack
34 add %i6, STACK_BIAS, %o2
35#ifdef CONFIG_COMPAT
36sys32_sigstack:
37 ba,pt %xcc, do_sys32_sigstack
38 mov %i6, %o2
39sys32_sigaltstack:
40 ba,pt %xcc, do_sys32_sigaltstack
41 mov %i6, %o2
42#endif
43 .align 32
44#ifdef CONFIG_COMPAT
45sys32_sigreturn:
46 add %sp, PTREGS_OFF, %o0
47 call do_sigreturn32
48 add %o7, 1f-.-4, %o7
49 nop
50#endif
51sys_rt_sigreturn:
52 add %sp, PTREGS_OFF, %o0
53 call do_rt_sigreturn
54 add %o7, 1f-.-4, %o7
55 nop
56#ifdef CONFIG_COMPAT
57sys32_rt_sigreturn:
58 add %sp, PTREGS_OFF, %o0
59 call do_rt_sigreturn32
60 add %o7, 1f-.-4, %o7
61 nop
62#endif
63 .align 32
641: ldx [%g6 + TI_FLAGS], %l5
65 andcc %l5, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
66 be,pt %icc, rtrap
67 nop
68 add %sp, PTREGS_OFF, %o0
69 call syscall_trace
70 mov 1, %o1
71 ba,pt %xcc, rtrap
72 nop
73
74 /* This is how fork() was meant to be done, 8 instruction entry.
75 *
76 * I questioned the following code briefly, let me clear things
77 * up so you must not reason on it like I did.
78 *
79 * Know the fork_kpsr etc. we use in the sparc32 port? We don't
80 * need it here because the only piece of window state we copy to
81 * the child is the CWP register. Even if the parent sleeps,
82 * we are safe because we stuck it into pt_regs of the parent
83 * so it will not change.
84 *
85 * XXX This raises the question, whether we can do the same on
86 * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The
87 * XXX answer is yes. We stick fork_kpsr in UREG_G0 and
88 * XXX fork_kwim in UREG_G1 (global registers are considered
89 * XXX volatile across a system call in the sparc ABI I think
90 * XXX if it isn't we can use regs->y instead, anyone who depends
91 * XXX upon the Y register being preserved across a fork deserves
92 * XXX to lose).
93 *
94 * In fact we should take advantage of that fact for other things
95 * during system calls...
96 */
97 .align 32
98sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */
99 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0
100 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0
101 ba,pt %xcc, sys_clone
102sys_fork:
103 clr %o1
104 mov SIGCHLD, %o0
105sys_clone:
106 flushw
107 movrz %o1, %fp, %o1
108 mov 0, %o3
109 ba,pt %xcc, sparc_do_fork
110 add %sp, PTREGS_OFF, %o2
111
112 .globl ret_from_syscall
113ret_from_syscall:
114 /* Clear current_thread_info()->new_child, and
115 * check performance counter stuff too.
116 */
117 stb %g0, [%g6 + TI_NEW_CHILD]
118 ldx [%g6 + TI_FLAGS], %l0
119 call schedule_tail
120 mov %g7, %o0
121 andcc %l0, _TIF_PERFCTR, %g0
122 be,pt %icc, 1f
123 nop
124 ldx [%g6 + TI_PCR], %o7
125 wr %g0, %o7, %pcr
126
127 /* Blackbird errata workaround. See commentary in
128 * smp.c:smp_percpu_timer_interrupt() for more
129 * information.
130 */
131 ba,pt %xcc, 99f
132 nop
133
134 .align 64
13599: wr %g0, %g0, %pic
136 rd %pic, %g0
137
1381: ba,pt %xcc, ret_sys_call
139 ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0
140
141 .globl sparc_exit
142 .type sparc_exit,#function
143sparc_exit:
144 rdpr %pstate, %g2
145 wrpr %g2, PSTATE_IE, %pstate
146 rdpr %otherwin, %g1
147 rdpr %cansave, %g3
148 add %g3, %g1, %g3
149 wrpr %g3, 0x0, %cansave
150 wrpr %g0, 0x0, %otherwin
151 wrpr %g2, 0x0, %pstate
152 ba,pt %xcc, sys_exit
153 stb %g0, [%g6 + TI_WSAVED]
154 .size sparc_exit,.-sparc_exit
155
156linux_sparc_ni_syscall:
157 sethi %hi(sys_ni_syscall), %l7
158 ba,pt %xcc, 4f
159 or %l7, %lo(sys_ni_syscall), %l7
160
161linux_syscall_trace32:
162 add %sp, PTREGS_OFF, %o0
163 call syscall_trace
164 clr %o1
165 srl %i0, 0, %o0
166 srl %i4, 0, %o4
167 srl %i1, 0, %o1
168 srl %i2, 0, %o2
169 ba,pt %xcc, 2f
170 srl %i3, 0, %o3
171
172linux_syscall_trace:
173 add %sp, PTREGS_OFF, %o0
174 call syscall_trace
175 clr %o1
176 mov %i0, %o0
177 mov %i1, %o1
178 mov %i2, %o2
179 mov %i3, %o3
180 b,pt %xcc, 2f
181 mov %i4, %o4
182
183
184 /* Linux 32-bit system calls enter here... */
185 .align 32
186 .globl linux_sparc_syscall32
187linux_sparc_syscall32:
188 /* Direct access to user regs, much faster. */
189 cmp %g1, NR_SYSCALLS ! IEU1 Group
190 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
191 srl %i0, 0, %o0 ! IEU0
192 sll %g1, 2, %l4 ! IEU0 Group
193 srl %i4, 0, %o4 ! IEU1
194 lduw [%l7 + %l4], %l7 ! Load
195 srl %i1, 0, %o1 ! IEU0 Group
196 ldx [%g6 + TI_FLAGS], %l0 ! Load
197
198 srl %i5, 0, %o5 ! IEU1
199 srl %i2, 0, %o2 ! IEU0 Group
200 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
201 bne,pn %icc, linux_syscall_trace32 ! CTI
202 mov %i0, %l5 ! IEU1
203 call %l7 ! CTI Group brk forced
204 srl %i3, 0, %o3 ! IEU0
205 ba,a,pt %xcc, 3f
206
207 /* Linux native system calls enter here... */
208 .align 32
209 .globl linux_sparc_syscall
210linux_sparc_syscall:
211 /* Direct access to user regs, much faster. */
212 cmp %g1, NR_SYSCALLS ! IEU1 Group
213 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
214 mov %i0, %o0 ! IEU0
215 sll %g1, 2, %l4 ! IEU0 Group
216 mov %i1, %o1 ! IEU1
217 lduw [%l7 + %l4], %l7 ! Load
2184: mov %i2, %o2 ! IEU0 Group
219 ldx [%g6 + TI_FLAGS], %l0 ! Load
220
221 mov %i3, %o3 ! IEU1
222 mov %i4, %o4 ! IEU0 Group
223 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
224 bne,pn %icc, linux_syscall_trace ! CTI Group
225 mov %i0, %l5 ! IEU0
2262: call %l7 ! CTI Group brk forced
227 mov %i5, %o5 ! IEU0
228 nop
229
2303: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
231ret_sys_call:
232 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
233 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc
234 sra %o0, 0, %o0
235 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
236 sllx %g2, 32, %g2
237
238 /* Check if force_successful_syscall_return()
239 * was invoked.
240 */
241 ldub [%g6 + TI_SYS_NOERROR], %l2
242 brnz,a,pn %l2, 80f
243 stb %g0, [%g6 + TI_SYS_NOERROR]
244
245 cmp %o0, -ERESTART_RESTARTBLOCK
246 bgeu,pn %xcc, 1f
247 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
24880:
249 /* System call success, clear Carry condition code. */
250 andn %g3, %g2, %g3
251 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
252 bne,pn %icc, linux_syscall_trace2
253 add %l1, 0x4, %l2 ! npc = npc+4
254 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
255 ba,pt %xcc, rtrap
256 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
257
2581:
259 /* System call failure, set Carry condition code.
260 * Also, get abs(errno) to return to the process.
261 */
262 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
263 sub %g0, %o0, %o0
264 or %g3, %g2, %g3
265 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
266 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
267 bne,pn %icc, linux_syscall_trace2
268 add %l1, 0x4, %l2 ! npc = npc+4
269 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
270
271 b,pt %xcc, rtrap
272 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
273linux_syscall_trace2:
274 add %sp, PTREGS_OFF, %o0
275 call syscall_trace
276 mov 1, %o1
277 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
278 ba,pt %xcc, rtrap
279 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
diff --git a/arch/sparc64/kernel/sysfs.c b/arch/sparc64/kernel/sysfs.c
index 52816c7be0b9..e885034a6b73 100644
--- a/arch/sparc64/kernel/sysfs.c
+++ b/arch/sparc64/kernel/sysfs.c
@@ -273,10 +273,22 @@ static void __init check_mmu_stats(void)
273 mmu_stats_supported = 1; 273 mmu_stats_supported = 1;
274} 274}
275 275
276static void register_nodes(void)
277{
278#ifdef CONFIG_NUMA
279 int i;
280
281 for (i = 0; i < MAX_NUMNODES; i++)
282 register_one_node(i);
283#endif
284}
285
276static int __init topology_init(void) 286static int __init topology_init(void)
277{ 287{
278 int cpu; 288 int cpu;
279 289
290 register_nodes();
291
280 check_mmu_stats(); 292 check_mmu_stats();
281 293
282 register_cpu_notifier(&sysfs_cpu_nb); 294 register_cpu_notifier(&sysfs_cpu_nb);
diff --git a/arch/sparc64/kernel/traps.c b/arch/sparc64/kernel/traps.c
index 96da847023f3..d9b8d46707d1 100644
--- a/arch/sparc64/kernel/traps.c
+++ b/arch/sparc64/kernel/traps.c
@@ -2091,9 +2091,8 @@ static void user_instruction_dump(unsigned int __user *pc)
2091 2091
2092void show_stack(struct task_struct *tsk, unsigned long *_ksp) 2092void show_stack(struct task_struct *tsk, unsigned long *_ksp)
2093{ 2093{
2094 unsigned long pc, fp, thread_base, ksp; 2094 unsigned long fp, thread_base, ksp;
2095 struct thread_info *tp; 2095 struct thread_info *tp;
2096 struct reg_window *rw;
2097 int count = 0; 2096 int count = 0;
2098 2097
2099 ksp = (unsigned long) _ksp; 2098 ksp = (unsigned long) _ksp;
@@ -2117,15 +2116,27 @@ void show_stack(struct task_struct *tsk, unsigned long *_ksp)
2117 printk("\n"); 2116 printk("\n");
2118#endif 2117#endif
2119 do { 2118 do {
2119 struct reg_window *rw;
2120 struct pt_regs *regs;
2121 unsigned long pc;
2122
2120 /* Bogus frame pointer? */ 2123 /* Bogus frame pointer? */
2121 if (fp < (thread_base + sizeof(struct thread_info)) || 2124 if (fp < (thread_base + sizeof(struct thread_info)) ||
2122 fp >= (thread_base + THREAD_SIZE)) 2125 fp >= (thread_base + THREAD_SIZE))
2123 break; 2126 break;
2124 rw = (struct reg_window *)fp; 2127 rw = (struct reg_window *)fp;
2125 pc = rw->ins[7]; 2128 regs = (struct pt_regs *) (rw + 1);
2129
2130 if ((regs->magic & ~0x1ff) == PT_REGS_MAGIC) {
2131 pc = regs->tpc;
2132 fp = regs->u_regs[UREG_I6] + STACK_BIAS;
2133 } else {
2134 pc = rw->ins[7];
2135 fp = rw->ins[6] + STACK_BIAS;
2136 }
2137
2126 printk(" [%016lx] ", pc); 2138 printk(" [%016lx] ", pc);
2127 print_symbol("%s\n", pc); 2139 print_symbol("%s\n", pc);
2128 fp = rw->ins[6] + STACK_BIAS;
2129 } while (++count < 16); 2140 } while (++count < 16);
2130#ifndef CONFIG_KALLSYMS 2141#ifndef CONFIG_KALLSYMS
2131 printk("\n"); 2142 printk("\n");
diff --git a/arch/sparc64/kernel/tsb.S b/arch/sparc64/kernel/tsb.S
index 10adb2fb8ffe..c499214b501d 100644
--- a/arch/sparc64/kernel/tsb.S
+++ b/arch/sparc64/kernel/tsb.S
@@ -275,7 +275,7 @@ sparc64_realfault_common:
275 stx %l5, [%g6 + TI_FAULT_ADDR] ! Save fault address 275 stx %l5, [%g6 + TI_FAULT_ADDR] ! Save fault address
276 call do_sparc64_fault ! Call fault handler 276 call do_sparc64_fault ! Call fault handler
277 add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg 277 add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg
278 ba,pt %xcc, rtrap_clr_l6 ! Restore cpu state 278 ba,pt %xcc, rtrap ! Restore cpu state
279 nop ! Delay slot (fill me) 279 nop ! Delay slot (fill me)
280 280
281winfix_trampoline: 281winfix_trampoline:
diff --git a/arch/sparc64/kernel/ttable.S b/arch/sparc64/kernel/ttable.S
index b0de4c00b11a..450053af039e 100644
--- a/arch/sparc64/kernel/ttable.S
+++ b/arch/sparc64/kernel/ttable.S
@@ -153,7 +153,7 @@ tl0_resv164: BTRAP(0x164) BTRAP(0x165) BTRAP(0x166) BTRAP(0x167) BTRAP(0x168)
153tl0_resv169: BTRAP(0x169) BTRAP(0x16a) BTRAP(0x16b) BTRAP(0x16c) 153tl0_resv169: BTRAP(0x169) BTRAP(0x16a) BTRAP(0x16b) BTRAP(0x16c)
154tl0_linux64: LINUX_64BIT_SYSCALL_TRAP 154tl0_linux64: LINUX_64BIT_SYSCALL_TRAP
155tl0_gsctx: TRAP(sparc64_get_context) TRAP(sparc64_set_context) 155tl0_gsctx: TRAP(sparc64_get_context) TRAP(sparc64_set_context)
156tl0_resv170: KPROBES_TRAP(0x170) KPROBES_TRAP(0x171) BTRAP(0x172) 156tl0_resv170: KPROBES_TRAP(0x170) KPROBES_TRAP(0x171) KGDB_TRAP(0x172)
157tl0_resv173: BTRAP(0x173) BTRAP(0x174) BTRAP(0x175) BTRAP(0x176) BTRAP(0x177) 157tl0_resv173: BTRAP(0x173) BTRAP(0x174) BTRAP(0x175) BTRAP(0x176) BTRAP(0x177)
158tl0_resv178: BTRAP(0x178) BTRAP(0x179) BTRAP(0x17a) BTRAP(0x17b) BTRAP(0x17c) 158tl0_resv178: BTRAP(0x178) BTRAP(0x179) BTRAP(0x17a) BTRAP(0x17b) BTRAP(0x17c)
159tl0_resv17d: BTRAP(0x17d) BTRAP(0x17e) BTRAP(0x17f) 159tl0_resv17d: BTRAP(0x17d) BTRAP(0x17e) BTRAP(0x17f)
diff --git a/arch/sparc64/kernel/utrap.S b/arch/sparc64/kernel/utrap.S
new file mode 100644
index 000000000000..b7f0f3f3a909
--- /dev/null
+++ b/arch/sparc64/kernel/utrap.S
@@ -0,0 +1,29 @@
1 .globl utrap_trap
2 .type utrap_trap,#function
3utrap_trap: /* %g3=handler,%g4=level */
4 TRAP_LOAD_THREAD_REG(%g6, %g1)
5 ldx [%g6 + TI_UTRAPS], %g1
6 brnz,pt %g1, invoke_utrap
7 nop
8
9 ba,pt %xcc, etrap
10 rd %pc, %g7
11 mov %l4, %o1
12 call bad_trap
13 add %sp, PTREGS_OFF, %o0
14 ba,pt %xcc, rtrap
15 nop
16
17invoke_utrap:
18 sllx %g3, 3, %g3
19 ldx [%g1 + %g3], %g1
20 save %sp, -128, %sp
21 rdpr %tstate, %l6
22 rdpr %cwp, %l7
23 andn %l6, TSTATE_CWP, %l6
24 wrpr %l6, %l7, %tstate
25 rdpr %tpc, %l6
26 rdpr %tnpc, %l7
27 wrpr %g1, 0, %tnpc
28 done
29 .size utrap_trap,.-utrap_trap
diff --git a/arch/sparc64/kernel/winfixup.S b/arch/sparc64/kernel/winfixup.S
index c4aa110a10e5..a6b0863c27df 100644
--- a/arch/sparc64/kernel/winfixup.S
+++ b/arch/sparc64/kernel/winfixup.S
@@ -32,7 +32,7 @@ fill_fixup:
32 rd %pc, %g7 32 rd %pc, %g7
33 call do_sparc64_fault 33 call do_sparc64_fault
34 add %sp, PTREGS_OFF, %o0 34 add %sp, PTREGS_OFF, %o0
35 ba,pt %xcc, rtrap_clr_l6 35 ba,pt %xcc, rtrap
36 nop 36 nop
37 37
38 /* Be very careful about usage of the trap globals here. 38 /* Be very careful about usage of the trap globals here.
@@ -100,7 +100,7 @@ spill_fixup_dax:
100 rd %pc, %g7 100 rd %pc, %g7
101 call do_sparc64_fault 101 call do_sparc64_fault
102 add %sp, PTREGS_OFF, %o0 102 add %sp, PTREGS_OFF, %o0
103 ba,a,pt %xcc, rtrap_clr_l6 103 ba,a,pt %xcc, rtrap
104 104
105winfix_mna: 105winfix_mna:
106 andn %g3, 0x7f, %g3 106 andn %g3, 0x7f, %g3
@@ -122,12 +122,12 @@ fill_fixup_mna:
122 mov %l4, %o2 122 mov %l4, %o2
123 call sun4v_do_mna 123 call sun4v_do_mna
124 mov %l5, %o1 124 mov %l5, %o1
125 ba,a,pt %xcc, rtrap_clr_l6 125 ba,a,pt %xcc, rtrap
1261: mov %l4, %o1 1261: mov %l4, %o1
127 mov %l5, %o2 127 mov %l5, %o2
128 call mem_address_unaligned 128 call mem_address_unaligned
129 nop 129 nop
130 ba,a,pt %xcc, rtrap_clr_l6 130 ba,a,pt %xcc, rtrap
131 131
132winfix_dax: 132winfix_dax:
133 andn %g3, 0x7f, %g3 133 andn %g3, 0x7f, %g3
@@ -150,7 +150,7 @@ fill_fixup_dax:
150 add %sp, PTREGS_OFF, %o0 150 add %sp, PTREGS_OFF, %o0
151 call sun4v_data_access_exception 151 call sun4v_data_access_exception
152 nop 152 nop
153 ba,a,pt %xcc, rtrap_clr_l6 153 ba,a,pt %xcc, rtrap
1541: call spitfire_data_access_exception 1541: call spitfire_data_access_exception
155 nop 155 nop
156 ba,a,pt %xcc, rtrap_clr_l6 156 ba,a,pt %xcc, rtrap
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-09 09:23:47 -0400